ACPL-P314 and ACPL-W Amp Output Current IGBT Gate Driver Optocoupler. Features. Specifications

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Scott Robinson
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consists of a GaAsP LED optically coupled to an integrated circuit with a power output stage.

The high operating voltage range of the output stage provides the drive voltages required by gate controlled devices.

1 ACPL-P and ACPL-W 0. Amp Output Current IGBT Gate Driver Optocoupler Data Sheet Lead (Pb) Free RoHS fully compliant RoHS fully compliant options available; -xxxe denotes a lead-free product Description The ACPL-P/W consists of a GaAsP LED optically coupled to an integrated circuit with a power output stage. These optocouplers are ideally suited for driving power IGBTs and MOSFETs used in motor control inverter applications. The high operating voltage range of the output stage provides the drive voltages required by gate controlled devices. The voltage and current supplied by this optocoupler makes it ideally suited for directly driving small or medium power IGBTs. Applications Isolated IGBT/Power MOSFET gate drive AC and brushless DC motor drives Industrial inverters Inverter for home appliances Induction cooker Switching Power Supplies (SPS) Functional Diagram ANODE N.C. CATHODE SHIELD V CC V O V EE Features High speed response. Ultra high CMR. Bootstrappable supply current. Available in Stretched SO- package Package Clearance/Creepage at 8mm (ACPL-W) Safety Approval: UL Recognized with 70 V rms for minute per UL77. CSA Approved. IEC/EN/DIN EN Approved with V IORM = 0V PEAK for option 00. Specifications 0. A maximum peak output current. 0. A minimum peak output current. 0.7 µs maximum propagation delay over temperature range. I CC(max) = ma maximum supply current. 0 kv/µs minimum common mode rejection (CMR) at V CM = 000 V. Wide V CC operating range: 0 V to 0 V over temperature range. Wide operating temperature range: 0 C to 00 C. Truth Table LED VO OFF LOW ON HIGH Note: A 0. µf bypass capacitor must be connected between pins V CC and VEE. CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD.

2 Ordering Information ACPL-P and ACPL-W are UL Recognized with 70 Vrms for minute per UL77. Part number ACPL-P ACPL-W Option RoHS Compliant -000E Package Surface Mount X Tape & Reel IEC/EN/DIN EN Quantity 00 per tube -00E X X 000 per reel Stretched SO- -00E X X 00 per tube -0E X X X 000 per reel To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. Example : ACPL-P-0E to order product of Stretched SO- Surface Mount package in Tape and Reel packaging with IEC/EN/DIN EN Safety Approval in RoHS compliant. Example : ACPL-P-000E to order product of Stretched SO- Surface Mount package in tube packaging and RoHS compliant. Option datasheets are available. Contact your Avago sales representative or authorized distributor for information. Remarks: The notation #XXX is used for existing products, while (new) products launched since th July 00 and RoHS compliant option will use -XXXE. Package Outline Drawings ACPL-P Stretched SO- Package, 7 mm clearance 0.8±0.7 [.0±.00].7[.00] BSG Land Pattern Recommendation 0.7[.].[.08] ±0.7.8 [.0±.00] [.008] A ±.0.0 [.00±.00] 0.0±0.0 [.008±.00] 9.7±0.0 [.8±.00] ±0.7 [.±.00] Dimensions in Millimeters [Inches] Coplanarity = 0.mm [0.00 inches]

3 ACPL-W Stretched SO- Package Recommended Solder Reflow Temperature Profile Note: Non-halide flux should be used

4 Recommended Pb-Free IR Profile Note: Non-halide flux should be used Regulatory Information The ACPL-P/W is pending approval by the following organizations: IEC/EN/DIN EN (Option 00 only) Approval under: IEC :997 + A:00 EN 077--:00 + A:00 DIN EN (VDE 088 Teil ):00-0 UL Approval under UL 77, component recognition program up to V ISO = 70 V RMS. File E. CSA Approval under CSA Component Acceptance Notice #, File CA 88.

5 P ACPL- W Units Table. IEC/EN/DIN EN Insulation Characteristics* (ACPL-P/W Option 00) Description Symbol Characteristic Unit Installation classification per DIN VDE 00/.89, Table for rated mains voltage 0V rms for rated mains voltage 00V rms for rated mains voltage 00V rms Climatic Classification /00/ Pollution Degree (DIN VDE 00/.89) Maximum Working Insulation Voltage V IORM 0 V peak Input to Output Test Voltage, Method b*v IORM x.87=v PR, 00% Production Test with t m = sec, Partial discharge < pc Input to Output Test Voltage, Method a*v IORM x.=v PR, Type and Sample Test, t m =0 sec, Partial discharge < pc I - IV I - III I - II V PR 8 V peak V PR 9 V peak Highest Allowable Overvoltage (Transient Overvoltage t ini = 0 sec) V IOTM 000 V peak Safety-limiting values - maximum values allowed in the event of a failure. Case Temperature Input Current** Output Power** T S I S, INPUT P S, OUTPUT Insulation Resistance at T S, V IO = 00 V R S > C ma mw * Refer to the optocoupler section of the Isolation and Control Components Designer s Catalog, under Product Safety Regulations section, (IEC/EN/DIN EN 077--) for a detailed description of Method a and Method b partial discharge test profiles. ** Refer to the following figure for dependence of P S and I S on ambient temperature. Table. Insulation and Safety Related Specifications Parameter Minimum External Air Gap (External Clearance) Minimum External Tracking (External Creepage) Minimum Internal Plastic Gap (Internal Clearance) Minimum Internal Tracking (Internal Creepage) Tracking Resistance (Comparative Tracking Index) Symbol Conditions L(0) mm Measured from input terminals to output terminals, shortest distance through air. L(0) mm Measured from input terminals to output terminals, shortest distance path along body mm Through insulation distance conductor to conductor, usually the straight line distance thickness between the emitter and detector. NA NA mm Measured from input terminals to output terminals, along internal cavity. CTI >7 >7 V DIN IEC /VDE 00 Part Isolation Group IIIa IIIa Material Group (DIN VDE 00, /89, Table )

6 Table. Absolute Maximum Ratings Parameter Symbol Min. Max. Units Note Storage Temperature T S - C Operating Temperature T A C Average Input Current I F(AVG) ma Peak Transient Input Current (< µs pulse width, 00pps) I F(TRAN).0 A Reverse Input Voltage V R V High Peak Output Current I OH(PEAK) 0. A Low Peak Output Current I OL(PEAK) 0. A Supply Voltage V CC - V EE -0. V Output Voltage V O(PEAK) -0. V CC V Output Power Dissipation P O 0 mw Input Power Dissipation P I mw Lead Solder Temperature Solder Reflow Temperature Profile 0 C for 0 sec.,. mm below seating plane See Package Outline Drawings section Table. Recommended Operating Conditions Parameter Symbol Min. Max. Units Note Power Supply V CC - V EE 0 0 V Input Current (ON) I F(ON) 8 ma Input Voltage (OFF) V F(OFF) V Operating Temperature T A C Table. Electrical Specifications (DC) Over recommended operating conditions unless otherwise specified. Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note High Level Output Current I OH 0. A V O = V CC A V O = V CC - 0 Low Level Output Current I OL A V O = V EE A V O = V EE + 0 High Level Output Voltage V OH V CC - V CC -.8 V I O = -00 ma, 7 Low Level Output Voltage V OL 0. V I O = 00 ma High Level Supply Current I CCH 0.7 ma I O = 0 ma 7, 8 Low Level Supply Current I CCL. ma I O = 0 ma 7, 8 Threshold Input Current Low to High Threshold Input Voltage High to Low I FLH 7 ma I O = 0 ma, V O > V 9, V FHL 0.8 V I O = 0 ma, V O > V Input Forward Voltage V F...8 V I F = 0 ma Temperature Coefficient of Input Forward Voltage DV F /DT A -. mv/ C I F = 0 ma Input Reverse Breakdown Voltage BV R V I R = 0 µa Input Capacitance C IN 0 pf f = MHz, V F = 0 V

7 Table. Switching Specifications (AC) Over recommended operating conditions unless otherwise specified. Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note Propagation Delay Time to High Output Level Propagation Delay Time to Low Output Level Propagation Delay Difference Between Any Two Parts or Channels t PLH µs R g = 7W, C g = nf, f = 0 khz, Duty Cycle = 0%, I F = 8 ma, V CC = 0 V 0,,,,, 7 t PHL µs PDD µs 0 Rise Time t R 0 ns Fall Time t F 0 ns Output High Level Common Mode Transient Immunity Output Low Level Common Mode Transient Immunity CM H 0 kv/µs T A = C, V CM = 000 V 8 CM L 0 kv/µs 8 Table 7. Package Characteristics Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note Input-Output Momentary Withstand Voltage V ISO 70 V rms T A = C,RH < 0% for min. Input-Output Resistance R I-O 0 V I-O = 00 V 9 Input-Output Capacitance C I-O 0. pf Freq= MHz 8, 9 Notes:. Derate linearly above 70 C free air temperature at a rate of 0. ma/ C.. Maximum pulse width = 0 µs, maximum duty cycle = 0.%. This value is intended to allow for component tolerances for designs with I O peak minimum = 0. A. See Application section for additional details on limiting I OL peak.. Derate linearly above 8 C, free air temperature at the rate of.0 mw/ C.. Input power dissipation does not require derating.. Maximum pulse width = 0 µs, maximum duty cycle = 0.%.. In this test, V OH is measured with a DC load current. When driving capacitive load V OH will approach V CC as I OH approaches zero amps. 7. Maximum pulse width = ms, maximum duty cycle = 0%. 8. In accordance with UL 77, each optocoupler is proof tested by applying an insulation test voltage > 00 V rms for second (leakage detection current limit I I-O < µa). This test is performed before 00% production test for partial discharge (method B) shown in the IEC/EN/DIN EN Insulation Characteristics Table, if applicable. 9. Device considered a two-terminal device: pins on input side shorted together and pins on output side shorted together. 0. PDD is the difference between t PHL and t PLH between any two parts or channels under the same test conditions.. Common mode transient immunity in the high state is the maximum tolerable dv CM /dt of the common mode pulse V CM to assure that the output will remain in the high state (i.e. V O >.0 V).. Common mode transient immunity in a low state is the maximum tolerable dv CM /dt of the common mode pulse, V CM, to assure that the output will remain in a low state (i.e. V O <.0 V).. This load condition approximates the gate load of a 00 V/ A IGBT.. The power supply current increases when operating frequency and Q g of the driven IGBT increases. 7

8 Figure. V OH vs. Temperature. Figure. I OH vs. Temperature. Figure. V OH vs. I OH. Figure. V OL vs. Temperature. Figure. I OL vs. Temperature. Figure. V OL vs. I OL. 8

9 Figure 7. I CC vs. Temperature. Figure 8. I CC vs. V CC. Figure 9. I FLH vs. Temperature. Figure 0. Propagation Delay vs. V CC. Figure. Propagation Delay vs. I F. Figure. Propagation Delay vs. Temperature. 9

10 Figure. Propagation Delay vs. Rg. Figure. Propagation Delay vs. Cg. Figure. Transfer Characteristics. Figure. Input Current vs. Forward Voltage. I F = 7 to ma 00 Ω + V O V = CC to 0 V 0 KHz 7 Ω 0% DUTY nf CYCLE 0. µf Figure 7. Propagation Delay Test Circuit and Waveforms. I F V A B 0. µf + V O V CC = 0V + - V CM = 000V Figure 8. CMR Test Circuit and Waveforms. 0

11 Applications Information Eliminating Negative IGBT Gate Drive To keep the IGBT firmly off, the ACPL-P/W has a very low maximum V OL specification of.0 V. Minimizing R g and the lead inductance from the ACPL-P/W to the IGBT gate and emitter (possibly by mounting the ACPL-P/W on a small PC board directly above the IGBT) can eliminate the need for negative IGBT gate drive in many applications as shown in Figure 9. Care should be taken with such a PC board design to avoid routing the IGBT collector or emitter traces close to the ACPL- P/W input as this can result in unwanted coupling of transient signals into the input of ACPL-P/W and degrade performance. (If the IGBT drain must be routed near the ACPL-P/W input, then the LED should be reverse biased when in the off state, to prevent the transient signals coupled from the IGBT drain from turning on the ACPL-P/W. Selecting the Gate Resistor (Rg) Step : Calculate R g minimum from the I OL peak specification. The IGBT and R g in Figure 9 can be analyzed as a simple RC circuit with a voltage supplied by the ACPL- P/W. R g VC I V OLPEAK OL = 0. = Ω The V OL value of V in the previous equation is the V OL at the peak current of 0.A. (See Figure ). Step : Check the ACPL-P/W power dissipation and increase R g if necessary. The ACPL-P/W total Figure 0. Energy Dissipated in the ACPL-P/W and for Each IGBT Switching Cycle. power dissipation (P T ) is equal to the sum of the emitter power (P E ) and the output power (P O ). P = P + P T E CCBIAS O P = I V DutyCycle E F F P = P + P = I V + E ( R ;Q ) f O O(BIAS) O(SWITCHING) C C SW g g = ( I + K Q f) V + E ( R ;Q ) f ICC g C where K ICC Q g f is the increase in I CC due to switching and K ICC is a constant of 0.00 ma/(nc*khz). For the circuit in Figure 9 with I F (worst case) = 0 ma, R g = Ω, Max Duty Cycle = 80%, Q g = 00 nc, f = 0 khz and T AMAX = 8 C: P = 0mA.8V 0.8 = mw P E O = ( ma + ( 0.00mA nc khz) 0kHz 00nC) 0.ì. 0kHz = 8mW 0mW( C) SW g g O( MAX) V + The value of ma for I CC in the previous equation is the max. I CC over entire operating temperature range. Since P O for this case is less than P O(MAX), R g = Ω is alright for the power dissipation. + V 70 Ω ACPL-P/W 0. µf + - V CC = V + HVDC CONTROL INPUT 7XXX OPEN COLLECTOR R g Q -PHASE AC Q - HVDC Figure 9. Recommended LED Drive and Application Circuit for ACPL-P/W

12 LED Drive Circuit Considerations for Ultra High CMR Performance Without a detector shield, the dominant cause of optocoupler CMR failure is capacitive coupling from the input side of the optocoupler, through the package, to the detector IC as shown in Figure. The ACPL-P/W improves CMR performance by using a detector IC with an optically transparent Faraday shield, which diverts the capacitively coupled current away from the sensitive IC circuitry. However, this shield does not eliminate the capacitive coupling between the LED and optocoupler pins -8 as shown in Figure. This capacitive coupling causes perturbations in the LED current during common mode transients and becomes the major source of CMR failures for a shielded optocoupler. The main design objective of a high CMR LED drive circuit becomes keeping the LED in the proper state (on or off ) during common mode transients. For example, the recommended application circuit (Figure 9), can achieve 0 kv/µs CMR while minimizing component complexity. Techniques to keep the LED in the proper state are discussed in the next two sections. C LEDP CMR with the LED Off (CMRL) A high CMR LED drive circuit must keep the LED off (V F V F(OFF) ) during common mode transients. For example, during a -dv CM /dt transient in Figure, the current flowing through C LEDP also flows through the R SAT and V SAT of the logic gate. As long as the low state voltage developed across the logic gate is less than V F(OFF) the LED will remain off and no common mode failure will occur. + V + V + V SAT - + V SAT - C LEDP C LEDN I LEDP SHIELD THE ARROWS INDICATE THE DIRECTION OF CURRENT FLOW DURING - dv CM / dt C LEDP C LEDN + - V CM SHIELD 0. µf 0. µf I LEDP - THE ARROWS INDICATE THE DIRECTION OF CURRENT FLOW DURING - dv CM /dt V CC = 8V + - Rg V CC = 8V Rg C LEDN + - V CM Figure. Optocoupler Input to Output Capacitance Model for Unshielded Optocouplers. C LEDP C LEDN C LED0 SHIELD C LED0 Figure. Optocoupler Input to Output Capacitance Model for Shielded Optocouplers. CMR with the LED On (CMR H ) A high CMR LED drive circuit must keep the LED on during common mode transients. This is achieved by overdriving the LED current beyond the input threshold so that it is not pulled below the threshold during a transient. A minimum LED current of 8 ma provides adequate margin over the maximum I FLH of ma to achieve 0 kv/µs CMR. Figure. Equivalent Circuit for Figure 7 During Common Mode Transient. The open collector drive circuit, shown in Figure, can not keep the LED off during a +dv CM /dt transient, since all the current flowing through CLEDN must be supplied by the LED, and it is not recommended for applications requiring ultra high CMR performance. The alternative drive circuit which like the recommended application circuit (Figure 9), does achieve ultra high CMR performance by shunting the LED in the off state. + V Q C LEDP I LEDN C LEDN SHIELD Figure. Not Recommended Open Collector Drive Circuit.

13 + V Delaying the LED signal by the maximum propagation C LEDP delay difference ensures that the minimum dead time is zero, but it does not tell a designer what the maximum dead time will be. The maximum dead time is equivalent to the difference between the maximum and minimum propagation delay difference specification as shown in C LEDN SHIELD Figure 7. The maximum dead time for the ACPL-P/ W is µs (= 0. µs - (-0. µs)) over the operating temperature range of 0 C to 00 C. Figure. Recommended LED Drive Circuit for Ultra-High CMR Dead Time and Propagation Delay Specifications. Dead Time and Propagation Delay Specifications The ACPL-P/W includes a Propagation Delay Difference (PDD) specification intended to help designers minimize dead time in their power inverter designs. Dead time is the time high and low side power transistors are off. Any overlap in Ql and Q conduction will result in large currents flowing through the power devices from the high voltage to the low-voltage motor rails. To minimize dead time in a given design, the turn on of LED should be delayed (relative to the turn off of LED) so that under worst-case conditions, transistor Q has just turned off when transistor Q turns on, as shown in Figure. The amount of delay necessary to achieve this condition is equal to the maximum value of the propagation delay difference specification, PDD max, which is specified to be 00 ns over the operating temperature range of -0 to 00 C. Figure 7. Waveforms for Dead Time. Note that the propagation delays used to calculate PDD and dead time are taken at equal temperatures and test conditions since the optocouplers under consideration are typically mounted in close proximity to each other and are switching identical IGBTs. Figure. Minimum LED Skew for Zero Dead Time. For product information and a complete list of distributors, please go to our web site: Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies, Limited, in the United States and other countries. Data subject to change. Copyright 007 Avago Technologies, Limited. All rights reserved. Obsoletes AV0-0EN AV0-08EN - April 9, 007

ACPL-P314 and ACPL-W Amp Output Current IGBT Gate Driver Optocoupler

ACPL-P314 and ACPL-W Amp Output Current IGBT Gate Driver Optocoupler .-Amp Output Current IGBT Gate Driver Optocoupler Description The ACPL-P/W consists of a GaAsP LED optically coupled to an integrated circuit with a power output stage. These optocouplers are ideally suited