Features. Note: A 0.1 F bypass capacitor must be connected between pins Vcc and Ground. Specifications. Truth Table (Negative Logic)

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1 ACPL-M483/P483/W483 Inverted Logic High CMR Intelligent Power Module and Gate Drive Interface Optocoupler Data Sheet Description The ACPL-M483/P483/W483 fast speed optocoupler contains a AlGaAs LED and photo detector with built-in Schmitt trigger to provide logic-compatible waveforms, eliminating the need for additional wave shaping. The totem pole output eliminates the need for a pull up resistor and allows for direct drive of Intelligent Power Module or as a gate driver. Minimized propagation delay difference between devices makes these optocouplers excellent solutions for improving inverter efficiency through reduced switching dead time. Applications IPM Interface Isolation Isolated IGBT/MOSFET Gate Drive AC and Brushless DC Motor Drives Industrial Inverters General Digital Isolation Functional Diagram Anode Cathode Anode N.C. Cathode 3 SHIELD 2 3 SHIELD ACPL-M483 ACPL-P483 & ACPL-W483 6 V CC V O 4 Ground 6 V CC V O 4 Ground Note: A 0. F bypass capacitor must be connected between pins Vcc and Ground. Truth Table (Negative Logic) LED V O ON LOW OFF HIGH Truth Table Guaranteed: Vcc from 4. V to 30 V Features Inverted output type (totem pole output) Truth Table Guaranteed: Vcc from 4. V to 30 V Performance Specified for Common IPM Applications Over Industrial Temperature Range. Short Maximum Propagation Delays Minimized Pulse Width Distortion (PWD) Very High Common Mode Rejection (CMR) Hysteresis Available in SO- (ACPL-M483) and Stretched SO-6 package (ACPCL-P483/W483). Package Clearance/Creepage at 8 mm (ACPL-W483) Safety Approval: UL Recognized with 000 V rms (ACPL-W483) for minute per UL77. CSA Approved. IEC/EN/DIN EN Approved with V IORM = 67 V peak for ACPL-M483 and V IORM = 89 V peak for ACPL-P483 and V IORM = 40 V peak for ACPL-W483, under option 060. Specifications Wide operating temperature range: -40 C to 0 C. Maximum propagation delay t PHL /t PLH = 20/20 ns Maximum Pulse Width Distortion (PWD) = 0 ns. Propagation Delay Difference Min/Max = 00/00 ns Wide Operating V CC Range: 4. to 30 Volts 30 kv/ s minimum common mode rejection (CMR) at V CM = 000 V. CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD.

2 Ordering Information ACPL-M483/P483/W483 is UL recognized with 370/370/000 V rms / minute rating per UL 77 respectively. Part number Option RoHS Compliant Package Surface Mount Tape & Reel IEC/EN/DIN EN Quantity ACPL-M E SO- X 00 per tube -00E X X 00 per reel -060E X X 00 per tube -60E X X X 00 per reel ACPL-P E Stretched X 00 per tube ACPL-W483-00E SO-6 X X 000 per reel -060E X X 00 per tube -60E X X X 000 per reel To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. Example : ACPL-P483-60E to order product of Stretched SO-6 Surface Mount package in Tape and Reel packaging with IEC/EN/ DIN EN Safety Approval in RoHS compliant. Example 2: ACPL-P E to order product of Stretched SO-6 Surface Mount package in Tube packaging and RoHS compliant. Example 3: ACPL-M E to order product of SO- Surface Mount package in Tube packaging and RoHS compliant. Option datasheets are available. Contact your Avago sales representative or authorized distributor for information. 2

3 Package Outline Drawings ACPL-M483 SO- Package, mm Creepage & Clearance 6 4 TYPE NUMBER (LAST 3 DIGITS) DATE CODE Land Pattern Recommendation 4.4 ± 0. (0.73 ± 0.004) MXXX XXX 7.0 ± 0.2 (0.276 ± 0.008) 2. (0.0) 4.4 (0.7).3 (0.0) ± 0.* (0.42 ± 0.004) 0.4 ± 0.0 (0.06 ± 0.002) 2.0 (0.080) 8.27 (0.32) 0.64 (0.02) 2. ± 0. (0.098 ± 0.004) 0.02 ± 0.02 (0.004 ± 0.004) 0. ± 0.02 (0.006 ± 0.00).27 (0.00) BSC 0.7 (0.028) MIN MAX. Dimensions in millimeters (inches). * Maximum Mold flash on each side is 0. mm (0.006). Note: Foating Lead Protrusion is 0. mm (6 mils) max. MAX. LEAD COPLANARITY = 0.02 (0.004) 3

4 ACPL-P483 Stretched SO-6 Package, 7 mm clearance 0.38 ±0.27 (0.0 ±0.00).27 (0.00) BSG ( ) Land Pattern Recommendation 0.64 (0.02).27 (0.0) 0.7 (0.42) 2.6 (0.08) 0.4 (0.08) (0.300) 6.8 (0.268).90 ±0.27 (0.063 ±0.00) 3.80 ±0.27 (0.2 ±0.00) 0.20 ±0.0 (0.008 ±0.004) 0.24 ±0.00 (0.00 ±0.002) ±0.20 (0.040 ±0.00) NOM. 9.7 ±0.20 (0.382 ±0.00) Floating Lead Protusions max. 0.2 (0.0) Dimensions in Millimeters (Inches) Lead Coplanarity = 0. mm (0.004 Inches) ACPL-W483 Stretched SO-6 Package, 8 mm clearance 0.38 ±0.27 (0.0 ±0.00).27 (0.00) BSG ( ) Land Pattern Recommendation 0.64 (0.02) (0.0) ( ) 7.62 (0.300) 2.6 (0.).90 (0.07) 0.4 (0.08) 4.90 ±0.27 (0.063 ±0.00) 3.80 ±0.27 (0.2 ±0.00) 0.20 ±0.0 (0.008 ±0.004) 0.70 ±0.20 (0.029 ±0.00) 0.24 ±0.00 (0.00 ±0.002) 3 NOM..00 ±0.2 (0.43 ±0.00) Floating Lead Protusions max. 0.2 (0.0) Dimensions in Millimeters (Inches) Lead Coplanarity = 0. mm (0.004 Inches) 4

5 Recommended Pb-Free IR Profile Recommended reflow condition as per JEDEC Standard, J-STD-020 (latest revision). Non-Halide Flux should be used. Regulatory Information The ACPL-M483/P483/W483 is approved by the following organizations: IEC/EN/DIN EN (Option 060 only) Approved with Maximum Working Insulation Voltage V IORM = 67 V peak for ACPL-M483, V IORM = 89 V peak for ACPL-P483, and V IORM = 40 V peak for ACPL-W483 UL Approval under UL 77, component recognition program up to V ISO = 370 V RMS File E36 for ACPL-M483 and ACPL-P483; Approval under UL 77, component recognition program up to V ISO = 000 V RMS File E36 for ACPL-W483; CSA Approval under CSA Component Acceptance Notice #, File CA Table. IEC/EN/DIN EN Insulation Characteristics* (ACPL-M483/P483/W483 Option 060) Description Symbol ACPL-M483 ACPL-P483 ACPL-W483 Unit Installation classification per DIN VDE 00/.89, Table for rated mains voltage 0 V rms for rated mains voltage 300 V rms for rated mains voltage 40 V rms for rated mains voltage 600 V rms for rated mains voltage 000 V rms Climatic Classification /0/2 /0/2 /0/2 Pollution Degree (DIN VDE 00/.89) Maximum Working Insulation Voltage V IORM V peak Input to Output Test Voltage, Method b* V IORM x.87 = V PR, 00% Production Test with t m = sec, Partial discharge < pc V PR V peak Input to Output Test Voltage, Method a* V IORM x.6 = V PR, Type and Sample Test, t m = 0 sec, Partial discharge < pc Highest Allowable Overvoltage (Transient Overvoltage t ini = 60 sec) Safety-limiting values maximum values allowed in the event of a failure. Case Temperature Input Current Output Power I III I III I III I III I III V PR V peak V IOTM V peak T S I S, INPUT P S, OUTPUT Insulation Resistance at T S, V IO = 00 V R S >0 9 >0 9 >0 9 * Refer to the optocoupler section of the Isolation and Control Components Designer s Catalog, under Product Safety Regulations section, (IEC/EN/DIN EN ) for a detailed description of Method a and Method b partial discharge test profiles C ma mw

6 Table 2. Insulation and Safety Related Specifications Parameter Symbol ACPL-M483 ACPL-P483 ACPL-W483 Units Conditions Minimum External Air Gap (External Clearance) Minimum External Tracking (External Creepage) Minimum Internal Plastic Gap (Internal Clearance) L(0) mm Measured from input terminals to output terminals, shortest distance through air. L(02) mm Measured from input terminals to output terminals, shortest distance path along body mm Through insulation distance conductor to conductor, usually the straight line distance thickness between the emitter and detector. Tracking Resistance CTI >7 >7 >7 V DIN IEC 2/VDE 0303 Part (Comparative Tracking Index) Isolation Group IIIa IIIa IIIa Material Group (DIN VDE 00, /89, Table ) Table 3. Absolute Maximum Ratings Parameter Symbol Min. Max. Units Note Storage Temperature T S - 2 C Operating Temperature T A C Average Input Current I F(avg) 0 ma Peak Transient Input Current (< s pulse width, 300 pps) (<200 s pulse width, < % duty cycle) I F(tran).0 40 Reverse Input Voltage V R V Average Output Current I O 0 ma Supply Voltage V CC 0 3 Output Voltage V O Total Package Power Dissipation (ACPL-M483) P T 4 mw Total Package Power Dissipation (Others) P T 20 mw Solder Reflow Temperature Profile See Reflow Thermal Profile. A ma Table 4. Recommended Operating Conditions Parameter Symbol Min. Max. Units Note Power Supply Voltage () V CC V 2 Forward Input Current (ON) I F(ON) 4 7 ma Forward Input Voltage (OFF) V F(OFF) 0.8 V Operating Temperature T A 40 0 C Note:. Truth Table guaranteed: 4. V to 30 V 6

7 Table. Electrical Specifications Over recommended operating conditions T A = -40 C to 0 C, V CC = +4. V to 30 V, I F(ON) = 4 ma to 7 ma, V F(OFF) = 0 V to 0.8 V, unless otherwise specified. All typical values at T A = 2 C. Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note Logic Low Output Voltage V OL 0.3 V I OL = 3. ma, 3 0. I OL = 6. ma Logic High Output Voltage V OH V CC -0.3 V CC V I OH = -3. ma 2, 3, 7 V CC -0. V CC I OH = -6. ma Logic Low Supply Current I CCL. 3.0 ma V CC =. V, I F = 7 ma, I o = 0 ma ma V CC = 20 V, I F = 7 ma, I o = 0 ma Logic High Supply Current I CCH. 3.0 ma V CC =. V, V F = 0 V, I o = 0 ma ma V CC = 30 V, V F = 0 V, I o = 0 ma Threshold Input Current, Output High to Low I FHL ma Threshold Input Voltage V FLH 0.8 V Output Low to High Logic Low Short Circuit I OSL ma V O = V CC =. V, I F = 7 ma, V O = GND 3 Output Current ma V O = V CC = 20 V, I F = 7 ma, V O = GND Logic High Short Circuit I OSH ma V CC =. V, V F = 0 V 3 Output Current ma V CC = 20 V, V F = 0 V Input Forward Voltage V F.3..7 V T A = 2 C, I F = 4 ma 4.8 V I F = 4 ma Input Reverse Breakdown BV R V I R = 0 A Voltage Input Diode Temperature Coefficient V F / T A.7 mv/ C I F = 4 ma Input Capacitance C IN 60 pf f = MHz, V F = 0 V 4 7

8 Table 6. Switching Specifications Over recommended operating conditions T A = -40 C to 0 C, V CC = +4. V to 30 V, I F(ON) = 4 ma to 7 ma, V F(OFF) = 0 V to 0.8 V, unless otherwise specified. All typicals at T A = 2 C. Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note Propagation Delay Time to Logic Low Output Level Propagation Delay Time to Logic High Output Level Pulse Width Distortion t PHL - t PLH = PWD t PHL 7 20 ns C L = 00pF, V F = 0 V I F(OFF) = 4 ma, 6, Loaded as per Fig. t PLH 7 20 ns C L = 00 pf, I F(OFF) = 4 ma V F = 0 V, 6, Loaded as per Fig. 0 ns C L = 00 pf, 6, Loaded as per Fig. Propagation Delay PDD ns C L = 00 pf, 6, 8 0 Difference Between Any 2 Parts Loaded as per Fig. Output Rise Time (0-90%) t r 6 ns Output Fall Time (90-0%) t f 6 ns Logic High Common Mode Transient Immunity Logic Low Common Mode Transient Immunity CM H 30 kv/ s V CM = 000 V, V F = 0 V, V CC = V, T A = 2 C CM L 30 kv/ s V CM = 000 V, I F = 4.0 ma, V CC = V, T A = 2 C Table 7. Package Characteristics Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note Input-Output Momentary Withstand Voltage* V ISO 370 (ACPL-M483 and P483) 000 (ACPL-W483) V rms RH < 0%, t = min. T A = 2 C Input-Output Resistance R I-O 0 2 Ohm V I-O = 00 V dc Input-Output Capacitance C I-O 0.6 pf f = MHz, V I-O = 0 V dc * The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. For the continuous voltage rating, refer to the IEC/EN/DIN EN Insulation Characteristics Table (if applicable)., 8 Inverted UVLO Figures 0a and b show typical output waveforms during Power-up and Power-down processes. Notes:. Derate total package power dissipation, PT, linearly above 70 C free-air temperature at a rate of 4.mW/ C (ACPL-P483/W483) and linearly above 8 C free-air temperature at a rate of 0.7 mw/ C (ACPL-M483). 2. Detector requires a Vcc of 4. V or higher for stable operation as output might be unstable if Vcc is lower than 4. V. Be sure to check the power ON/OFF operation other than the supply current. 3. Duration of output short circuit time should not exceed 00 s. 4. Input capacitance is measured between pin and pin 3.. Device considered a two-terminal device: pins, 2 and 3 shorted together and pins 4, and 6 shorted together. 6. The t PLH propagation delay is measured from the 0% point on the trailing edge of the input pulse to the.3 V point on the leading edge of the output pulse. The t PHL propagation delay is measured from the 0% point on the leading edge of the input pulse to the.3 V point on the trailing edge of the output pulse. Peaking capacitor, C = 20 pf must be connected as shown in Figure. 7. CM H is the maximum slew rate of the common mode voltage that can be sustained with the output voltage in the logic high state, V O > 2.0 V. CM L is the maximum slew rate of the common mode voltage that can be sustained with the output voltage in the logic low state, V O < 0.8 V. Note: Equal value split resistors (Rin/2) must be used at both ends of the LED. 8. In accordance with UL 77, each optocoupler is proof tested by applying an insulation test voltage 400 V RMS for one second (leakage detection current limit, I I-O < = A). This test is performed before the 00% production test for partial discharge (Method b) shown in the IEC/EN/DIN EN Insulation Characteristics Table, if applicable. 9. Pulse Width Distortion (PWD) is defined as t PHL - t PLH for any given device. 0. The difference of tplh and tphl between any two devices under the same test condition.. Use of a 0. F bypass capacitor connected between pins Vcc and Ground is recommended. 8

9 VOL - LOW LEVEL OUTPUT VOLTAGE - V 0.0 I F = 4 ma I O = 6. ma I O = 3. ma T A - TEMPERATURE - C Figure. Typical Logic Low Output Voltage vs. Temperature (VCC-VOH) - High Level Output Voltage - V V F = 0 V I O = -6. ma I O = -3. ma T A - TEMPERATURE - C Figure 2. Typical Logic High Output Voltage vs. Temperature Vo - OUTPUT VOLTAGE - V IFLH IFHL V CC = 4. V T A = 2 C IF - FORWARD CURRENT - ma T A = 2 C I F - INPUT CURRENT - ma Figure 3. Typical Output Voltage vs. Forward Input Current V F - FORWARD VOLTAGE - V Figure 4. Typical Input Diode Forward Characteristic INPUT MONITORING NODE PULSE GEN. t r = t f = ns f = 00 khz 0% DUTY CYCLE V o = V Z o = 0 R 2 3 SHIELD C = 20 pf 6 4 *0. μf BYPASS SEE NOTE V CC OUTPUT V o MONITORING * NODE C 2 = pf kω D V 69 Ω D2 D3 D4 INPUT I F OUTPUT V THE PROBE AND JIG CAPACITANCES ARE INCLUDED IN C AND C2. R I F(ON) ma 60 7 ma ALL DIODES ARE EITHER N96 OR N3064 t PHL I F (ON) V OL (0 V) 0% I F (ON) t PLH 0 ma V OH.3 V Figure. Circuit for t PLH, t PHL, t r, t f 9

10 Tp - Propagation Delay - ns Vcc = 4. V T A - Temperature - C Figure 6. Typical Propagation Delays vs. Temperature T PHL (If = 4 ma) T PLH (If = 4 ma) T PHL (If = 7 ma) T PLH (If = 7 ma) VO - Output Voltage - V I F = 4 ma T A = 2 C V CC - Supply Voltage - V Figure 7. Typical Logic High Output Voltage vs. Supply Voltage Tp - Propagation Delay - ns T A = 2 C T PHL (If = 4 ma) T PLH (If = 4 ma) T PHL (If = 7 ma) T PLH (If = 7 ma) V CC - Supply Voltage - V Figure 8. Typical Propagation Delay vs. Supply Voltage V FF + R IN /2 R IN /2 A B 2 3 SHIELD V CM V CC 0. μf OUTPUT V o MONITORING NODE V CM OUTPUT V o 0 V CM H CM L SWITCH AT B: V F = 0 V V OH V o (MIN.)* V CM (PEAK) SWITCH AT A: I F = 4 ma V o (MAX.)* V OL * SEE NOTE 7 Figure 9. Test Circuit for Common Mode Transient Immunity and Typical Waveforms 0

11 Vcc = 2~4 V Vcc =.8 V (typ) 0 V Vcc Vcc = 2~4 V Vcc =.8 V (typ) 0 V Output High Impedance state High Impedance state ms Figure 0a. Vcc Ramp when LED is OFF i. LED is OFF Discharge delay, depending on the power supply slew rate Vcc = 2~4 V Vcc =.8 V (typ) 0 V Vcc Vcc = 2~4 V Vcc =.8 V (typ) 0 V High Impedance state ms Figure 0b. Vcc Ramp when LED is ON Output ii. LED is ON High Impedance state Discharge delay, depending on the power supply slew rate

12 Thermal Model for ACPL-M483 SO Package Optocoupler Definitions R : Junction to Ambient Thermal Resistance of LED due to heating of LED R 2 : Junction to Ambient Thermal Resistance of LED due to heating of Detector (Output IC) R 2 : Junction to Ambient Thermal Resistance of Detector (Output IC) due to heating of LED. R 22 : Junction to Ambient Thermal Resistance of Detector (Output IC) due to heating of Detector (Output IC). P : Power dissipation of LED (W). P 2 : Power dissipation of Detector/Output IC (W). T : Junction temperature of LED ( C). T 2 : Junction temperature of Detector ( C). T a : Ambient temperature. ΔT : Temperature difference between LED junction and ambient ( C). ΔT 2 : Temperature deference between Detector junction and ambient. Ambient Temperature: Junction to Ambient Thermal Resistances were measured approximately.2cm above optocoupler at ~23 C in still air Description This thermal model assumes that an -pin single-channel plastic package optocoupler is soldered into a 7.62 cm x 7.62 cm printed circuit board (PCB). The temperature at the LED and Detector junctions of the optocoupler can be calculated using the equations below. T = (R * P + R 2 * P 2 ) + T a -- () T 2 = (R 2 * P + R 22 * P 2 ) + T a -- (2) Jedec Specifications R R 2, R 2 R 22 low K board 9 77, 9 99 high K board 26 26, 3 Notes:. Maximum junction temperature for above parts: 2 C. Thermal Model for ACPL-P483/W483 SO6 Package Optocoupler Definitions R : Junction to Ambient Thermal Resistance of LED due to heating of LED R 2 : Junction to Ambient Thermal Resistance of LED due to heating of Detector (Output IC) R 2 : Junction to Ambient Thermal Resistance of Detector (Output IC) due to heating of LED. R 22 : Junction to Ambient Thermal Resistance of Detector (Output IC) due to heating of Detector (Output IC). P : Power dissipation of LED (W). P 2 : Power dissipation of Detector/Output IC (W). T : Junction temperature of LED ( C). T 2 : Junction temperature of Detector ( C). T a : Ambient temperature. ΔT : Temperature difference between LED junction and ambient ( C). ΔT 2 : Temperature deference between Detector junction and ambient. Ambient Temperature: Junction to Ambient Thermal Resistances were measured approximately.2cm above optocoupler at ~23 C in still air Description This thermal model assumes that an 6-pin single-channel plastic package optocoupler is soldered into a 7.62 cm x 7.62 cm printed circuit board (PCB). The temperature at the LED and Detector junctions of the optocoupler can be calculated using the equations below. T = (R * P + R 2 * P 2 ) + T a -- () T 2 = (R 2 * P + R 22 * P 2 ) + T a -- (2) Jedec Specifications R R 2, R 2 R 22 low K board 67 64, 8 89 high K board 7 3, 39 4 Notes:. Maximum junction temperature for above parts: 2 C. For product information and a complete list of distributors, please go to our web site: Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright Avago Technologies. All rights reserved. AV02-326EN - September 9, 206

ACPL-P480 and ACPL-W480

ACPL-P480 and ACPL-W480 High CMR Intelligent Power Module and Gate Drive Interface Optocoupler Description The high-speed ACPL-P48/W48 optocoupler contains a GaAsP LED, a photo detector, and a Schmitt trigger that eliminates