ACNV2601. High Insulation Voltage 10-MBd Digital Optocoupler. Data Sheet. Description. Features. Applications

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1 High Insulation Voltage -MBd Digital Optocoupler Description The ACNV26 is an optically coupled gate that combines an AlGaAs light-emitting diode and an integrated photo detector housed in a widebody package. The distance-throughinsulation (DTI) between the emitting diode and photo-detector is at 2 mm. The output of the detector IC is an open collector Schottky clamped transistor. The internal shield provides a guaranteed common mode transient immunity specification of 2 kv/μs at V cm = V. With creepage and clearance of greater than mm, ACNV26 is designed to provide high isolation voltage (7 V rms ). It can withstand a continuous high working voltage of 2262 V peak and a surge voltage of 2, V peak, meeting IEC6747--, UL, and CSA standard for reinforced insulation. ACNV26 provides the high insulation voltage protection at a high data rate of MBd. Features High voltage insulation with minimum -mm creepage and clearance 2 kv/μs minimum common mode rejection (CMR) at V CM = V High speed: MBd typical TTL compatible Open collector output Guaranteed AC and DC performance over wide temperature: 4 C to + C Available in -pin widebody packages Safety approval: Approval at 7 V rms for minute per UL77 CSA IEC/EN/DIN EN with V iorm = 2262 V peak CAUTION It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD. The components featured in this data sheet are not to be used in military or aerospace applications or environments Applications High voltage insulation Instrument input/output isolation Line receivers Ground loop elimination Isolation of high-speed logic systems Microprocessor system interfaces - -

2 Functional Diagram Anode Cathode NOTE 2 4 SHIELD Vcc 9 Ve 8 Vo 7 6 GND A.-μF bypass capacitor must be connected between pins V CC and GND. Truth Table (Positive Logic) LED ENABLE OUTPUT On H L Off H H On L H Off L H On L Off H Ordering Information ACNV26 is UL recognized with 7 V rms for minute per UL77. Part Number To order, choose a part number from the Part Number column and combine with the desired option from the Option column to form an order entry. Example : ACNV26-E to order product of mil DIP- Widebody with Gull Wing Surface Mount package in Tape and Reel packaging with both UL 7 V rms / min and IEC/EN/DIN EN Safety Approval in RoHS compliant. Option data sheets are available. Contact your sales representative or authorized distributor for information. Schematic Option RoHS Compliant Package Surface Mount Gull Wing Tape & Reel UL 7 V rms / Minute Rating IEC/EN/DIN EN Quantity ACNV26 -E mil X X per tube -E DIP- X X X X per tube -E X X X X X per reel 2+ I F I CC V CC I O 8 V O V F SHIELD I E 9 V E 7 GND NOTE Use of a.-μf bypass capacitor connected between pins of 7 and is recommended

3 Package Drawings -Pin Widebody ( mils) DIP Package [.7 ±.].4 ±.6 Device Part Number Lead Free Pin Dot [.]. TYP A NNNNNNNN YYWW EEE [. ±.].4 ±.6 Date Code Lot ID [.].2 MIN [.2].2 [. ±.].2 ±.6 [. ±.].4 ±.6 [.2].27 [.].22 [.9].4 [.998].8 [.6].4 [.78 ±.].7 ±.6 [2.4]. TYP [.48 ±.8].9 ±. TYP [.2 ] Dimensions in Inches [Millimeters] -Pin Widebody ( mils) DIP Package with Gull Wing Surface Mount Option [.7 ±.].4 ±.6 LAND PATTERN RECOMMENDATION [. ±.]. ±.6 Device Part Number Lead Free Pin Dot A NNNNNNNN YYWW EEE [. ±.].4 ±.6 Date Code Lot ID [6. ±.].644 ±.6 [2.29 ±.].9 ±.6 [2.29 ±.].9 ±.6 [.]. TYP [4.9 ±.].87 ±.6 [. ±.].2 ±.6 [.78 ±.].7 ±.6 [.2].27 MAX [.7 ±.]. ±.6 [. ±.].9 ±.6 [.24 ]. NOM Dimension in Inches [Millimeter] - -

4 Solder Reflow Profile Recommended reflow condition as per JEDEC Standard, J-STD-2 (latest revision). Non-Halide Flux should be used. Insulation and Safety Related Specifications Parameter Symbol ACNV26 Unit Conditions Minimum External Air Gap (External Clearance) Minimum External Tracking (External Creepage) Minimum Internal Plastic Gap (Internal Clearance) Minimum Internal Tracking (Internal Creepage) Tracking Resistance (Comparative Tracking Index) L() mm Measured from input terminals to output terminals, shortest distance through air. L(2) mm Measured from input terminals to output terminals, shortest distance path along body. 2. mm Through insulation distance conductor to conductor, usually the straight line distance thickness between the emitter and detector. 4.6 mm Measured from input terminals to output terminals, along internal cavity. CTI 2 V DIN IEC 2/VDE Part. Isolation Group IIIa Material Group (DIN VDE, /89, Table )

5 IEC/EN/DIN EN Insulation Characteristics a Installation Classification per DIN VDE /.89, Table For Rated Mains Voltage 6 V rms For Rated Mains Voltage V rms Description Symbol Characteristic Unit Climatic Classification //2 Pollution Degree (DIN VDE /.89) 2 Maximum Working Insulation Voltage V IORM 2262 V peak I IV I III Input to Output Test Voltage, Method b a V IORM x.87 = V PR, % Production Test with t m = sec, Partial Discharge < pc Input to Output Test Voltage, Method a a V IORM x.6 = V PR, Type and Sample Test, t m = sec, Partial Discharge < pc V PR 424 V peak V PR 69 V peak Highest Allowable Overvoltage (Transient Overvoltage t ini = 6 sec) V IOTM 2 V peak Safety-Limiting Values Maximum Values Allowed in the Event of a Failure Case Temperature Input Current b Output Power b T S I S, INPUT P S, OUTPUT 4 C ma W Insulation Resistance at T S, V IO = V R S > 9 Ω a. Refer to the optocoupler section of the Isolation and Control Components Designer s Catalog, under Product Safety Regulations section, (IEC/EN/DIN EN ) for a detailed description of Method a and Method b partial discharge test profiles. b. Refer to the following figure for dependence of P S and I S on ambient temperature: OUTPUT POWER - PS, INPUT CURRENT - IS P S (mw) I S (ma) T s - CASE TEMPERATURE - C NOTE These optocouplers are suitable for safe electrical isolation only within the safety limit data. Maintenance of the safety data shall be ensured by means of protective circuits. - -

6 Absolute Maximum Ratings Parameter Symbol Min. Max. Unit Storage Temperature T S 2 C Operating Temperature T A 4 C Average Input Current I F(AVG) 2 ma Reverse Input Voltage V R V Input Power Dissipation P I 4 mw Supply Voltage ( Minute Maximum) V CC 7 V Enable Input Voltage (Not to exceed V CC by more than mv) V E V CC +. V Enable Input Current I E ma Output Collector Current I O ma Output Collector Voltage V O 7 V Output Collector Power Dissipation P O 8 mw Lead Solder Temperature T LS 24 C for sec, up to seat plane Recommended Operating Conditions Parameter Symbol Min. Max. Unit Notes Input Current, Low Level Input Current, High Level I FL a I FH b 2 μa 9 6 ma c Power Supply Voltage V CC 4.. V Low Level Enable Voltage V EL.8 V High Level Enable Voltage V EH 2. V CC V Operating Temperature T A 4 C Fan Out (at R L = kω) N TTL Loads Output Pull-up Resistor R L 4k Ω a. The off condition can also be guaranteed by ensuring that V FL.8V. b. The initial switching threshold is 8 ma or less. It is recommended that 9 ma to 6 ma be used for best performance and to permit at least a 2% LED degradation guardband. c. Peaking circuits may produce transient input currents up to -ma, -ns maximum pulse width, provided average current does not exceed 2 ma

7 Electrical Specifications (DC) Over recommended operating conditions unless otherwise specified. All typicals at V CC = V, T A = 2 C. Parameter Symbol Min. Typ. Max. Unit Test Conditions Fig. Notes High Level Output Current I OH. μa V CC =.V, V E = 2.V V O =.V, I FL = 2 μa Input Threshold Current I TH. 8 ma V CC =.V, V E = 2.V, V O =.6V, I OL > ma Low Level Output Voltage V OL..6 V V CC =.V, V E = 2.V, I F = 8 ma, I OL(Sinking) = ma High Level Supply Current I CCH 7. 2 ma V E =.V V CC =. V, 6. V E = V CC I F = ma Low Level Supply Current I CCL 9. ma V E =.V V CC =.V, 8. V E = V CC I F = ma a. No external pull-up is required for a high logic state on the enable input. If the V E pin is not used, tying V E to V CC results in improved CM R performance a, 2 a High Level Enable Current I EH.7 ma V CC =.V, V E = 2.V Low Level Enable Current I EL.9 ma V CC =.V, V E =.V High Level Enable Voltage V EH 2. ma V CC =. V, V E = 2.V a Low Level Enable Voltage V EL.8 ma V CC =.V, V E =.V Input Forward Voltage V F V T A = 2 C I F = ma.2 2. Input Reverse Breakdown Voltage BV R V I R = μa, T A = 2 C Input Capacitance C IN 6 pf f = MHz, V F = V Input Diode Temperature Coefficient ΔV F /ΔT A.9 mv/ C I F = ma, 2,, 4 a - 7 -

8 Switching Specifications (AC) Over recommended temperature (T A = 4 C to + C), V CC = V, I F = ma unless otherwise specified. All typicals are at T A = 2 C, V CC = V. Parameter Symbol Min. Typ. Max. Unit Test Conditions Fig. Notes Propagation Delay Time to High Output Level t PLH 8 2 ns T A = 2 C R L = Ω, C L = pf 6, 7, 8 a, b Propagation Delay Time to Low t PHL 8 ns T A = 2 C c, b Output Level 2 Pulse Width Distortion t PHL t PLH 4 ns R L = Ω, C L = pf 6, 7, 8, 9 b Propagation Delay Skew t psk ns d, b Output Rise Time (% to 9%) T r 2 ns b Output Fall Time (% to 9%) T f ns b Propagation Delay Time of Enable t ELH ns R L = Ω, C L = pf, from V EH to V EL V EL = V, V EH = V Propagation Delay Time of Enable t EHL 2 ns R L = Ω, C L = pf, from V EL to V EH V EL = V, V EH = V, 2 e, 2 f Output High Level Common Mode Transient Immunity Output Low Level Common Mode Transient Immunity CM H 2 2 kv/μs V CC = V, I F = ma, V O(MIN) = 2V, R L = Ω, T A = 2 C, V CM = V CM L 2 2 kv/μs V CC = V, I F = ma, V O(MAX) =.8V, R L = Ω, T A = 2 C, V CM = V g, h, b h, i, b a. The t PLH propagation delay is measured from the ma point on the falling edge of the input pulse to the.v point on the rising edge of the output pulse. b. No external pull-up is required for a high logic state on the enable input. If the V E pin is not used, tying V E to V CC results in improved CM R performance. c. The tphl propagation delay is measured from the ma point on the rising edge of the input pulse to the.v point on the falling edge of the output pulse. d. t PSK is equal to the worst-case difference in t PHL and/or t PLH that is seen between units at any given temperature and specified test conditions. e. The t ELH enable propagation delay is measured from the.v point on the falling edge of the enable input pulse to the.v point on the rising edge of the output pulse. f. The t EHL enable propagation delay is measured from the.v point on the rising edge of the enable input pulse to the.v point on the falling edge of the output pulse. g. CM H is the maximum tolerable rate of rise of the common mode voltage to ensure that the output remains in a high logic state (i.e., V O > 2.V). h. For sinusoidal voltages, ( dv CM /dt) max = πf CM V CM(p-p). i. CM L is the maximum tolerable rate of fall of the common mode voltage to ensure that the output remains in a low logic state (i.e., V O <.8V). Package Characteristics All typicals are at T A = 2 C. Parameter Symbol Min. Typ. Max. Unit Test Conditions Fig. Notes Input-Output Insulation V ISO 7 V rms RH < % for min., T A = 2 C a, b Input-Output Resistance R I-O 2 Ω V I-O = V a Input-Output Capacitance C I-O..6 pf f = MHz, T A = 2 C a a. Device considered a two-terminal device: pins, 2,, 4 and shorted together, and pins 6, 7, 8, 9 and shorted together. b. In accordance with UL77, each optocoupler is proof tested by applying an insulation test voltage 9 V rms for one second (leakage detection current limit, I I-O μa). This test is performed before the % production test for partial discharge (Method b) shown in the IEC/EN/DIN EN Insulation Characteristics a table, if applicable

9 Figure Typical Output Voltage vs. Forward Input Voltage Current VO - OUTPUT VOLTAGE - V R L = R L = k R L = 4k V CC = V T A = 2 C 2 4 I F - FORWARD INPUT VOLTAGE - ma Figure 2 Typical Input Threshold Current vs. Temperature ITH - INPUT THRESHOLD CURRENT - ma R L =, k, 4k V CC =. V V E =.6 V Figure Typical Low Level Output Voltage vs. Temperature VOL - Low Level Output Voltage - V I = 6 ma I = 9.6 ma I = ma I = 6.4 ma V CC =. V V E = 2. V I F = 8. ma Figure 4 Typical Low Level Output Current vs. Temperature IOL - LOW LEVEL OUTPUT CURRENT - ma I F = ma I F = 8 ma V CC =. V V E = 2. V V OL =.6 V I F = 4-6 ma Figure Typical Input Diode Forward Characteristic IF - FORWARD CURRENT - ma T A = 2 C V F - FORWARD VOLTAGE - V - 9 -

10 Figure 6 Test Circuit for t PHL and t PLH + V PULSE GEN. Z O = t f = t r = ns INPUT MONITORING NODE R M I F 2 4 SHIELD F BYPASS *C L R L OUTPUT V O MONITORING NODE INPUT I F OUTPUT V O *C L IS APPROXIMATELY pf WHICH ILUDES PROBE AND STRAY WIRING CAPACITAE. t PHL t PLH I F = ma I F = ma. V Figure 7 Typical Propagation Delay vs. Temperature tp - PROPAGATION DELAY - ns V CC =. V T A = 2 C t PLH, R L = k t PLH, R L = t PLH, R L = 4k t PHL, R L = t PHL, R L = k 4k Figure 8 Typical Propagation Delay vs. Pulse Input Current tp - PROPAGATION DELAY - ns t PHL, R L = t PHL, R L = k t PHL, R L = 4k t PLH, R L = 4k V CC =. V T A = 2 C t PLH, R L = t PLH, R L = k I F - PULSE INPUT CURRENT - ma Figure 9 Typical Pulse Width Distortion vs. Temperature PWD - PULSE WIDTH DISTORTION - ns R L = R L = 4k R L = k V CC =. V I F =. ma Figure Typical Rise and Fall Time vs. Temperature tr, tf - RISE,FALL TIME - ns 2 2 V CC =. V I F =. ma R L = R L = 4k R L = k t RISE t FALL R L =, k, 4k - -

11 Figure Test Circuit for t EHL and t ELH PULSE GEN. Z O = t f = t r = ns INPUT V E MONITORING NODE + V ma I F 2 4 SHIELD F BYPASS *C L R L OUTPUT V O MONITORING NODE INPUT V E OUTPUT V O t EHL t ELH. V. V. V *C L IS APPROXIMATELY pf WHICH ILUDES PROBE AND STRAY WIRING CAPACITAE. Figure 2 Typical Enable Propagation Delay vs. Temperature te - ENABLE PROPAGATION DELAY - ns V CC =. V V EH =. V V EL =. V I F =. ma t ELH, R L = 4k t ELH, R L = k t ELH, R L =, k, 4k t ELH, R L = - -

12 Figure Test Circuit for Common Mode Transient Immunity and Typical Waveforms I F V FF B A 2 4 SINGLE CHANNEL SHIELD V CM + PULSE GENERATOR Z O = F BYPASS + V RL OUTPUT V O MONITORING NODE V CM V O V V V O. V V CM (PEAK) SWITCH AT A: I F = ma V O (MIN.) SWITCH AT B: I F = ma V O (MAX.) CM H CM L Figure 4 Recommended Printed Circuit Board Layout V CC BUS (FRONT) GND BUS (BACK). F mm MAX. ENABLE OUTPUT SINGLE CHANNEL DEVICE ILLUSTRATED

13 For product information and a complete list of distributors, please go to our web site: the pulse logo, Connecting everything, Avago Technologies, Avago, and the A logo are among the trademarks of in the United States, certain other countries and/or the EU. Copyright All Rights Reserved. The term "" refers to Limited and/or its subsidiaries. For more information, please visit reserves the right to make changes without further notice to any products or data herein to improve reliability, function, or design. Information furnished by is believed to be accurate and reliable. However, does not assume any liability arising out of the application or use of this information, nor the application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others. AV2-246EN April 2, 27

Features. Applications. Truth Table (Positive Logic) LED ENABLE OUTPUT

Features. Applications. Truth Table (Positive Logic) LED ENABLE OUTPUT ACNVE mm DTI, MBd Digital Optocoupler Data Sheet Description The new ACNVE is an optically coupled gate that combines a AlGaAs light emitting diode and an integrated photo detector housed in a widebody