Features. Specifications. Applications

Size: px

Start display at page:

Download "Features. Specifications. Applications"

Leona Warren
5 years ago
Views:

1 ACPL-77L and ACPL-07L.V/V High Speed CMOS Optocoupler Data Sheet Lead (Pb) Free RoHS fully compliant RoHS fully compliant options available; -xxxe denotes a lead-free product Description Available in either an -pin DIP or SO- style respectively, the ACPL-77L or ACPL-07L optocouplers utilize the latest CMOS IC technology to achieve outstanding speed performance of minimum MBd data rate and ns maximum pulse width distortion. Basic building blocks of this family of products are a CMOS LED driver IC, a high speed LED and a CMOS detector IC. A CMOS logic input signal controls the LED driver IC, which supplies current to the LED. The detector IC incorporates an integrated photodiode, a high speed transimpedance amplifier, and a voltage comparator with an output driver. Functional Diagram **V DD NC* GND LED SHIELD 7 V DD ** V O GND * Pin is the anode of the internal LED and must be left unconnected for guaranteed datasheet performance. Pin 7 is not connected internally. ** A 0.uF bypass capacitor must be connected between pins and, and and. TRUTH TABLE (POSITIVE LOGIC) NC*, INPUT LED V O, OUTPUT H OFF H L ON L I O Features Dual voltage operation (.V and V) Allow level shifting functionality Support high Speed datarate of MBd Wide Temperature operation CMOS output and buffer input Compatible with CMOS and TTL logic level Lower power consumption with.v supply Good AC performance with lower pulse width distortion Lead-free option available Specifications.V and V CMOS Compatibility High Speed: DC to MBd ns max. Pulse Width Distortion 0 ns max. Prop. Delay 0 ns max. Prop. Delay Skew 0 kv/ms min. Common Mode Rejection -0 C to 0 C Temperature Range Safety and Regulatory Approvals: UL Recognised - 000V rms for min. per UL77 for ACPL-77L for option 00-70V rms for min. per UL77 for ACPL-07L CSA Component Acceptance Notice # IEC/EN/DIN EN ORM = 0 V peak for ACPL-77L Option 00 ORM = 0 V peak for ACPL-07L Option 00 Applications Digital Fieldbus Isolation: DeviceNet, Profibus, SDS Multiplexed Data Transmission General Instrument and Data Acquisition Computer Peripheral interface Microprocessor System Interface CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation, which may be induced by ESD.

2 Device Selection Guide -Pin DIP (00 Mil) ACPL-77L Small Outline SO- ACPL-07L Ordering Information ACPL-07L and ACPL-77L are UL Recognized with 70 Vrms for minute per UL77. Part number ACPL-77L ACPL-07L RoHS Compliant Option Non RoHS Compliant -000E - Package Surface Mount Gull Wing Tape & Reel UL 000 Vrms/ Minute rating IEC/EN/DIN EN Quantity 0 per tube -00E - X X 0 per tube -00E - X X X 000 per reel -00E - X 0 per tube -0E - 00mil DIP- X X X 0 per tube -0E - X X X X 000 per reel -00E - X 0 per tube -0E - X X X 0 per tube -0E - X X X X 000 per reel -000E No option X 00 per tube -00E -00 X X 00 per reel SO- -00E -00 X X 00 per tube -0E -0 X X X 00 per reel To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. Example : ACPL-77L-0E to order product of Gull Wing Surface Mount package in Tape and Reel packaging with IEC/EN/DIN EN Safety Approval in RoHS compliant. Example : ACPL-07L to order product of Small Outline SO- package in tube packaging and non RoHS compliant. Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.

3 Package Dimensions ACPL-77L -Pin DIP Package 9. ± 0. (0.0 ± 0.00) 7. ± 0. (0.00 ± 0.00) TYPE NUMBER 7 A XXXXV OPTION 00 CODE* DATE CODE. ± 0. (0.0 ± 0.00) YYWW.9 (0.07) MAX.. ± 0. (0.0 ± 0.00).7 (0.070) MAX..70 (0.) MAX TYP ( ) ).00 ± 0.0 (0.0 ± 0.0) 0. (0.00) MIN..9 (0.) MIN. 0. (0.0) MAX.. ± 0. (0.00 ± 0.00) DIMENSIONS IN MILLIMETERS AND (INCHES). *OPTION 00 AND 00 NOT MARKED. NOTE: FLOATING LEAD PROTRUSION IS 0. mm (0 mils) MAX. ACPL-77L Package with Gull Wing Surface Mount Option 00 LAND PATTERN RECOMMENDATION 9. ± 0. (0.0 ± 0.00).0 (0.00) 7.0 ± 0. (0.0 ± 0.00) 0.9 (0.0).7 (0.00).0 (0.00).9 (0.07) MAX..70 (0.070) MAX.. ± 0. (0.0 ± 0.00) 9. ± 0. (0.0 ± 0.00) 7. ± 0. (0.00 ± 0.00) ( ) ).00 ± 0.0 (0.0 ± 0.0). (0.00) BSC DIMENSIONS IN MILLIMETERS (INCHES). LEAD COPLANARITY = 0.0 mm (0.00 INCHES). 0. ± 0.0 (0.0 ± 0.00) 0. ± 0. (0.0 ± 0.00) NOM. NOTE: FLOATING LEAD PROTRUSION IS 0. mm (0 mils) MAX.

4 ACPL-07L Small Outline SO- Package LAND PATTERN RECOMMENDATION.97 ± 0.7 (0. ± 0.00) PIN ONE 7 XXXV YWW 0.0 ± 0.07 (0.0 ± 0.00).70 (0.00).99 ± 0.0 (0. ± 0.00) TYPE NUMBER (LAST DIGITS) DATE CODE BSC 0. (0.0).9 (0.07) 7.9 (0.9) *.00 ± 0.7 (0.00 ± 0.00) 7 X 0. (0.07).7 ± 0.7 (0. ± 0.00). (0.00) 0 ~ 7 0. ± 0.0 (0.009 ± 0.00) * TOTAL PACKAGE LENGTH (INCLUSIVE OF MOLD FLASH).07 ± 0. (0.0 ± 0.00) DIMENSIONS IN MILLIMETERS (INCHES). LEAD COPLANARITY = 0.0 mm (0.00 INCHES) MAX. OPTION NUMBER 00 NOT MARKED. NOTE: FLOATING LEAD PROTRUSION IS 0. mm ( mils) MAX. 0.0 (0.0) MIN. 0.0 ± 0.0 (0.00 ± 0.00)

5 Solder Reflow Temperature Profile TEMPERATURE ( C) PREHEATING RATE C + C/- 0. C/SEC. REFLOW HEATING RATE. C ± 0. C/SEC. 0 C 0 C 0 C C + C/- 0. C. C ± 0. C/SEC. PEAK TEMP. C 0 SEC. 0 SEC. SOLDERING TIME 00 C PEAK TEMP. 0 C PEAK TEMP. 0 C 00 PREHEATING TIME 0 C, SEC. 0 SEC. ROOM TEMPERATURE 0 0 TIGHT TYPICAL LOOSE TIME (SECONDS) Note: Non-halide flux should be used Recommended Pb-Free IR Profile TEMPERATURE T p T L T smax T smin 0 +0/- C 7 C RAMP-UP C/SEC. MAX C t s PREHEAT 0 to 0 SEC. t p t L TIME WITHIN C of ACTUAL PEAK TEMPERATURE 0-0 SEC. RAMP-DOWN C/SEC. MAX. 0 to 0 SEC. t C to PEAK TIME NO TES: THE TIME FROM C to PEAK TEMPERATURE = MINUTES MAX. T smax = 00 C, T smin = 0 C Note: Non-halide flux should be used Regulatory Information Both ACPL-07L and ACPL-77L are approved by the following organizations: IEC/EN/DIN EN Approved under: IEC 077--:997 + A:00 EN 077--:00 + A:00 DIN EN (VDE 0 Teil ):00-0. (option 00 only) UL Approved under UL 77, component recognition program up, File E. CSA Approved under CSA Component Acceptance Notice #, File CA.

6 Table. IEC/EN/DIN EN Insulation Characteristics* Description Installation classification per DIN VDE 00/.9, Table for rated mains voltage 0 Vrms for rated mains voltage 00 Vrms for rated mains voltage 0 Vrms Symbol ACPL-77L Option 00 ACPL-07L Option 00 Climatic Classification /0/ /0/ I IV I IV I III Pollution Degree (DIN VDE 00/.9) I IV I III Units Maximum Working Insulation Voltage ORM 0 0 V peak Input to Output Test Voltage, Method b** ORM x.7=v PR, 00% Production Test with t m = sec, Partial discharge < pc Input to Output Test Voltage, Method a** ORM x.=v PR, Type and Sample Test, t m =0 sec, Partial discharge < pc V PR 00 V peak V PR 9 0 V peak Highest Allowable Overvoltage (Transient Overvoltage t ini = 0 sec) OTM V peak Safety-limiting values maximum values allowed in the event of a failure, also see Figure. Case Temperature Input Current Output Power T S I S, INPUT P S, OUTPUT Insulation Resistance at T S, O = 00 V R IO >09 >09 W * Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in application. Surface mount classification is class A in accordance with CECCOO0. ** Refer to the optocoupler section of the Isolation and Control Components Designer s Catalog, under Product Safety Regulations section IEC/EN/ DIN EN 077--, for a detailed description of Method a and Method b partial discharge test profiles. Note: These optocouplers are suitable for safe electrical isolation only within the safety limit data. Maintenance of the safety data shall be ensured by means of protective circuits. Note: The surface mount classification is Class A in accordance with CECC C ma mw Table. Insulation and Safety Related Specifications Parameter Minimum External Air Gap (Clearance) Minimum External Tracking (Creepage) Minimum Internal Plastic Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Symbol ACPL- 77L Value ACPL-07L Units Conditions L(0) 7..9 mm Measured from input terminals to output terminals, shortest distance through air. L(0) 7.. mm Measured from input terminals to output terminals, shortest distance path along body mm Through insulation distance conductor to conductor, usually the straight line distance thickness between the emitter and detector. CTI >7 >7 V DIN IEC /VDE 00 Part Isolation Group IIIa IIIa Material Group (DIN VDE 00, /9, Table ) All Avago Technologies data sheets report the creepage and clearance inherent to the optocoupler component itself. These dimensions are needed as a starting point for the equipment designer when determining the circuit insulation requirements. However, once mounted on a printed circuit board, minimum creepage and clearance requirements must be met as specified for individual equipment standards. For creepage, the shortest distance path along the surface of a printed circuit board between the solder fillets of the input and output leads must be considered. There are recommended techniques such as grooves and ribs which may be used on a printed circuit board to achieve desired creepage and clearances. Creepage and clearance distances will also change depending on factors such as pollution degree and insulation level.

7 Table. Absolute Maximum Ratings Parameter Symbol Min. Max. Units Storage Temperature T S + C Ambient Operating Temperature [] T A 0 +0 C Supply Voltages V DD, V DD 0.0 Volts Input Voltage 0. V DD +0. Volts Output Voltage V O 0. V DD +0. Volts Average Output Current I O 0 ma Lead Solder Temperature 0 C for 0 sec.,. mm below seating plane Solder Reflow Temperature Profile Please See Solder Reflow Temperature Profile Section Table. Recommended Operating Conditions Parameter Symbol Min. Max. Units Ambient Operating Temperature T A 0 +0 C Supply Voltages (.V operation) V DD, V DD.0. V Supply Voltages ( V operation) V DD, V DD.. V Logic High Input Voltage H.0 V DD V Logic Low Input Voltage L V Input Signal Rise and Fall Times t r, t f.0 ms Table. Electrical Specifications Test conditions that are not specified can be anywhere within the recommended operating range. The following specifications cover the following power supply combinations: (.V V DD.V,.V V DD.V), (V V DD.V, V V DD.V), (.V V DD.V, V V DD.V) and (V V DD.V,.V V DD.V). All typical specifications are at T A =+ C, V DD = V DD = +.V. Parameter Symbol Min. Typ. Max. Units Test Conditions Logic Low Input Supply Current [] I DDL. ma = 0 V Logic High Input Supply Current [] I DDH. ma = V DD Output Supply Current I DDL. 0 ma I DDH. 0 ma Input Current I I 0 0 ma Logic High Output Voltage V OH V DD -0. V DD O = 0 ma, = H V DD -. V DD -0. O = ma, = H Logic Low Output Voltage V OL 0 0. O = 0 ma, = L 0..0 O = ma, = L 7

8 Table. Switching Specifications Test conditions that are not specified can be anywhere within the recommended operating range. The following specifications cover the following power supply combinations: (.V V DD.V,.V V DD.V), (V V DD.V, V V DD.V), (.V V DD.V, V V DD.V) and (V V DD.V,.V V DD.V). All typical specifications are at T A =+ C, V DD = V DD = +.V. Parameter Symbol Min. Typ. Max. Units Test Conditions Propogation Delay Time t PHL. 0 ns C L = pf, CMOS Signal Levels to Logic Low Output [] Propogation Delay Time t PLH. 0 ns C L = pf, CMOS Signal Levels to Logic High Output [] Pulse Width [] t PW 0 ns C L = pf, CMOS Signal Levels Maximum Data Rate [] MBd C L = pf, CMOS Signal Levels Pulse Width Distortion [] t PHL - t PLH PWD ns C L = pf, CMOS Signal Levels Propagation Delay Skew [7] t PSK 0 ns C L = pf, CMOS Signal Levels Output Rise Time (0% 90%) Output Fall Time (90% - 0%) t R 9 ns C L = pf, CMOS Signal Levels t F ns C L = pf, CMOS Signal Levels Common Mode Transient CM H 0 0 kv/ms V CM = 000 V, T A = C, Immunity at Logic High Output [] = V DD, V O > 0. V DD Common Mode Transient CM L 0 0 kv/ms V CM = 000 V, T A = C, Immunity at Logic Low Output [] = 0 V, V O < 0. V Table 7. Package Characteristics All typical specifications are at T A = C. Parameters Symbol Min. Typ. Max. Units Test Conditions Input-Output Momentary 07L SO 70 V rms RH 0%, t = min, T A = C With-stand Voltage [7,,9] 77L 70 77L with 00 option Input-Output Resistance [9] R I-O 0 W -O = 00 V dc Input-Output Capacitance C I-O 0. pf f = MHz 000 Input Capacitance [] C I.0 pf Input IC Junction-to-Case Thermal Resistance Output IC Junction-to-Case Thermal Resistance 77L qjci C/W Thermocouple located at center 07L 0 underside of package 77L qjco 0 C/W 07L Package Power Dissipation P PD 0 mw Notes:. Absolute Maximum ambient operating temperature means the device will not be damaged if operated under these conditions. It does not guarantee functionality.. The LED is ON when is low and OFF when is high.. t PHL propagation delay is measured from the 0% level on the falling edge of the signal to the 0% level of the falling edge of the V O signal. t PLH propagation delay is measured from the 0% level on the rising edge of the signal to the 0% level of the rising edge of the V O signal.. The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.. The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.. PWD is defined as t PHL - t PLH. %PWD (percent pulse width distortion) is equal to the PWD divided by pulse width. 7. t PSK is equal to the magnitude of the worst case difference in t PHL and/or t PLH that will be seen between units at any given temperature within the recommended operating conditions.

9 . CM H is the maximum common mode voltage slew rate that can be sustained while maintaining V O > 0. V DD. CML is the maximum common mode voltage slew rate that can be sustained while maintaining V O < 0. V. The common mode voltage slew rates apply to both rising and falling common mode voltage edges. 9. Device considered a two-terminal device: pins,,, and shorted together and pins,, 7, and shorted together. 0. In accordance with UL77, each ACPL-07L is proof tested by applying an insulation test voltage 00 V RMS for second (leakage detection current limit, I I-O ma). Each ACPL-77L is proof tested by applying an insulation test voltage 00 V RMS for second (leakage detection current limit, I I-O ma).. The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. For the continuous voltage rating refers to your equipment level safety specification or Avago Technologies Application Note 07 entitled Optocoupler Input-Output Endurance Voltage.. C I is the capacitance measured at pin ( ). Tplh, T phl (ns) T A ( o C) PWD (ns) T plh T.0 phl T A ( o C) PWD Figure. Typical propagation delays vs temperature Tr, T f (ns) T A ( o C) Figure. Typical rise and fall time vs temperature Rise Time Fall Time Figure. Typical pulse width distortion vs temperature Tplh, T phl (ns) 0 0 C L (pf) Figure. Typical propagation delays vs load capacitance T plh T phl PWD Surface Mount SO- Product Standard -pin DIP Product, PWD (ns) 0 C L (pf) Figure. Typical pulse width distortion vs load capacitance Output Power - Ps, Input Current - Is T A - Case Temperature - C Is (ma) Ps (mw) Figure. Thermal derating curve, dependence of safety limiting value with case temperature per IEC/EN/DIN EN Output Power - Ps, Input Current - Is Is (ma) Ps (mw) TA - Case Temperature - C 9

10 Application Information Bypassing and PC Board Layout The ACPL-x7L optocouplers are extremely easy to use. No external interface circuitry is required because ACPLx7L uses high speed CMOS IC technology allowing CMOS logic to be connected directly to the inputs and outputs. As shown in Figure 7, the only external components required for proper operation are two bypass capacitors. Capacitor values should be between 0.0mF and 0.mF. For each capacitor, the total lead length between both ends of the capacitor and power supply pins should not exceed 0mm. Figure illustrates the recommended printed circuit board layout for ACPL-x7L. Propagation Delay, Pulse-Width Distortion and Propagation Delay Skew Propagation Delay is a figure of merit which describes how quickly a logic signal propagates through a system. The propagation delay from a low to high (t PLH ) is the amount of time required for an input signal to propagate to the output, causing the output to change from low to high. Similarly, the propagation delay from high to low (t PHL ) is the amount of time required for the input signal to propagate to the output, causing the output to change from high to low. Please see Figure 9. INPUT t PLH t PHL 0% V CMOS 0 V V DD C GND Figure 7. Recommended Circuit Diagram NC 7L YYL C, C = 0.0 µf TO 0. µf 7 NC C GND V DD V O OUTPUT V O 0% 90% Figure 9. Signal plot shows how propagation delay is defined Pulse-width distortion (PWD) is the difference between t PHL and t PLH and often determines the maximum data rate capability of a transmission system. PWD can be expressed in percent by dividing the PWD (in ns) by the minimum pulse width (in ns) being transmitted. Typically, PWD on the order of 0-0% of the minimum pulse width is tolerable. The PWD specification for ACPL-x7L is ns (%) maximum across recommended operating conditions. 90% 0% V OH. V CMOS V OL V DD V DD C 7L YYL C VO GND GND Figure. Recommended Printed Circuit Board Layout C, C = 0.0 µf TO 0. µf 0

11 Propagation delay skew, t PSK, is an important parameter to consider in parallel data applications where synchronization of signals on parallel data lines is a concern. If the parallel data is sent through a group of optocouplers, differences in propagation delays will cause the data to arrive at the outputs of the optocouplers at different times. If this difference in propagation delay is large enough it will determine the maximum rate at which parallel data can be sent through the optocouplers. Propagation delay skew is defined as the difference between the minimum and maximum propagation delays, either t PLH or t PHL for any given group of optocouoplers which are operating under the same conditions (i.e., the same drive current, supply voltage, output load, and operating temperature). As illustrated in Figure 0, if the inputs of a group of optocouplers are switched either ON or OFF at the same time, t PSK is the difference between the shortest propagation delay, either t PLH or t PHL and the longest propagation delay, either t PLH and t PHL. V O V O 0%. V, CMOS 0% t PSK Figure 0. Propagation delay skew waveform. V, CMOS As mentioned earlier, t PSK can determine the maximum parallel data transmission rate. Figure is the timing diagram of a typical parallel data application with both the clock and data lines being sent through the optocouplers. The figure shows data and clock signals at the inputs and outputs of the optocouplers. In this case the data is assumes to be clocked off of the rising edge of the clock. INPUTS OUTPUTS DATA CLOCK DATA CLOCK t PSK t PSK Figure. Parallel data transmission example. Propagation delay skew represents the uncertainty of where an edge might be after being sent through an optocoupler. Figure shows that there will be uncertainty in both the data and clock lines. It is important that these two areas of uncertainty not overlap, otherwise the clock signal might arrive before all the data outputs have settled, or some of the data outputs may start to change before the clock signal has arrived. From these considerations, the absolute minimum pulse width that can be sent through optocouplers in a parallel application is twice t PSK. A cautious design should use a slightly longer pulse width to ensure that any additional uncertainty in the rest of the circuit does not cause a problem. The ACPL-x7L optocoupler offers the advantage of guaranteed specifications for propagation delays, pulsewidth distortion, and propagation delay skew over the recommended temperature and power supply ranges. For product information and a complete list of distributors, please go to our web site: Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright Avago Technologies. All rights reserved. Obsoletes AV0-0EN AV0-0EN - January 9, 00

HCPL-7723/ MBd 2 ns PWD High Speed CMOS Optocoupler. Features. Applications

HCPL-7723/ MBd 2 ns PWD High Speed CMOS Optocoupler. Features. Applications HCPL-7723/0723 50 MBd 2 ns PWD High Speed CMOS Optocoupler Data Sheet Lead (Pb) Free RoHS 6 fully compliant RoHS 6 fully compliant options available; -xxxe denotes a lead-free product Description Available