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HCPL-M, HCPL-M, HCPL-M Small Outline, Lead, High CMR, High Speed, Logic Gate Optocouplers Data Sheet Description These small outline high CMR, high speed, logic gate optocouplers are single channel

2 HCPL-M, HCPL-M, HCPL-M Small Outline, Lead, High CMR, High Speed, Logic Gate Optocouplers Data Sheet Description These small outline high CMR, high speed, logic gate optocouplers are single channel devices in a five lead miniature footprint. They are electrically equivalent to the following Avago optocouplers (except there is no output enable feature): SO- Package Standard DIP SO-8 Package HCPL-M N7 HCPL- HCPL-M HCPL-2 HCPL- HCPL-M HCPL-2 HCPL- The SO- JEDEC registered (MO-) package outline does not require through holes in a PCB. This package occupies approximately one fourth the footprint area of the standard dual-in-line package. The lead profile is designed to be compatible with standard surface mount processes. The HCPL-M// optically coupled gates combine a GaAsP light emitting diode and an integrated high gain photon detector. The output of the detector I.C. is an Opencollector Schottky-clamped transistor. The internal shield provides a guaranteed common mode transient immunity specification of, V/µs for the HCPL-M, and, V/µs for the HCPL-M. This unique design provides maximum ac and dc circuit isolation while achieving TTL compatibility. The optocoupler ac and dc operational parameters are guaranteed from C to 8 C allowing trouble free system performance. Features Surface Mountable Very Small, Low Profile JEDEC Registered Package Outline Compatible with Infrared Vapor Phase Reflow and Wave Soldering Processes Internal Shield for High Common Mode Rejection (CMR) HCPL-M:, V/µs at V CM = V HCPL-M:, V/µs at V CM = V High Speed: Mbd LSTTL/TTL Compatible Low Input Current Capability: ma Guaranteed ac and dc Performance over Temperature: C to 8 C Recognized under the Component Program of U.L. (File No. E) for Dielectric Withstand Proof Test Voltage of 7 Vac, Minute Lead Free Option Applications Isolated Line Receiver Simplex/Multiplex Data Transmission Computer-Peripheral Interface Microprocessor System Interface Digital Isolation for A/D, D/A Conversion Switching Power Supply Instrument Input/Output Isolation Ground Loop Elimination Pulse Transformer Replacement CAUTION: The small device geometries inherent to the design of this bipolar component increase the component's susceptibility to damage from electrostatic discharge (ESD). It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD.

3 The SO- JEDEC registered (MO-) package outline does not require through holes in a PCB. This package occupies approximately one fourth the footprint area of the standard dual-in-line package. The lead profile is designed to be compatible with standard surface mount processes. The HCPL-M// optically coupled gates combine a GaAsP light emitting diode and an integrated high gain photon detector. The output of the detector I.C. is an Open-collector Schottky-clamped transistor. The internal shield provides a guaranteed common mode transient immunity specification of, V/µs for the HCPL-M, and, V/µs for the HCPL-M. This unique design provides maximum ac and dc circuit isolation while achieving TTL compatibility. The optocoupler ac and dc operational parameters are guaranteed from - C to 8 C allowing trouble free system performance. The HCPL-M// are suitable for high speed logic interfacing, input/output buffering, as line receivers in environments that conventional line receivers cannot tolerate, and are recommended for use in extremely high ground or induced noise environments. Ordering Information HCPL-xxxx is UL Recognized with 7 Vrms for minute per UL77. Part number HCPL-M HCPL-M RoHS Compliant Option Non RoHS Compliant Package Surface Mount Gull Wing Tape& Reel UL Vrms/ Minute rating IEC/EN/DIN EN Quantity -E No option X per tube SO- -E # X X per reel HCPL-M -E No option X per tube -E # SO- X X per reel -E - X X X per reel To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. Combination of Option 2 and Option is not available. Example : HCPL-M-E to order product of Surface Mount SO- package in Tape and Reel packaging with RoHS compliant. Example 2: HCPL-M to order product of Surface Mount SO- package in tube packaging and non RoHS compliant. Option datasheets are available. Contact your Avago sales representative or authorized distributor for information. Remarks: The notation #XXX is used for existing products, while (new) products launched since th July 2 and RoHS compliant option will use -XXXE.

4 Outline Drawing (JEDEC MO-). ±. (.7 ±.) MXXX XXX 7. ±.2 (.27 ±.8) ANODE CATHODE V CC V OUT GND. ±. (. ±.2). ±.* (.2 ±.) 2. ±. (.98 ±.).2 ±.2 (. ±.). ±.2 (. ±.).27 (.) BSC.7 (.28) MIN. 7 MAX. DIMENSIONS IN MILLIMETERS (INCHES) * MAXIMUM MOLD FLASH ON EACH SIDE IS. mm (.) MAX. LEAD COPLANARITY =.2 (.) NOTE: FLOATING LEAD PROTRUSION IS. mm ( mils) MAX. Land Pattern Recommendation Schematic. (.7) + I F ICC V CC 2. (.). (.) I O V O 2. (.8) 8.27 (.2). (.2) HCPL-M/ SHIELD USE OF A. µf BYPASS CAPACITOR MUST BE CONNECTED BETWEEN PINS AND (SEE NOTE ). GND TRUTH TABLE (POSITIVE LOGIC) LED ON OFF OUTPUT L H

5 Recommended Operating Conditions Parameter Symbol Min. Max. Units Input Current, Low Level I FL * 2 µa Input Current, High Level I FH ma Supply Voltage, Output V CC.. V Fan Out (R L = kω) N TTL Loads Output Pull-Up Resistor R L, Ω Operating Temperature T A - 8 C * The off condition can also be guaranteed by ensuring that V F (off).8 volts. Absolute Maximum Ratings (No Derating Required up to 8 C) Storage Temperature...- C to +2 C Operating Temperature...- C to +8 C Forward Input Current - I F (see Note 2)...2 ma Reverse Input Voltage - V R... V Supply Voltage - V CC ( Minute Maximum)...7 V Output Collector Current - I O... ma Output Collector Power Dissipation...8 mw Output Collector Voltage - V O...7 V (Selection for higher output voltages up to 2 V is available) Infrared and Vapor Phase Reflow Temperature... see below Solder Reflow Thermal Profile TEMPERATURE ( C) 2 PREHEATING RATE C + C/. C/SEC. REFLOW HEATING RATE 2. C ±. C/SEC. C C C C + C/. C 2. C ±. C/SEC. PREHEATING TIME C, 9 + SEC. PEAK TEMP. 2 C SEC. SEC. SEC. PEAK TEMP. 2 C SOLDERING TIME 2 C PEAK TEMP. 2 C ROOM TEMPERATURE 2 2 TIME (SECONDS) TIGHT TYPICAL LOOSE Note: Non-halide flux should be used. Recommended Pb-Free IR Profile TEMPERATURE 2 +/- C T p 27 C T L RAMP-UP C/SEC. MAX. T - 2 C smax T smin 2 t s PREHEAT to 8 SEC. t 2 C to PEAK TIME t p t L TIME WITHIN C of ACTUAL PEAK TEMPERATURE 2- SEC. RAMP-DOWN C/SEC. MAX. to SEC. NOTES: THE TIME FROM 2 C to PEAK TEMPERATURE = 8 MINUTES MAX. T smax = 2 C, T smin = C Note: Non-halide flux should be used.

6 Insulation Related Specifications Parameter Symbol Value Units Conditions Min. External Air Gap L(IO) mm Measured from input terminals (Clearance) to output terminals Min. External Tracking Path L(IO2) mm Measured from input terminals (Creepage) to output terminals Min. Internal Plastic Gap.8 mm Through insulation distance (Clearance) conductor to conductor Tracking Resistance CTI 7 V DIN IEC 2/VDE Part Isolation Group (per DIN VDE 9) IIIa Material Group DIN VDE 9 Electrical Specifications Over recommended temperature (T A = - C to 8 C) unless otherwise specified. (See note.) Parameter Symbol Min. Typ.* Max. Units Test Conditions Fig. Note Input Threshold I TH ma V CC =. V, I O ma, Current V O =. V High Level Output I OH. µa V CC =. V, V O =. V Current I F = 2 µa Low Level Output V OL.. V V CC =. V, I F = ma, 2,, Voltage I OL (Sinking) = ma, High Level Supply I CCH 7. ma V CC =. V, I F = ma, Current Low Level Supply I CCL. ma V CC =. V, I F = ma, Current Input Forward V F..7 V T A = 2 C, I F = ma Voltage...8 I F = ma Input Reverse BV R I R = µa Breakdown Voltage Input Capacitance C IN pf V F = V, f = MHz Input Diode V F / T A -. mv/ C I F = ma 2 Temperature Coefficient Input-Output V ISO 7 V RMS RH %, t = min., Insulation Resistance R I-O 2 Ω V I-O = V (Input-Output) Capacitance C I-O. pf f = MHz (Input-Output) *All typicals at T A = 2 C, V CC = V.

7 Switching Specifications Over recommended temperature (T A = - C to 8 C), V CC = V, I F = 7. ma unless otherwise specified. Device Parameter Symbol HCPL- Min. Typ.* Max. Unit Test Conditions Fig. Note Propagation t PLH ns T A = 2 C R L = Ω, 7 Delay Time to High C L = pf 8 Output Level Propagation t PHL 2 7 T A = 2 C, 7 Delay Time to Low 8 Output Level Propagation t PSK, Delay Skew Pulse Width t PHL - t PLH. 9 Distortion Output Rise t rise Time (%-9%) Output Fall t fall Time (%-9%) Common CM H M, V/µs V CM = V V O(min) = 2 V 7, 9 Mode Transient R M,, V CM = V L = Ω Immunity at High I F = ma Output Level M,, V CM = V T A = 2 C Common CM H M, V CM = V V O(max) =.8 V 8, 9 Mode Transient Immunity at Low Output Level M,, V CM = V M,, V CM = V R L = Ω I F = 7. ma T A = 2 C *All typicals at T A = 2 C, V CC = V. Notes:. Bypassing of the power supply line is required with a. µf ceramic disc capacitor adjacent to each optocoupler. The total lead length between both ends of the capacitor and the isolator pins should not exceed mm. 2. Peaking circuits may produce transient input currents up to ma, ns maximum pulse width, provided average current does not exceed 2 ma.. Device considered a two terminal device: pins and shorted together, and pins, and shorted together.. In accordance with UL 77, each optocoupler is proof tested by applying an insulation test voltage V RMS for second (Leakage detection current limit, I I-O µa).. The t PLH propagation delay is measured from.7 ma point on the falling edge of the input pulse to the. V point on the rising edge of the output pulse.. The t PHL propagation delay is measured from.7 ma point on the rising edge of the input pulse to the. V point on the falling edge of the output pulse. 7. CM H is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state (i.e., V OUT > 2. V). 8. CM L is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state (i.e., V OUT >.8 V). 9. For sinusoidal voltages, ( dv CM /dt) max = πf CM V CM(p-p).. See application section; Propagation Delay, Pulse-Width Distortion and Propagation Delay Skew for more information.. t PSK is equal to the worst case difference in t PHL and/or t PLH that will be seen between units at any given temperature within the worst case operating condition range.

8 I OH HIGH LEVEL OUTPUT CURRENT µa - V CC =. V V O =. V I F = 2 µa V OL LOW LEVEL OUTPUT VOLTAGE V....2 I O = 2.8 ma I O = 9. ma V CC =. V I F =. ma I O = ma I O =. ma I F FORWARD CURRENT ma T A = 2 C I F +. V F V F FORWARD VOLTAGE VOLTS Figure. High Level Output Current vs. Temperature. Figure 2. Low Level Output Voltage vs. Temperature. Figure. Input Diode Forward Characteristic. V O OUTPUT VOLTAGE V 2 R L = Ω R L = KΩ R L = KΩ V CC = V T A = 2 C PULSE GEN. Z O = Ω t f = t r = ns INPUT MONITORING NODE I F R M V CC GND.µF BYPASS *C L + V RL OUTPUT V O MONITORING NODE 2 I F FORWARD INPUT CURRENT ma *C L IS APPROXIMATELY pf WHICH INCLUDES PROBE AND STRAY WIRING CAPACITANCE. Figure. Output Voltage vs. Forward Input current. INPUT I F I F = 7. ma I F =.7 ma t PHL t PLH I OL LOW LEVEL OUTPUT CURRENT ma V CC =. V V OL =. V I F = ma, ma I F =. ma OUTPUT V O Figure. Test Circuit for t PHL and t PLH.. V Figure. Low Level Output Current vs. Temperature. 7

9 t P PROPAGATION DELAY ns 8 2 V CC =. V I F = 7. ma t PHL, R L = Ω KΩ KΩ t PLH, R L = Ω t PLH, R L = KΩ t PLH, R L = KΩ t P PROPAGATION DELAY ns 9 7 V CC =. V T A = 2 C t PLH, R L = Ω t PLH, R L = KΩ t PLH, R L = KΩ t PHL, R L = Ω KΩ KΩ 7 9 PWD PULSE WIDTH DISTORTION ns R L = kω R L = kω R L = kω V CC =. V I F = 7. ma I F PULSE INPUT CURRENT ma Figure 7. Propagation Delay vs. Temperature. Figure 8. Propagation Delay vs. Pulse Input Current. Figure 9. Pulse Width Distortion vs. Temperature. t r, t f RISE, FALL TIME ns V CC =. V I F = 7. ma R L = kω R L = kω R L = Ω R L = Ω, kω, kω t RISE t FALL IF V FF B A V CC + _ PULSE GENERATOR Z O = Ω GND. µf BYPASS Ω + V OUTPUT V O MONITORING NODE Figure. Rise and Fall Time vs. Temperature. dvf/ dt FORWARD VOLTAGE TEMPERATURE COEFFICIENT mv/ C I F PULSE INPUT CURRENT ma V V CM (PEAK) CM V SWITCH AT A: I F = ma V CM H V O V O (MIN.) SWITCH AT B: I F = 7. ma V V O O (MAX.). V CM L Figure. Test Circuit for Common Mode Transient Immunity and Typical Waveforms. Figure 2. Temperature Coefficient for Forward Voltage vs. Input Current. 8

10 Propagation Delay, Pulse-Width Distortion and Propagation Delay Skew Propagation delay is a figure of merit which describes how quickly a logic signal propagates through a system. The propagation delay from low to high (t PLH ) is the amount of time required for an input signal to propagate to the output, causing the output to change from low to high. Similarly, the propagation delay from high to low (t PHL ) is the amount of time required for the input signal to propagate to the output, causing the output to change from high to low (see Figure 7). Pulse-width distortion (PWD) results when t PLH and t PHL differ in value. PWD is defined as the difference between t PLH and t PHL and often determines the maximum data rate capability of a transmission system. PWD can be expressed in percent by dividing the PWD (in ns) by the minimum pulse width (in ns) being transmitted. Typically, PWD on the order of 2-% of the minimum pulse width is tolerable; the exact figure depends on the particular application (RS22, RS22, T-, etc.). Propagation delay skew, t PSK, is an important parameter to consider in parallel data applications where synchronization of signals on parallel data lines is a concern. If the parallel data is being sent through a group of optocouplers, differences in propagation delays will cause the data to arrive at the outputs of the optocouplers at different times. If this difference in propagation delays is large enough, it will determine the maximum rate at which parallel data can be sent through the optocouplers. Propagation delay skew is defined as the difference between the minimum and maximum propagation delays, either t PLH or t PHL, for any given group of optocouplers which are operating under the same conditions (i.e., the same drive current, supply voltage, output load, and operating temperature). As illustrated in Figure, if the inputs of a group of optocouplers are switched either ON or OFF at the same time, t PSK is the difference between the shortest propagation delay, either t PLH or t PHL, and the longest propagation delay, either t PLH or t PHL. As mentioned earlier, t PSK can determine the maximum parallel data transmission rate. Figure is the timing diagram of a typical parallel data application with both the clock and the data lines being sent through optocouplers. The figure shows data and clock signals at the inputs and outputs of the optocouplers. To obtain the maximum data transmission rate, both edges of the clock signal are being used to clock the data; if only one edge were used, the clock signal would need to be twice as fast. Propagation delay skew represents the uncertainty of where an edge might be after being sent through an optocoupler. Figure shows that there will be uncertainty in both the data and the clock lines. It is important that these two areas of uncertainty not overlap, otherwise the clock signal might arrive before all of the data outputs have settled, or some of the data outputs may start to change before the clock signal has arrived. From these considerations, the absolute minimum pulse width that can be sent through optocouplers in a parallel application is twice t PSK. A cautious design should use a slightly longer pulse width to ensure that any additional uncertainty in the rest of the circuit does not cause a problem. The t PSK specified optocouplers offer the advantages of guaranteed specifications for propagation delays, pulsewidth distortion and propagation delay skew over the recommended temperature, and input current, and power supply ranges.

11 I TH INPUT THRESHOLD CURRENT ma 2 - V CC =. V V O =. V R L = kω R L = kω R L = Ω V CC GND V 7 *D V F I F SHIELD * DIODE D (N9 OR EQUIVALENT) IS NOT REQUIRED FOR UNITS WITH OPEN COLLECTOR OUTPUT. 9 Ω. µf BYPASS 2 V V CC 2 GND 2 Figure. Input Threshold Current vs. Temperature. Figure. Recommended TTL/LSTTL to TTL/LSTTL Interface Circuit. I F % DATA INPUTS CLOCK V O. V I F % DATA OUTPUTS t PSK V O. V CLOCK t PSK t PSK Figure. Illustration of Propagation Delay Skew t PSK. Figure. Parallel Data Transmission Example. For product information and a complete list of distributors, please go to our website: Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies Limited in the United States and other countries. Data subject to change. Copyright 27 Avago Technologies Limited. All rights reserved. Obsoletes AV-2EN AV-9EN - December 2, 27

Features. Applications. Truth Table (Positive Logic) LED ENABLE OUTPUT

Features. Applications. Truth Table (Positive Logic) LED ENABLE OUTPUT ACNVE mm DTI, MBd Digital Optocoupler Data Sheet Description The new ACNVE is an optically coupled gate that combines a AlGaAs light emitting diode and an integrated photo detector housed in a widebody