HCPL-261A, HCPL-061A, HCPL-263A, HCPL-063A HCPL-261N, HCPL-061N, HCPL-263N, HCPL-063N HCMOS Compatible, High CMR, 10 MBd Optocouplers.

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1 HCPL-A, HCPL-A, HCPL-A, HCPL-A HCPL-N, HCPL-N, HCPL-N, HCPL-N HCMOS Compatible, High CMR, MBd Optocouplers Data Sheet Lead (Pb) Free RoHS fully compliant RoHS fully compliant options available; -xxxe denotes a lead-free product Description The HCPL-A family of optically coupled gates shown on this data sheet provide all the benefits of the industry standard N family with the added benefit of HCMOS compatible input cur rent. This allows direct interface to all common circuit topologies without additional LED buffer or drive components. The Al- GaAs LED used allows lower drive currents and reduces degradation by using the latest LED tech nol ogy. On the single channel parts, an enable output allows the detector to be strobed. The output of the detector IC is an open collector schottky-clamped transistor. The internal shield provides a mini mum common mode transient immunity of V/µs for the HCPL-A family and V/µs for the HCPL-N family. Functional Diagram NC ANODE CATHODE NC HCPL-A/N HCPL-A/N SHIELD TRUTH TABLE (POSITIVE LOGIC) LED ENABLE ON H OFF H ON L OFF L ON NC OFF NC OUTPUT L H H H L H V CC V E VO ANODE CATHODE CATHODE ANODE The connection of a. µf bypass capacitor between pins and is required. HCPL-A/N HCPL-A/N SHIELD TRUTH TABLE (POSITIVE LOGIC) LED OUTPUT ON L OFF H V CC VO Features HCMOS/LSTTL/TTL performance compatible V/µs minimum Common Mode Rejection (CMR) at V CM = V (HCPL-A family) and kv/µs minimum CMR at V CM = V (HCPL-N family) High speed: MBd typical AC and DC performance specified over industrial temperature range - C to + C Available in pin DIP, SOIC- packages Safety approval: UL recognized per UL V rms for minute and V for minute (Option ) rms CSA Approved IEC/EN/DIN EN -- approved Applications Low input current (. ma) HCMOS compatible version of N optocoupler Isolated line receiver Simplex/multiplex data transmission Computer-peripheral interface Digital isolation for A/D, D/A conversion Switching power supplies Instrumentation input/output isolation Ground loop elimination Pulse transformer replacement CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD.

2 Selection Guide Widebody Minimum CMR Input -Pin DIP ( Mil) Small-Outline SO- ( Mil) Hermetic On- Single Dual Single Dual Single Single and dv/dt V CM Current Output Channel Channel Channel Channel Channel Dual Channel (V/µs) (V) (ma) Enable Package Package Package Package Package Packages NA NA YES N [] HCPL- [] HCNW [] NO HCPL- [] HCPL- [], YES HCPL- [] HCPL- [] HCNW [] NO HCPL- [] HCPL- [],, YES HCPL- [] HCPL- [] HCNW [], YES HCPL- [], YES HCPL- [] NO HCPL- [] HCPL- [], YES HCPL-A HCPL-A NO HCPL-A HCPL-A, [], YES HCPL-N HCPL-N NO HCPL-N HCPL-N,. [] HCPL-9x [] Notes:. Technical data are on separate Avago publications.. kv/µs with V CM = kv can be achieved using Avago application circuit.. Enable is available for single channel products only, except for HCPL-9x devices. HCPL-xx [] HCPL-xx [] Schematic HCPL-A/N HCPL-A/N ICC V CC + I O + V F HCPL-A/N HCPL-A/N I CC I O V CC V F SHIELD I E V E USE OF A. µf BYPASS CAPACITOR CONNECTED BETWEEN PINS AND IS RECOMMENDED (SEE NOTE ). V F + SHIELD I O SHIELD

3 Ordering Information HCPL-xxxx is UL Recognized with V rms for minute per UL. Part number HCPL-A HCPL- N HCPL-A HCPL- N HCPL-A HCPL- N HCPL-A HCPL- N RoHS Compliant Option Non RoHS Compliant Surface Mount Gull Wing Tape & Reel UL Vrms/ Minute rating IEC/EN/DIN EN -- Quantity per tube Package -E No option -E # X X per tube -E # X X X per reel -E # mil X per tube -E - DIP- X X X per tube -E - X X X X per reel -E # X per tube -E # X X X X per reel -E No option per tube -E # X X per tube -E # X X X per reel -E # X per tube mil -E # X X X per tube DIP- -E - X X X X per reel -E # X per tube -E # X X X per tube -E - X X X X per reel -E No option per tube -E # X X per tube -E # mil X X X per reel -E # DIP- X per tube -E # X X X per tube -E - X X X X per reel -E No option per tube -E # X X per tube -E # mil X X X per reel -E # DIP- X per tube -E # X X X per tube -E # X X X X per reel -E No option X per tube -E # X X per reel SO- -E # X X per tube -E # X X X per reel -E No option X per tube -E # SO- X X per reel To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. Combination of Option and Option is not available. Example : HCPL-A-E to order product of mil DIP Gull Wing Surface Mount package in Tape and Reel packaging with IEC/EN/DIN EN -- Safety Approval in RoHS compliant. Example : HCPL-N to order product of mil DIP package in tube packaging and non RoHS compliant. Option datasheets are available. Contact your Avago sales representative or authorized distributor for information. Remarks: The notation #XXX is used for existing products, while (new) products launched since th July and RoHS compliant option will use -XXXE.

4 HCPL-A/N/A/N Outline Drawing Pin Location (for reference only) 9. (.) 9.9 (.9) TYPE NUMBER A XXXXZ YYWW OPTION CODE* DATE CODE. (.). (.). (.9). (.). (.). (.) TYP. PIN ONE. (.) MAX..9 (.) MAX.. ±. (. ±.). (.) MAX.. (.) MIN..9 (.) MIN. DIMENSIONS IN MILLIMETERS AND (INCHES). * MARKING CODE LETTER FOR OPTION NUMBERS. "L" = OPTION "V" = OPTION OPTION NUMBERS AND NOT MARKED. NOTE: FLOATING LEAD PROTRUSION IS. mm ( mils) MAX.. (.). (.). (.) MAX.. (.9). (.) Figure. -Pin dual in-line package device outline drawing. LAND PATTERN RECOMMENDATION 9. ±. (. ±.). (.). ±. (. ±.).9 (.). (.). (.).9 (.) MAX.. (.) MAX. 9. ±. (. ±.). ±. (. ±.). ±. (. ±.). (.). (.). ±. (. ±.). (.) BSC. ±. (. ±.). ±. (. ±.) NOM. DIMENSIONS IN MILLIMETERS (INCHES). TOLERANCES (UNLESS OTHERWISE SPECIFIED): LEAD COPLANARITY MAXIMUM:. (.) NOTE: FLOATING LEAD PROTRUSION IS. mm ( mils) MAX. Figure. Gull wing surface mount option #. xx.xx =. xx.xxx =.

5 HCPL-A/N/A/N Outline Drawing LAND PATTERN RECOMMENDATION.9 ±. (. ±.) XXX YWW.99 ±. (. ±.). ±. (. ±.). (.) BSC TYPE NUMBER (LAST DIGITS) DATE CODE. (.).9 (.).9 (.9) *. ±. (. ±.) X. (.). ±. (. ±.). (.). ±. (.9 ±.) * TOTAL PACKAGE LENGTH (INCLUSIVE OF MOLD FLASH). ±. (. ±.) DIMENSIONS IN MILLIMETERS (INCHES). LEAD COPLANARITY =. mm (. INCHES) MAX. Figure. -Pin Small Outline Package Device Drawing.. ±. (. ±.). (.) MIN. NOTE: FLOATING LEAD PROTRUSION IS. mm ( mils) MAX. Solder Reflow Profile Recommended reflow condition as per JEDEC Standard, J-STD- (latest revision). Non-Halide Flux should be used. Regulatory Information The HCPL-A and HCPL-N families have been approved by the following organizations: UL Recognized under UL, Component Recognition Program, File E. CSA Approved under CSA Component Acceptance Notice #, File CA. IEC/EN/DIN EN --

6 Insulation and Safety Related Specifications -Pin DIP ( Mil) SO- Parameter Symbol Value Value Units Conditions Minimum External Air L()..9 mm Measured from input terminals to Gap (External output terminals, shortest distance Clearance) through air. Minimum External L().. mm Measured from input terminals to Tracking (External output terminals, shortest distance Creepage) path along body. Minimum Internal Plastic.. mm Through insulation distance, conductor Gap (Internal Clearance) to conductor, usually the direct distance between the photoemitter and photodetector inside the optocoupler cavity. Tracking Resistance CTI Volts DIN IEC / VDE Part (Comparative Tracking Index) Isolation Group IIIa IIIa Material Group (DIN VDE, /9, Table ) Option surface mount classification is Class A in accordance with CECC. IEC/EN/DIN EN -- Insulation Characteristics* Description Symbol PDIP Option SO- Option Unit Installation classification per DIN VDE, Table for rated mains voltage V rms for rated mains voltage V rms for rated mains voltage V rms I IV I IV I III I IV I IV I III Climatic Classification // // Pollution Degree (DIN VDE /9) Maximum Working Insulation Voltage V IORM V peak Input to Output Test Voltage, Method b* V IORM x. = V PR, % Production Test with t m = sec, Partial discharge < pc Input to Output Test Voltage, Method a* V IORM x. = V PR, Type and Sample Test, t m = sec, Partial discharge < pc Highest Allowable Overvoltage (Transient Overvoltage t ini = sec) Safety-limiting values maximum values allowed in the event of a failure V PR V peak V PR 9 V peak V IOTM V peak Case Temperature T S C Input Current I S, INPUT ma Output Power P S, OUTPUT mw Insulation Resistance at T S, V IO = V R S 9 9 W * Refer to the front of the optocoupler section of the current catalog, under Product Safety Regulations section IEC/EN/DIN EN --, for a detailed description.

7 Absolute Maximum Ratings Parameter Symbol Min. Max. Units Note Storage Temperature T S - C Operating Temperature T A - + C Average Input Current (AVG) ma Reverse Input Voltage V R Volts Supply Voltage V CC -. Volts Enable Input Voltage V E -.. Volts Output Collector Current (Each Channel) I O ma Output Power Dissipation (Each Channel) P O mw Output Voltage (Each channel) -. Volts Lead Solder Temperature (Through Hole Parts Only) Solder Reflow Temperature Profile (Surface Mount Parts Only) C for s,. mm Below Seating Plane See Package Outline Drawings section Recommended Operating Conditions Parameter Symbol Min. Max. Units Input Voltage, Low Level V FL -. V Input Current, High Level H. ma Power Supply Voltage V CC.. Volts High Level Enable Voltage V EH. V CC Volts Low Level Enable Voltage V EL. Volts Fan Out (at R L = kω) N TTL Loads Output Pull-up Resistor R L k Ω Operating Temperature T A - C

8 Electrical Specifications Over recommended operating temperature (T A = - C to + C) unless otherwise specified. Parameter Symbol Min. Typ.* Max. Units Test Conditions Fig. Note High Level Output I OH. µa V CC =. V, =. V, Current V F =. V, V E =. V Low Level Output L.. V V CC =. V, I OL = ma,, Voltage (sinking), =. ma, V E =. V High Level Supply I CCH ma V E =. V** V CC =. V Current 9 Dual Channel Products*** Low Level Supply I CCL ma V E =. V** V CC =. V Current Dual Channel =. ma Products*** High Level Enable I EH ma V CC =. V, V E =. V Current** Low Level Enable I EL ma V CC =. V, V E =. V Current** Input Forward V F... V = ma Voltage Temperature Co- V F / T A -. mv/ C = ma efficient of Forward Voltage Input Reverse BV R V I R = µa Breakdown Voltage Input Capacitance C IN pf f = MHz, V F = V = ma *All typical values at T A = C, V CC = V **Single Channel Products only (HCPL-A/N/A/N) ***Dual Channel Products only (HCPL-A/N/A/N)

9 Switching Specifications Over recommended operating temperature (T A = - C to + C) unless otherwise specified. Parameter Symbol Min. Typ.* Max. Units Test Conditions Fig. Note Input Current Threshold I THL.. ma V CC =. V, =. V,, High to Low I O > ma (Sinking) Propagation Delay t PLH ns =. ma 9,,, 9, Time to High Output V CC =. V, Level V E = Open, Propagation Delay t PHL ns C L = pf, 9,,,, Time to Low Output R L = Ω Level Pulse Width Distortion PWD ns 9,, t PHL - t PLH Propagation Delay Skew t PSK ns, Output Rise Time t R ns 9,, Output Fall Time t F ns 9,, Propagation Delay t EHL 9 ns =. ma, Time of Enable V CC =. V, from V EH to V EL V EL = V, V EH = V, Propagation Delay t ELH ns C L = pf,, Time of Enable R L = Ω from V EL to V EH *All typical values at T A = C, V CC = V. Common Mode Transient Immunity Specifications, All values at T A = C Parameter Device Symbol Min. Typ. Max. Units Test Conditions Fig. Note Output High HCPL-A CM H kv/µs V CM = V V CC =. V,,, Level Common HCPL-A R L = Ω,, Mode Transient HCPL-A = ma, Immunity HCPL-A T A = C HCPL-N kv/µs V CM = V HCPL-N HCPL-N kv/µs Using Avago,, HCPL-N App Circuit Output Low HCPL-A CM L kv/µs V CM = V V CC =. V,,, Level Common HCPL-A R L = Ω,, Mode Transient HCPL-A =. ma, Immunity HCPL-A (MAX) =. V HCPL-N kv/µs V CM = V HCPL-N (MIN) = V T A = C HCPL-N kv/µs Using Avago,, HCPL-N App Circuit 9

10 Package Characteristics All Typicals at T A = C Parameter Sym. Package* Min. Typ. Max. Units Test Conditions Fig. Note Input-Output V ISO V rms RH %,, Momentary With- t = min., stand Voltage** OPT T A = C, Input-Output R I-O Ω V I-O = Vdc, Resistance Input-Output C I-O. pf f = MHz,, Capacitance T A = C Input-Input I I-I Dual Channel. µa RH %, 9 Insulation t = s, Leakage Current V I-I = V Resistance R I-I Dual Channel Ω 9 (Input-Input) Capacitance C I-I Dual -pin DIP. pf f = MHz 9 (Input-Input) Dual SO-. *Ratings apply to all devices except otherwise noted in the Package column. **The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. For the continuous voltage rating refer to the IEC/EN/DIN EN -- Insulation Characteristics Table (if applicable), your equipment level safety specification or Avago Application Note entitled Optocoupler Input-Output Endurance Voltage. For -pin DIP package devices (HCPL-A/N/A/N) only. Notes:. Peaking circuits may be used which produce transient input currents up to ma, ns maximum pulse width, provided the average current does not exceed ma.. minute maximum.. Derate linearly above C free-air temperature at a rate of. mw/ C for the SOIC- package.. Each channel.. Device considered a two-terminal device: Pins,,, and shorted together and Pins,,, and shorted together.. In accordance with UL, each optocoupler is proof tested by applying an insulation test voltage V RMS for second (leakage detection current limit, I I-O µa). This test is performed before the % production test for partial discharge (method b) shown in the IEC/EN/ DIN EN -- Insulation Characteristics Table, if applicable.. In accordance with UL, each optocoupler is proof tested by applying an insulation test voltage V RMS for second (leakage detection current limit, I I-O µa).. Measured between the LED anode and cathode shorted together and pins through shorted together. 9. The t PLH propagation delay is measured from the. ma point on the falling edge of the input pulse to the. V point on the rising edge of the output pulse.. The t PHL propagation delay is measured from the. ma point on the rising edge of the input pulse to the. V point on the falling edge of the output pulse.. Propagation delay skew (t PSK ) is equal to the worst case difference in t PLH and/or t PHL that will be seen between any two units under the same test conditions and operating temperature.. Single channel products only (HCPL-A/N/A/N).. Common mode transient immunity in a Logic High level is the maximum tolerable dv CM /dt of the common mode pulse, V CM, to assure that the output will remain in a Logic High state (i.e., V o >. V).. Common mode transient immunity in a Logic Low level is the maximum tolerable dv CM /dt of the common mode pulse, V CM, to assure that the output will remain in a Logic Low state (i.e., <. V).. For sinusoidal voltages ( dv CM /dt )max = πf CM V CM(P-P).. Bypassing of the power supply line is required with a. µf ceramic disc capacitor adjacent to each optocoup ler as shown in Figure 9. Total lead length between both ends of the capacitor and the isolator pins should not exceed mm.. Pulse Width Distortion (PWD) is defined as the difference between t PLH and t PHL for any given device.. No external pull up is required for a high logic state on the enable input of a single channel product. If the V E pin is not used, tying V E to V CC will result in improved CMR performance. 9. Measured between pins and shorted together, and pins and shorted together. For dual channel parts only.

11 I OH HIGH LEVEL OUTPUT CURRENT µa - V CC =. V =. V V E = V V F =. V - - T A TEMPERATURE C Figure. Typical high level output current vs. temperature. I OL LOW LEVEL OUTPUT CURRENT ma - V CC = V V E = V L =. V =. ma - - T A TEMPERATURE C Figure. Low level output current vs. temperature. INPUT FORWARD CURRENT ma T A = C... T A = C T A = C + V F. V F FORWARD VOLTAGE V Figure. Typical diode input forward current characteristic.. OUTPUT VOLTAGE V..... R L = kw R L = Ω R L = kω.... FORWARD INPUT CURRENT ma Figure. Typical output voltage vs. forward input current. L LOW LEVEL OUTPUT VOLTAGE V I O = ma I O =. ma I O = 9. ma I O =. ma V CC =. V V E = V =. ma - - T A TEMPERATURE C Figure. Typical low level output voltage vs. temperature. HCPL-A/N + V PULSE GEN. Z O= Ω t f = t r = ns V CC. µf BYPASS R L INPUT MONITORING NODE *C L OUTPUT MONITORING NODE R M *C L IS APPROXIMATELY pf WHICH INCLUDES PROBE AND STRAY WIRING CAPACITANCE. INPUT =. ma I F =. ma 9% 9% H OUTPUT t PHL tplh. V % % t rise t fall L Figure 9. Test circuit for t PHL and t PLH.

12 I TH INPUT THRESHOLD CURRENT ma R L = Ω R L = kω R L = kω V CC = V =. V - - t p PROPAGATION DELAY ns - TPLH R L = kω TPLH R L = kω TPLH R L = kω TPHL R L = Ω, kω, kω V CC = V =. ma - - t p PROPAGATION DELAY ns TPLH R L = kω V CC = V T A = C TPLH R L = kω TPLH R L = Ω TPHL RL = Ω, kω, kω T A TEMPERATURE C T A TEMPERATURE C PULSE INPUT CURRENT ma Figure. Typical input threshold current vs. temperature. Figure. Typical propagation delay vs. temperature. Figure. Typical propagation delay vs. pulse input current. PWD ns - R L = kω R L = kω V CC = V =. ma R L = Ω - - T A TEMPERATURE C Figure. Typical pulse width distortion vs. temperature. t r, t f RISE, FALL TIME ns - V CC = V =. ma R L = kω R L = kω R L = Ω t rise t fall R L = Ω, kω, kω - - T A TEMPERATURE C Figure. Typical rise and fall time vs. temperature.

13 PULSE GEN. Z O = Ω t f = t r = ns INPUT V E MONITORING NODE HCPL-A/N + V V CC. ma. µf BYPASS R L INPUT V E OUTPUT *C L IS APPROXIMATELY pf WHICH INCLUDES PROBE AND STRAY WIRING CAPACITANCE. t EHL telh *C L. V. V. V OUTPUT MONITORING NODE t E ENABLE PROPAGATION DELAY ns 9 - V CC = V V EH = V V EL = V =. ma t ELH, R L = kω t ELH, R L = kω t ELH, R L = Ω t EHL, R L = Ω, k Ω, kω - - T A TEMPERATURE C Figure. Test circuit for t EHL and t ELH. Figure. Typical enable propaga tion delay vs. temperature. HCPL-A/-N/-A/-N Only. HCPL-A/N VCC + V A B V CM V FF V CM V V. V PULSE GEN. + O Z = Ω SWITCH AT A: I = ma F SWITCH AT B: =. ma _ V CM (PEAK) (min.) (max.). µf BYPASS Ω OUTPUT MONITORING NODE CM H CM L OUTPUT POWER P S, INPUT CURRENT I S HCPL-A/N OPTION ONLY P S (mw) I S (ma) T S CASE TEMPERATURE C Figure. Test circuit for common mode transient immunity and typical waveforms. Figure. Thermal derating curve, dependence of safety limiting value with case temperature per IEC/EN/DIN EN --.

14 V CC BUS (FRONT) N.C. N.C. N.C. N.C. V CC BUS (FRONT) SINGLE CHANNEL PRODUCTS DUAL CHANNEL PRODUCTS Figure 9. Recommended printed circuit board layout. VCC LS OR ANY TOTEM-POLE OUTPUT LOGIC GATE Ω (MAX.) Ω (MAX.) *.µf.µf.µf * BUS (BACK) mm MAX. (SEE NOTE ) BUS (BACK) mm MAX. (SEE NOTE ) HCPL-A/N SHIELD ENABLE (IF USED) OUTPUT ENABLE (IF USED) OUTPUT. µf OUTPUT OUTPUT Ω VCC+ VO Application Information Common-Mode Rejection for HCPL- A/HCPL-N Families: Figure shows the recom mended drive circuit for the HCPL-N/- A for optimal common-mode rejection performance. Two main points to note are:. The enable pin is tied to V CC rather than floating (this applies to single-channel parts only).. Two LED-current setting resistors are used instead of one. This is to balance I LED variation during common-mode transients. If the enable pin is left floating, it is possible for common-mode transients to couple to the enable pin, resulting in common-mode failure. This failure mechanism only occurs when the LED is on and the output is in the Low State. It is identified as occurring when the transient output voltage rises above. V. Therefore, the enable pin should be connected to either V CC or logic-level high for best common-mode performance with the output low (CMR L ). This failure mechanism is only present in single-channel parts (HCPL-N, -A, N, -A) which have the enable function. Also, common-mode transients can capacitively couple from the LED anode (or cathode) to the output-side ground causing current to be shunted away from the LED (which can be bad if the LED is on) or conversely cause current to be injected into the LED (bad if the LED is meant to be off). Figure shows the parasitic capacitances which exists between LED anode/cathode and output ground (C LA and C LC ). Also shown in Figure on the input side is an ACequivalent circuit. * HIGHER CMR MAY BE OBTAINABLE BY CONNECTING PINS, TO INPUT GROUND (). *Higher CMR may be obtainable by connecting pins, to input ground (Gnd). Figure. Recommended drive circuit for HCPL-A/-N families for high-cmr (similar for HCPL-A/-N).

15 Table indicates the directions of I LP and I LN flow depending on the direction of the common-mode transient. For transients occurring when the LED is on, commonmode rejec tion (CMR L, since the output is in the low state) depends upon the amount of LED current drive ( ). For conditions where is close to the switching threshold (I TH ), CMR L also depends on the extent which I LP and I LN balance each other. In other words, any condition where common-mode transients cause a momentary decrease in (i.e. when dv CM /dt> and P > N, referring to Table ) will cause common-mode failure for transients which are fast enough. Likewise for common-mode transients which occur when the LED is off (i.e. CMR H, since the output is high ), if an imbalance between I LP and I LN results in a transient equal to or greater than the switching threshold of the optocoupler, the transient signal may cause the output to spike below V (which consti tutes a CMR H failure). By using the recommended circuit in Figure, good CMR can be achieved. (In the case of the -N families, a minimum CMR of kv/µs is guaranteed using this circuit.) The balanced I LED -setting resistors help equalize I LP and I LN to reduce the amount by which I LED is modulated from transient coupling through C LA and C LC. CMR with Other Drive Circuits CMR performance with drive circuits other than that shown in Figure may be enhanced by following these guidelines:. Use of drive circuits where current is shunted from the LED in the LED off state (as shown in Figures and ). This is beneficial for good CMR H.. Use of H >. ma. This is good for high CMR L. Using any one of the drive circuits in Figures - with = ma will result in a typical CMR of kv/µs for the HCPL-N family, as long as the PC board layout practices are followed. Figure shows a circuit which can be used with any totem-pole-output TTL/LSTTL/HCMOS logic gate. The buffer PNP transistor allows the circuit to be used with logic devices which have low current-sinking capability. It also helps maintain the driving-gate power-supply current at a constant level to minimize ground shifting for other devices connected to the input-supply ground. When using an open-collector TTL or open-drain CMOS logic gate, the circuit in Figure may be used. When using a CMOS gate to drive the optocoupler, the circuit shown in Figure may be used. The diode in parallel with the R LED speeds the turn-off of the optocoupler LED. V CC / R LED / R LED I LP I LN C LA C LC SHIELD. µf pf Ω V CC + L (ANY TTL/CMOS GATE) Ω (MAX) N9 (ANY PNP) HCPL-X LED + V CM Figure. AC equivalent circuit for HCPL-X. Figure. TTL interface circuit for the HCPL-A/-N families.

16 V CC Ω HCPL-X V CC N HCPL-A/N HC (OR ANY OPEN-COLLECTOR/ OPEN-DRAIN LOGIC GATE) LED HC (OR ANY TOTEM-POLE OUTPUT LOGIC GATE) Ω LED Figure. TTL open-collector/open drain gate drive circuit for HCPL-A/-N families. Figure. CMOS gate drive circuit for HCPL-A/-N families. If I < I, LP LN LED Current If I > I, LP LN LED Current If dv CM /dt Is: then I LP Flows: and I LN Flows: Is Momentarily: Is Momentarily: positive (>) away from LED away from LED increased decreased anode through C LA cathode through C LC negative (<) toward LED toward LED decreased increased anode through C LA cathode through C LC Propagation Delay, Pulse-Width Distortion and Propagation Delay Skew Propagation delay is a figure of merit which describes how quickly a logic signal propagates through a system. The propaga tion delay from low to high (t PLH ) is the amount of time required for an input signal to propagate to the output, causing the output to change from low to high. Similarly, the propagation delay from high to low (t PHL ) is the amount of time required for the input signal to propagate to the output, causing the output to change from high to low (see Figure 9). Pulse-width distortion (PWD) results when t PLH and t PHL differ in value. PWD is defined as the difference between t PLH and t PHL and often determines the maximum data rate capability of a transmission system. PWD can be expressed in percent by dividing the PWD (in ns) by the minimum pulse width (in ns) being transmitted. Typically, PWD on the order of -% of the minimum pulse width is tolerable; the exact figure depends on the particular appli cation (RS, RS, T-, etc.). Propagation delay skew, t PSK, is an important parameter to con sider in parallel data applications where synchronization of signals on parallel data lines is a con cern. If the parallel data is being sent through a group of opto- coup lers, differences in propaga tion delays will cause the data to arrive at the outputs of the opto couplers at different times. If this difference in propagation delay is large enough it will determine the maximum rate at which parallel data can be sent through the optocouplers. Propagation delay skew is defined as the difference between the minimum and maximum propaga tion delays, either t PLH or t PHL, for any given group of optocouplers which are operating under the same conditions (i.e., the same drive current, supply voltage, output load, and operating temperature). As illustrated in Figure, if the inputs of a group of optocouplers are switched either ON or OFF at the same time, t PSK is the differ ence between the shortest propagation delay, either t PLH or t PHL, and the longest propagation delay, either t PLH or t PHL. As mentioned earlier, t PSK can determine the maximum parallel data transmission rate. Figure is the timing diagram of a typical parallel data application with both the clock and the data lines being sent through optocouplers.

17 The figure shows data and clock signals at the inputs and outputs of the optocouplers. To obtain the maximum data transmission rate, both edges of the clock signal are being used to clock the data; if only one edge were used, the clock signal would need to be twice as fast. Propagation delay skew repre sents the uncertainty of where an edge might be after being sent through an optocoupler. Figure shows that there will be uncertainty in both the data and the clock lines. It is important that these two areas of uncer tainty not overlap, otherwise the clock signal might arrive before all of the data outputs have settled, or some of the data outputs may start to change before the clock signal has arrived. From these considera tions, the absolute minimum pulse width that can be sent through optocouplers in a parallel application is twice t PSK. A cautious design should use a slightly longer pulse width to ensure that any additional uncertainty in the rest of the circuit does not cause a problem. The t PSK specified optocouplers offer the advantages of guaran teed specifications for propaga tion delays, pulsewidth distortion, and propagation delay skew over the recommended temperature, input current, and power supply ranges. %. V TPHL %. V TPLH t PSK Figure. Illustration of propagation delay skew t PSK. DATA INPUTS CLOCK DATA OUTPUTS t PSK CLOCK t PSK Figure. Parallel data transmission example. For product information and a complete list of distributors, please go to our website: Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright - Avago Technologies. All rights reserved. Obsoletes AV-EN AV-9EN - April,