Features. Applications

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HCPL-9000/-0900, -900/-090, HCPL-90/-09, -900J/-090J, HCPL-90J/-09J, -90J/-09J High Speed Digital Isolators Data Sheet Lead (Pb) Free RoHS 6 fully compliant RoHS 6 fully compliant options available;

The symmetric magnetic coupling barrier gives these devices a typical pulse width distortion of ns, a typical propagation delay skew of 4 ns and 00 Mbaud data rate, making them the industry s fastest

1 HCPL-9000/-0900, -900/-090, HCPL-90/-09, -900J/-090J, HCPL-90J/-09J, -90J/-09J High Speed Digital Isolators Data Sheet Lead (Pb) Free RoHS 6 fully compliant RoHS 6 fully compliant options available; -xxxe denotes a lead-free product Description The HCPL-90xx and HCPL-09xx CMOS digital isolators feature high speed performance and excellent transient immunity specifications. The symmetric magnetic coupling barrier gives these devices a typical pulse width distortion of ns, a typical propagation delay skew of 4 ns and 00 Mbaud data rate, making them the industry s fastest digital isolators. The single channel digital isolators (HCPL-9000/ -0900) features an active-low logic output enable. The dual channel digital isolators are configured as unidirectional (HCPL-900/-090) and bi-directional (HCPL-90/-09), operating in full duplex mode making it ideal for digital fieldbus applications. The quad channel digital isolators are configured as unidirectional (HCPL-900J/-090J), two channels in one direction and two channels in opposite direction (HCPL- 90J/-09J), and one channel in one direction and three channels in opposite direction (HCPL-90J/-09J). These high channel density make them ideally suited to isolating data conversion devices, parallel buses and peripheral interfaces. They are available in 8-pin PDIP, 8-pin Gull Wing, 8 pin SOIC packages, and 6 pin SOIC narrow-body and wide-body packages. They are specified over the temperature range of -40 C to +00 C. Features +.V and +5V TTL/CMOS compatible ns max. pulse width distortion 6 ns max. propagation delay skew 5 ns max. propagation delay High speed: 00 MBd 5 kv/µs min. common mode rejection Tri-state output (HCPL-9000/-0900) 500 V RMS isolation UL577 and IEC 600- approved Applications Digital fieldbus isolation Multiplexed data transmission Computer peripheral interface High speed digital systems Isolated data interfaces Logic level shifting CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD.

2 Selection Guide Device Number Channel Configuration Package HCPL-9000 Single 8-pin DIP (00 Mil) HCPL-0900 Single 8-pin Small Outline HCPL-900 Dual 8-pin DIP (00 Mil) HCPL-090 Dual 8-pin Small Outline HCPL-90 Dual, Bi-Directional 8-pin DIP (00 Mil) HCPL-09 Dual, Bi-Directional 8-pin Small Outline HCPL-900J Quad 6-pin Small Outline, Wide Body HCPL-090J Quad 6-pin Small Outline, Narrow Body HCPL-90J Quad, /, Bi-Directional 6-pin Small Outline, Wide Body HCPL-09J Quad, /, Bi-Directional 6-pin Small Outline, Narrow Body HCPL-90J Quad, /, Bi-Directional 6-pin Small Outline, Wide Body HCPL-09J Quad, /, Bi-Directional 6-pin Small Outline, Narrow Body Ordering Information HCPL-09xx and HCPL-90xx are UL Recognized with 500 V rms for minute per UL577. Option RoHS Non RoHS Surface Gull Tape & Part number Compliant Compliant Package Mount Wing Reel Quantity HCPL-9000 HCPL-900 HCPL-90 HCPL-0900 HCPL-090 HCPL-09 HCPL-900J HCPL-90J HCPL-90J HCPL-090J HCPL-09J HCPL-09J -000E No option 00mil 50 per tube -00E -00 DIP-8 X X 50 per tube -500E -500 X X X 000 per reel -000E No option X 00 per tube SO-8-500E -500 X X 500 per reel -000E No option Wide Body X 50 per tube -500E -500 SO-6 X X 000 per reel -000E No option Narrow Body X 50 per tube -500E -500 SO-6 X X 000 per reel To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. Example : HCPL E to order product of 00mil DIP Gull Wing Surface Mount package in Tape and Reel in RoHS compliant. Example : HCPL-0900 to order product of SO-8 package in tube packaging and non RoHS compliant. Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.

3 Pin Description Symbol Description V DD Power Supply Power Supply IN X OUT X Logic Input Signal Logic Output Signal GND Power Supply Ground GND Power Supply Ground V OE NC Logic Output Enable (Single Channel), Active Low Not Connected Functional Diagrams Single Channel V DD IN NC Galvanic Isolation 8 7 V OE 6 OUT GND 4 5 GND HCPL-9000/0900 Truth Table IN V OE OUT L L L H L H L H Z H H Z Dual Channel V DD 8 V DD 8 IN IN Galvanic Isolation 7 OUT 6 OUT GND 4 5 GND HCPL-900/090 IN OUT Galvanic Isolation GND 4 5 GND HCPL-90/09 7 OUT 6 IN Quad Channel V DD 6 V DD 6 V DD 6 GND 5 GND GND 5 GND GND 5 GND IN IN IN IN Galvanic Isolation 4 OUT OUT OUT OUT 4 IN IN OUT OUT Galvanic Isolation 4 OUT OUT IN IN 4 IN IN IN OUT Galvanic Isolation 4 OUT OUT OUT IN 4 NC 7 0 NC NC 7 0 NC NC 7 0 NC GND 8 9 GND GND 8 9 GND GND 8 9 GND HCPL-900J/-090J HCPL-90J/-09J HCPL-90J/-09J

4 Package Outline Drawings HCPL-9000, HCPL-900 and HCPL-90 Standard DIP Packages (6.096) 0.60 (6.604) (9.000) (0.60) 0.90 (7.66) 0.0 (7.874) 0.55 (.97) 0.65 (.65) 0.00 (0.76) (.4) 0.05 (0.80) 0.0 (0.584) (.4) (.65) 0.05 (0.8) 0.05 (0.889) (.86) 0.0 (.794) 0.0 (.048) 0.50 (.80) 0.00 (7.60) 0.70 (9.98) DIMENSIONS: INCHES (MILLIMETERS) HCPL-9000, HCPL-900 and HCPL-90 Gull Wing Surface Mount Option 00 PAD LOCATION (for reference only) (0.0) 0.05 (0.8) 8 MIN MAX 0.60 (9.000) (0.60) (.06) (.94) (6.096) 0.60 (6.604) 0.90 TYP. (4.86) 0.70 (9.98) 0.90 (9.906) (.94) (.778) 0.05 (0.8) 0.05 (0.65) 0.00 (0.76) (.4) (.4) (.65) 0.0 (.048) 0.50 (.80) 0.70 (9.400) 0.90 (9.900) 0.90 (7.70) 0.0 (7.870) (0.0) 0.0 (0.0) 0.00 (0.760) (.400) 0.00 (.540) BSC 0.05 (0.6) 0.05 (0.89) 0.05 (0.85) 0.05 (0.885) NOM. MIN DIMENSIONS INCHES (MILLIMETERS) MAX LEAD COPLANARITY = INCHES (0.0 mm) 4

5 HCPL-0900, HCPL-090 and HCPL-09 Small Outline SO-8 Package 0.89 (4.80) 0.97 (5.00) (5.80) 0.44 (6.0) 0.50 (.80) 0.57 (4.00) (.7) (.75) 0.0 (0.) 0.00 (0.5) (0.0) 0.00 (0.5) 0.00 (0.5) 0.00 (0.50) x (0.9) 0.00 (0.5) (.06) (.54) DIMENSIONS: INCHES (MILLIMETERS) MIN MAX 0.06 (0.40) (.7) HCPL-900J, HCPL-90J and HCPL-90J Wide Body SOIC-6 Package 0.97 (0.084) 0.4 (0.490) Pin indent (0.007) 0.49 (0.64) 0.0 (0.0) 0.00 (0.508) 7 TYP 0.09 (.7) 0.05 (.670) 7 TYP 0.87 (7.90) 0.00 (7.60) (.0) 0.00 (.54) (.06) (.54) DIMENSIONS: INCHES (MILLIMETERS) MIN MAX (0.06) 0.0 (0.00) (0.00) 0.0 (0.0) 0.06 (0.40) (.7) 5

6 HCPL-090J, HCPL-09J and HCPL-09J Narrow Body SOIC-6 Package 0.86 (9.80) 0.94 (9.999) Pin indent (5.79) 0.44 (6.97) 0.5 (.86) 0.57 (.988) 0.0 (0.0) 0.00 (0.508) (.7) 0.07 (.800) (0.00) 0.0 (0.0) (.00) (.70) (.06) (.54) DIMENSIONS: INCHES (MILLIMETERS) MIN MAX (0.0) 0.0 (0.00) 0.06 (0.406) (.70) Package Characteristics Parameter Symbol Min. Typ. Max. Units Test Conditions Capacitance (Input-Output) [] C I-O pf f = MHz Single Channel. Dual Channel.0 Quad Channel 4.0 Thermal Resistance θ JCT C/W Thermocouple located at 8-Pin PDIP 54 center underside of package 8-Pin SOIC 44 6-Pin SOIC Narrow Body 4 6-Pin SOIC Wide Body 8 Package Power Dissipation P PD mw 8-Pin PDIP 50 8-Pin SOIC 50 6-Pin SOIC Narrow Body 50 6-Pin SOIC Wide Body 50 Notes:. Single and dual channels device are considered two-terminal devices: pins -4 shorted and pins 5-8 shorted. Quad channel devices are considered two terminal devices: pins -8 shorted and pins 9-6 shorted. This product has been tested for electrostatic sensitivity to the limits stated in the specifications. However, Avago recommends that all integrated circuits be handled with appropriate care to avoid damage. Damage caused by inappropriate handling or storage could range from performance degradation to complete failure. 6

7 Insulation and Safety Related Specifications Parameters Condition Min. Typ. Max. Units Barrier Impedance Single Channel >0 4 Dual Channel >0 4 Quad Channel >0 4 7 Creepage Distance (External) 8-Pin PDIP Pin SOIC Pin SOIC Narrow Body Pin SOIC Wide Body 8.08 Leakage Current 40 V RMS 0. µa 60 Hz Ω pf mm IEC600- Insulation Characteristics* Description Installation classification per DIN VDE 00/.89, Table Symbol HCPL-0900 HCPL-090 HCPL-090J HCPL-09J HCPL-09J HCPL-9000 HCPL-900 HCPL-900J HCPL-90J HCPL-90J for rated mains voltage 50 Vrms I III I IV for rated mains voltage 00 Vrms Pollution Degree (DIN VDE 00/.89) Maximum Working Insulation Voltage VIORM Vrms I III Units Soldering Profile The recommended reflow soldering conditions are per JEDEC Standard J-STD-00 (latest revision). 7

8 Absolute Maximum Ratings Parameters Symbol Min. Max. Units Storage Temperature T S C Ambient Operating Temperature [] T A 55 5 C Supply Voltage V DD, V Input Voltage V IN 0.5 V DD +0.5 V Voltage Output Enable (HCPL-9000/-0900) V OE V Output Voltage V OUT V Output Current Drive I OUT 0 ma Lead Solder Temperature (0s) 60 C ESD kv Human Body Model Notes:. Absolute Maximum ambient operating temperature means the device will not be damaged if operated under these conditions. It does not guarantee performance. Recommended Operating Conditions Parameters Symbol Min. Max. Units Ambient Operating Temperature T A C Supply Voltage V DD, V Logic High Input Voltage V IH.4 V DD V Logic Low Input Voltage V IL V Input Signal Rise and Fall Times t IR, t IF µs This product has been tested for electrostatic sensitivity to the limits stated in the specifications. However, Avago recommends that all integrated circuits be handled with appropriate care to avoid damage. Damage caused by inappropriate handling or storage could range from performance degradation to complete failure. 8

9 .V operation: Electrical Specifications Test conditions that are not specified can be anywhere within the recommended operating range. All typical specifications are at T A =+5 C, V DD = = +. V. Parameter Symbol Min. Typ. Max. Units Test Conditions Quiescent Supply Current I DD ma V IN = 0V HCPL-9000/ HCPL-900/ HCPL-90/ HCPL-900J/-090J HCPL-90J/-09J. 4.0 HCPL-90J/-09J.5.0 Quiescent Supply Current I DD ma V IN = 0V HCPL-9000/ HCPL-900/ HCPL-90/ HCPL-900J/-090J HCPL-90J/-09J. 4.0 HCPL-90J/-09J Logic Input Current I IN -0 0 µa Logic High Output Voltage V OH 0. V I OUT = -0 µa, V IN =V IH 0.8* 0.5 V I OUT = -4 ma, V IN =V IH Logic Low Output Voltage V OL 0 0. V I OUT = 0 µa, V IN =V IL V I OUT = 4 ma, V IN =V IL Switching Specifications Maximum Data Rate 00 0 MBd C L = 5 pf Clock Frequency fmax 50 MHz Propagation Delay Time to Logic t PHL 8 ns Low Output Propagation Delay Time tologic t PLH 8 ns High Output Pulse Width t PW 0 ns Pulse Width Distortion [] PWD ns t PHL t PLH Propagation Delay Skew [] t PSK 4 6 ns Output Rise Time (0 90%) t R 4 ns Output Fall Time (0 90%) t F 4 ns Propagation Delay Enable to Output (Single Channel) High to High Impedance t PHZ 9 Low to High Impedance t PLZ High Impedance to High t PZH High Impedance to Low t PZL Channel-to-Channel Skew t CSK ns (Dual and Quad Channels) Common Mode Transient Immunity CM H 5 8 kv/µs V cm = 000V (Output Logic High or Logic Low) [] CM L Notes:. PWD is defined as t PHL -t PLH. %PWD is equal to the PWD divided by the pulse width.. t PSK is equal to the magnitude of the worst case difference in t PHL and/or t PLH that will be seen between units at 5 C.. CM H is the maximum common mode voltage slew rate that can be sustained while maintaining V OUT > 0.8. CM L is the maximum common mode input voltage that can be sustained while maintaining V OUT < 0.8V. The common mode voltage slew rates apply to both rising and falling common mode voltage edges. This product has been tested for electrostatic sensitivity to the limits stated in the specifications. However, Avago recommends that all integrated circuits be handled with appropriate care to avoid damage. Damage caused by inappropriate handling or storage could range from performance degradation to complete failure.

10 5V operation: Electrical Specifications Test conditions that are not specified can be anywhere within the recommended operating range. All typical specifications are at T A =+5 C, V DD = = +5.0 V. Parameter Symbol Min. Typ. Max. Units Test Conditions Quiescent Supply Current I DD ma V IN = 0V HCPL-9000/ HCPL-900/ HCPL-90/ HCPL-900J/-090J HCPL-90J/-09J HCPL-90J/-09J.5.0 Quiescent Supply Current I DD ma V IN = 0V HCPL-9000/ HCPL-900/ HCPL-90/ HCPL-900J/-090J HCPL-90J/-09J HCPL-90J/-09J Logic Input Current I IN -0 0 µa Logic High Output Voltage V OH 0. V I OUT = -0 µa, V IN =V IH 0.8* 0.5 V I OUT = -4 ma, V IN =V IH Logic Low Output Voltage V OL 0 0. V I OUT = 0 µa, V IN =V IL V I OUT = 4 ma, V IN =V IL Switching Specifications Maximum Data Rate 00 0 MBd C L = 5 pf Clock Frequency fmax 50 MHz Propagation Delay Time to Logic t PHL 0 5 ns Low Output Propagation Delay Time to Logic t PLH 0 5 ns High Output Pulse Width t PW 0 ns Pulse Width Distortion [] PWD ns t PHL t PLH Propagation Delay Skew [] t PSK 4 6 ns Output Rise Time (0 90%) t R ns Output Fall Time (0 90%) t F ns Propagation Delay Enable to Output (Single Channel) High to High Impedance t PHZ 0 Low to High Impedance t PLZ High Impedance to High t PZH High Impedance to Low t PZL Channel-to-Channel Skew t CSK ns (Dual and Quad Channels) Common Mode Transient Immunity CM H 5 8 kv/µs V cm = 000V (Output Logic High or Logic Low) [] CM L Notes:. PWD is defined as t PHL -t PLH. %PWD is equal to the PWD divided by the pulse width.. t PSK is equal to the magnitude of the worst case difference in t PHL and/or t PLH that will be seen between units at 5 C.. CM H is the maximum common mode voltage slew rate that can be sustained while maintaining V OUT > 0.8. CM L is the maximum common mode input voltage that can be sustained while maintaining V OUT < 0.8V. The common mode voltage slew rates apply to both rising and falling common mode voltage edges. This product has been tested for electrostatic sensitivity to the limits stated in the specifications. However, Avago recommends that all integrated circuits be handled with appropriate care to avoid damage. Damage caused by inappropriate handling or storage could range from performance degradation to complete failure.

11 Mixed 5V/.V or.v/5v operation: Electrical Specifications Test conditions that are not specified can be anywhere within the recommended operating range. All typical specifications are at T A =+5 C, V DD = +5.0 V, = +.V. Parameter Symbol Min. Typ. Max. Units Test Conditions HCPL-9000/-0900 I DD HCPL-900/ HCPL-90/ HCPL-900J/-090J HCPL-90J/-09J HCPL-90J/-09J.5.0 Quiescent Supply Current I DD ma V IN = 0V HCPL-9000/ HCPL-900/ HCPL-90/ HCPL-900J/-090J HCPL-90J/-09J HCPL-90J/-09J Logic Input Current I IN -0 0 µa Logic High Output Voltage V OH 0. V I OUT = -0 µa, V IN =V IH 0.8* 0.5 V I OUT = -4 ma, V IN =V IH Logic Low Output Voltage V OL 0 0. V I OUT = 0 µa, V IN =V IL V I OUT = 4 ma, V IN =V IL Switching Specifications Maximum Data Rate 00 0 MBd C L = 5 pf Clock Frequency fmax 50 MHz Propagation Delay Time to Logic t PHL 8 ns Low Output Propagation Delay Time to Logic t PLH 8 ns High Output Pulse Width t PW 0 ns Pulse Width Distortion [] PWD ns t PHL t PLH Propagation Delay Skew [] t PSK 4 6 ns Output Rise Time (0 90%) t R 4 ns Output Fall Time (0 90%) t F 4 ns Propagation Delay Enable to Output (Single Channel) High to High Impedance t PHZ Low to High Impedance t PLZ High Impedance to High t PZH High Impedance to Low t PZL Channel-to-Channel Skew t CSK ns (Dual and Quad Channels) Common Mode Transient Immunity CM H 5 8 kv/µs V cm = 000V (Output Logic High or Logic Low) [] CM L Notes:. PWD is defined as t PHL -t PLH. %PWD is equal to the PWD divided by the pulse width.. t PSK is equal to the magnitude of the worst case difference in t PHL and/or t PLH that will be seen between units at 5 C.. CM H is the maximum common mode voltage slew rate that can be sustained while maintaining V OUT > 0.8. CM L is the maximum common mode input voltage that can be sustained while maintaining V OUT < 0.8V. The common mode voltage slew rates apply to both rising and falling common mode voltage edges. This product has been tested for electrostatic sensitivity to the limits stated in the specifications. However, Avago recommends that all integrated circuits be handled with appropriate care to avoid damage. Damage caused by inappropriate handling or storage could range from performance degradation to complete failure.

12 Applications Information Power Consumption The HCPL-90xx and HCPL-09xx CMOS digital isolators achieves low power consumption from the manner by which they transmit data across isolation barrier. By detecting the edge transitions of the input logic signal and converting this to a narrow current pulse, which drives the isolation barrier, the isolator then latches the input logic state in the output latch. Since the current pulses are narrow, about.5 ns wide, the power consumption is independent of mark-to-space ratio and solely dependent on frequency. The approximate power supply current per channel is: I(Input) = 40(f/fmax)(/4) ma where f = operating frequency, fmax = 50 MHz. Bypassing and PC Board Layout The HCPL-90xx and HCPL-09xx digital isolators are extremely easy to use. No external interface circuitry is required because the isolators use high-speed CMOS IC technology allowing CMOS logic to be connected directly to the inputs and outputs. As shown in Figure, the only external components required for proper operation are two 47 nf ceramic capacitors for decoupling the power supplies. For each capacitor, the total lead length between both ends of the capacitor and the power-supply pins should not exceed 0 mm. Figure illustrates the recommended printed circuit board layout for the HCPL-9000 or HCPL For data rates in excess of 0MBd, use of ground planes for both GND and GND is highly recommended. Signal Status on Start-up and Shut Down To minimize power dissipation, the input signals to the channels of HCPL-90xx and HCPL-09xx digital isolators are differentiated and then latched on the output side of the isolation barrier to reconstruct the signal. This could result in an ambiguous output state depending on power up, shutdown and power loss sequencing. Therefore, the designer should consider the inclusion of an initialization signal in this start-up circuit. Initialization consists of toggling the input either high then low or low then high. V DD IN 8 7 V OE C C NC 6 HCPL-9000 or HCPL-0900 OUT GND 4 5 GND Note: C, C = 47 nf ceramic capacitors Figure. Functional Diagram of Single Channel HCPL-0900 or HCPL V DD IN C HCPL-9000 or HCPL-0900 V OE C OUT GND GND Figure. Recommended Printed Circuit Board Layout.

13 Propagation Delay, Pulse Width Distortion and Propagation Delay Skew Propagation Delay is a figure of merit, which describes how quickly a logic signal propagates through a system as illustrated in Figure. INPUT V IN OUTPUT V OUT 0% tplh 90% tphl 5 V CMOS VOH.5 V CMOS VOL Figure. Timing Diagrams to Illustrate Propagation Delay, t PLH and t PHL. The propagation delay from low to high, t PLH, is the amount of time required for an input signal to propagate to the output, causing the output to change from low to high. Similarly, the propagation delay from high to low, t PHL, is the amount of time required for the input signal to propagate to the output, causing the output to change from high to low. Pulse Width Distortion, PWD, is the difference between t PHL and t PLH and often determines the maximum data rate capability of a transmission system. PWD can be expressed in percent by dividing the PWD (in ns) by the minimum pulse width (in ns) being transmitted. Typically, PWD on the order of 0 0% of the minimum pulse width is tolerable. Propagation Delay Skew, t PSK, and Channel-to-Channel Skew, t CSK, are critical parameters to consider in parallel data transmission applications where synchronization of signals on parallel data lines is a concern. If the parallel data is being sent through channels of the digital isolators, differences in propagation delays will cause the data to arrive at the outputs of the digital isolators at different times. If this difference in propagation delay is large enough, it will limit the maximum transmission rate at which parallel data can be sent through the digital isolators. t PSK is defined as the difference between the minimum and maximum propagation delays, either t PLH or t PHL, among two or more devices which are operating under the same conditions (i.e., the same drive current, supply voltage, output load, and operating temperature). t CSK is defined as the difference between the minimum and maximum propagation delays, either t PLH or t PHL, among two or more channels within a single device (applicable to dual and quad channel devices) which are operating under the same conditions. 90% 50% 0% 0 V As illustrated in Figure 4, if the inputs of two or more devices are switched either ON or OFF at the same time, t PSK is the difference between the minimum propagation delay, either t PLH or t PHL, and the maximum propagation delay, either t PLH or t PHL. V IN V OUT V IN V OUT 50%.5 V CMOS 50% t PSK.5 V CMOS Figure 4. Timing Diagrams to Illustrate Propagation Delay Skew. As mentioned earlier, t PSK, can determine the maximum parallel data transmission rate. Figure 5 shows the timing diagram of a typical parallel data transmission application with both the clock and data lines being sent through the digital isolators. The figure shows data and clock signals at the inputs and outputs of the digital isolators. In this case, the data is clocked off the rising edge of the clock. INPUTS OUTPUTS DATA CLOCK DATA CLOCK t PSK t PSK Figure 5. Parallel Data Transmission.

14 Propagation delay skew represents the uncertainty of where an edge might be after being sent through a digital isolator. Figure 5 shows that there will be uncertainty in both the data and clock lines. It is important that these two areas of uncertainty not overlap, otherwise the clock signal might arrive before all of the data outputs have settled, or some of the data outputs may start to change before the clock signal has arrived. From these considerations, the absolute minimum pulse width that can be sent through digital isolators in a parallel application is twice t PSK. A cautious design should use a slightly longer pulse width to ensure that any additional uncertainty in the rest of the circuit does not cause a problem. Figure 6 shows the minimum pulse width, rise and fall time, and propagation delay enable to output waveforms for HCPL-9000 or HCPL % V IN V OUT 50% t PLZ t PZH 90% 0% 0% 90% t PHZ t PZL t PW t F t R V OE t PW Minimum Pulse Width t PHZ Propagation Delay, High to High Impedance t PLZ Propagation Delay, Low to High Impedance t PZL Propagation Delay, High Impedance to Low t PZH Propagation Delay, High Impedance to High t R Rise Time t F Fall Time Figure 6. Timing Diagrams to Illustrate the Minimum Pulse Width, Rise and Fall Time, and Propagation Delay Enable to Output Waveforms for HCPL 9000 or HCPL For product information and a complete list of distributors, please go to our web site: Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright Avago Technologies. All rights reserved. Obsoletes EN AV0-07EN - May 0, 0

HCPL-9000/-0900, -9030/-0930, HCPL-9031/-0931, -900J/-090J, HCPL-901J/-091J, -902J/-092J

Data Sheet HCPL-9000/-0900, -9030/-0930, HCPL-901J/-091J, -902J/-092J Description The HCPL-90xx and HCPL-09xx CMOS digital isolators feature high speed performance and excellent transient immunity specifications.