Features. Applications

Transcription

1 HCPL-/// ns Propagation Delay, CMOS Optocoupler Data Sheet Lead (Pb) Free RoHS fully compliant RoHS fully compliant options available; -xxxe denotes a lead-free product Description Available in either an -pin DIP or SO- package style respectively, the HCPL-X or HCPL-X optocouplers utilize the latest CMOS IC technology to achieve outstanding performance with very low power consumption. The HCPL-X/X require only two bypass capacitors for complete CMOS compatability. Basic building blocks of the HCPL-X/X are a CMOS LED driver IC, a high speed LED and a CMOS detector IC. A CMOS logic input signal controls the LED driver IC which supplies current to the LED. The detector IC incorporates an integrated photodiode, a high-speed transimpedance amplifier, and a voltage comparator with an output driver. Functional Diagram **V DD V I * GND LED SHIELD I O V DD ** NC* GND Features + V CMOS compatibility ns maximum prop. delay skew High speed: MBd ns max. prop. delay kv/µs minimum common mode rejection to C temperature range Safety and regulatory approvals UL recognized Vrms for min. per UL Vrms for min. per UL (for HCPL-X option ) CSA component acceptance notice # IEC/EN/DIN EN -- V IORM = Vpeak for HCPL-X option V IORM = Vpeak for HCPL-X option Applications Digital fieldbus isolation: CC-Link, DeviceNet, Profibus, SDS AC plasma display panel level shifting Multiplexed data transmission Computer peripheral interface Microprocessor system interface * Pin is the anode of the internal LED and must be left unconnected for guaranteed data sheet performance. Pin is not connected internally. ** A. µf bypass capacitor must be connected between pins and, and and. TRUTH TABLE POSITIVE LOGIC V I LED V o OUTPUT H OFF H L ON L CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD.

2 Selection Guide -Pin DIP Small Outline ( Mil) SO- Data Rate PWD HCPL- HCPL- MB ns HCPL- HCPL- MB ns Ordering Information HCPL-, HCPL-, HCPL- and HCPL- are UL Recognized with Vrms for minute per UL. Option Part RoHS non RoHS Surface Gull Tape UL Vrms/ IEC/EN/DIN Number Compliant Compliant Package Mount Wing & Reel Minute rating EN -- Quantity -E no option per tube -E # X X per tube -E # X X X per reel HCPL- -E - mil X per tube HCPL- -E - DIP- X X X per tube -E - X X X X per reel -E # X per tube -E # X X X per tube -E # X X X X per reel -E no option per tube HCPL- -E # SO- X X X per reel HCPL- -E # X per tube -E # X X X X per reel To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. Example : HCPL--E to order product of Gull Wing Surface Mount package in Tape and Reel packaging with IEC/EN/DIN EN -- Safety Approval and RoHS compliant. Example : HCPL- to order product of Small Outline SO- package in Tube packaging and non RoHS compliant. Option datasheets are available. Contact your Avago sales representative or authorized distributor for information. Remarks: The notation #XXX is used for existing products, while (new) products launched since July, and RoHS compliant will use XXXE.

3 Package Outline Drawing HCPL-X -Pin DIP Package 9. ±. (. ±.). ±. (. ±.) TYPE NUMBER A XXXXV OPTION CODE* DATE CODE. ±. (. ±.) YYWW.9 (.) MAX.. ±. (. ±.). (.) MAX.. (.) MAX. TYP (. +.) -.). ±. (. ±.).9 (.) MIN.. (.) MAX.. ±. (. ±.). (.) MIN. DIMENSIONS IN MILLIMETERS AND (INCHES). *OPTION AND NOT MARKED. NOTE: FLOATING LEAD PROTRUSION IS. mm ( mils) MAX.

4 Package Outline Drawing HCPL-X Package with Gull Wing Surface Mount Option LAND PATTERN RECOMMENDATION 9. ±. (. ±.). (.). ±. (. ±.).9 (.). (.). (.).9 (.) MAX.. (.) MAX.. ±. (. ±.) 9. ±. (. ±.). ±. (. ±.) (. +.) -.). ±. (. ±.).. ±. (.) (. ±.) BSC DIMENSIONS IN MILLIMETERS (INCHES). LEAD COPLANARITY =. mm (. INCHES).. ±. (. ±.) NOM. NOTE: FLOATING LEAD PROTRUSION IS. mm ( mils) MAX. Package Outline Drawing HCPL-X Outline Drawing (Small Outline SO- Package) LAND PATTERN RECOMMENDATION.9 ±. (. ±.) PIN ONE XXXV YWW.99 ±. (. ±.). ±. (. ±.). (.) BSC TYPE NUMBER (LAST DIGITS) DATE CODE. (.).9 (.).9 (.9) *. ±. (. ±.) X. (.). ±. (. ±.). (.) ~. ±. (.9 ±.) * TOTAL PACKAGE LENGTH (INCLUSIVE OF MOLD FLASH). ±. (. ±.) DIMENSIONS IN MILLIMETERS (INCHES). LEAD COPLANARITY =. mm (. INCHES) MAX.. (.) MIN.. ±. (. ±.) OPTION NUMBER NOT MARKED. NOTE: FLOATING LEAD PROTRUSION IS. mm ( mils) MAX.

5 Solder Reflow Thermal Profile TEMPERATURE ( C) PREHEATING RATE C + C/. C/SEC. REFLOW HEATING RATE. C ±. C/SEC. C C C C + C/. C. C ±. C/SEC. PREHEATING TIME C, 9 + SEC. PEAK TEMP. C SEC. SEC. SEC. PEAK TEMP. C SOLDERING TIME C PEAK TEMP. C ROOM TEMPERATURE TIME (SECONDS) TIGHT TYPICAL LOOSE Note: Non-halide flux should be used. Pb-Free IR Profile TEMPERATURE T p +/- C T L C RAMP-UP C/SEC. MAX. T smax - C T smin t s PREHEAT to SEC. t p t L TIME WITHIN C of ACTUAL PEAK TEMPERATURE - SEC. RAMP-DOWN C/SEC. MAX. to SEC. t C to PEAK TIME NOTES: THE TIME FROM C to PEAK TEMPERATURE = MINUTES MAX. T smax = C, T smin = C Note: Non-halide flux should be used. Regulatory Information The HCPL-X/X have been approved by the following organizations: UL Recognized under UL, component recognition program, File E. CSA Approved under CSA Component Acceptance Notice #, File CA. IEC/EN/DIN EN -- Approved under: IEC --:99 + A: EN --: + A: DIN EN -- (VDE Teil ):-. (Option only)

6 Insulation and Safety Related Specifications Value Parameter Symbol X X Units Conditions Minimum External Air L(I)..9 mm Measured from input terminals to output Gap (Clearance) terminals, shortest distance through air. Minimum External L(I).. mm Measured from input terminals to output Tracking (Creepage) terminals, shortest distance path along body. Minimum Internal Plastic.. mm Insulation thickness between emitter and Gap (Internal Clearance) detector; also known as distance through insulation. Tracking Resistance CTI Volts DIN IEC /VDE Part (Comparative Tracking Index) Isolation Group IIIa IIIa Material Group (DIN VDE, /9, Table ) All Avago data sheets report the creepage and clearance inherent to the optocoupler component itself. These dimensions are needed as a starting point for the equipment designer when determining the circuit insulation requirements. However, once mounted on a printed circuit board, minimum creepage and clearance requirements must be met as specified for individual equipment standards. For creepage, the shortest distance path along the surface of a printed circuit board between the solder fillets of the input and output leads must be considered. There are recommended techniques such as grooves and ribs which may be used on a printed circuit board to achieve desired creepage and clearances. Creepage and clearance distances will also change depending on factors such as pollution degree and insulation level.

7 IEC/EN/DIN EN -- Insulation Related Characteristics (Option ) HCPL-X HCPL-X Description Symbol Option Option Units Installation classification per DIN VDE /.9, Table for rated mains voltage V rms I-IV I-IV for rated mains voltage V rms I-IV I-III for rated mains voltage V rms I-III Climatic Classification // // Pollution Degree (DIN VDE /.9) Maximum Working Insulation Voltage V IORM V peak Input to Output Test Voltage, Method b V PR V peak V IORM x. = V PR, % Production Test with t m = sec, Partial Discharge < pc Input to Output Test Voltage, Method a V PR 9 V peak V IORM x. = V PR, Type and Sample Test, t m = sec, Partial Discharge < pc Highest Allowable Overvoltage V IOTM V peak (Transient Overvoltage, t ini = sec) Safety Limiting Values (Maximum values allowed in the event of a failure, also see Thermal Derating curve, Figure.) Case Temperature T S C Input Current I S,INPUT ma Output Power P S,OUTPUT mw Insulation Resistance at T S, V = V R IO 9 9 Ω Refer to the front of the optocoupler section of the Isolation and Control Component Designer s Catalog, under Product Safety Regulations section IEC/EN/DIN EN --, for a detailed description. Note: These optocouplers are suitable for safe electrical isolation only within the safety limit data. Maintenance of the safety data shall be ensured by means of protective circuits. The surface mount classification is Class A in accordance with CECC. Absolute Maximum Ratings Parameter Symbol Min. Max. Units Figure Storage Temperature T S C Ambient Operating Temperature [] T A + C Supply Voltages V DD, V DD. Volts Input Voltage V I. V DD +. Volts Output Voltage. V DD +. Volts Average Output Current I O ma Lead Solder Temperature Solder Reflow Temperature Profile C for sec.,. mm below seating plane See Solder Reflow Temperature Profile Section Recommended Operating Conditions Parameter Symbol Min. Max. Units Figure Ambient Operating Temperature T A + C Supply Voltages V DD, V DD.. V Logic High Input Voltage V IH. V DD V, Logic Low Input Voltage V IL.. V Input Signal Rise and Fall Times t r, t f. ms

8 Electrical Specifications Test conditions that are not specified can be anywhere within the recommended operating range. All typical specifications are at T A = + C, V DD = V DD = + V. Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note DC Specifications Logic Low Input I DDL.. ma V I = V Supply Current Logic High Input I DDH.. ma V I = V DD Supply Current Output Supply Current I DDL. 9. ma I DDH. 9. Input Current I I µa Logic High Output H.. V I O = - µa, V I = V IH, Voltage.. I O = - ma, V I = V IH Logic Low Output L. V I O = µa, V I = V IL Voltage. V I O = µa, V I = V IL.. I O = ma, V I = V IL Switching Specifications Propagation Delay Time t PHL ns C L = pf, to Logic Low Output CMOS Signal Levels Propagation Delay Time t PLH to Logic High Output Pulse Width PW Data Rate MBd Pulse Width Distortion PWD / ns t PHL - t PLH / ns Propagation Delay Skew t PSK Output Rise Time t R 9 ns ( - 9%) Output Fall Time t F ns (9 - %) Common Mode CM H kv/µs V I = V DD, > Transient Immunity at. V DD, Logic High Output V CM = V Common Mode CM L V I = V, >. V, Transient Immunity at V CM = V Logic Low Output Input Dynamic Power C PD pf Dissipation Capacitance Output Dynamic Power C PD Dissipation Capacitance

9 Package Characteristics Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note Input-Output Momentary X V ISO Vrms RH %,, 9, Withstand Voltage X t = min., Option T A = C Resistance R I-O Ω V I-O = Vdc (Input-Output) Capacitance C I-O. pf f = MHz (Input-Output) Input Capacitance C I. Input IC Junction-to-Case -X θ jci C/W Thermocouple Thermal Resistance -X located at center Output IC Junction-to-Case -X θ jco underside of package Thermal Resistance -X Package Power Dissipation P PD mw Notes:. Absolute Maximum ambient operating temperature means the device will not be damaged if operated under these conditions. It does not guarantee functionality.. The LED is ON when V I is low and OFF when V I is high.. t PHL propagation delay is measured from the % level on the falling edge of the V I signal to the % level of the falling edge of the signal. t PLH propagation delay is measured from the % level on the rising edge of the V I signal to the % level of the rising edge of the signal.. PWD is defined as t PHL - t PLH. %PWD (percent pulse width distortion) is equal to the PWD divided by pulse width.. t PSK is equal to the magnitude of the worst case difference in t PHL and/or t PLH that will be seen between units at any given temperature within the recommended operating conditions.. CM H is the maximum common mode voltage slew rate that can be sustained while maintaining >. V DD. CM L is the maximum common mode voltage slew rate that can be sustained while maintaining <. V. The common mode voltage slew rates apply to both rising and falling common mode voltage edges.. Unloaded dynamic power dissipation is calculated as follows: C PD * V DD * f + I DD * V DD, where f is switching frequency in MHz.. Device considered a two-terminal device: pins,,, and shorted together and pins,,, and shorted together. 9. In accordance with UL, each HCPL-X is proof tested by applying an insulation test voltage V RMS for second (leakage detection current limit, I I-O µa). Each HCPL-X is proof tested by applying an insulation test voltage Vrms for second (leakage detection current limit. I I-O µa.). The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. For the continuous voltage rating refer to your equipment level safety specification or Avago Application Note entitled Optocoupler Input-Output Endurance Voltage.. C I is the capacitance measured at pin (V I ). (V) C C C V ITH (V) C C C T PLH, T PHL (ns) 9 9 T PLH T PHL..... V I (V) V DD (V) T A (C) Figure. Typical output voltage vs. input voltage. Figure. Typical input voltage switching threshold vs. input supply voltage. Figure. Typical propagation delays vs. temperature. 9

10 PWD (ns) T R (ns) 9 T F (ns) T A (C) T A (C) T A (C) Figure. Typical pulse width distortion vs. temperature. Figure. Typical rise time vs. temperature. Figure. Typical fall time vs. temperature. 9 T PLH, T PHL (ns) 9 T PHL T PLH PWD (ns) C I (pf) C I (pf) Figure. Typical propagation delays vs. output load capacitance. Figure. Typical pulse width distortion vs. output load capacitance. OUTPUT POWER P S, INPUT CURRENT I S () STANDARD PIN DIP PRODUCT P S (mw) I S (ma) T A CASE TEMPERATURE C OUTPUT POWER P S, INPUT CURRENT I S () SURFACE MOUNT SO PRODUCT P S (mw) I S (ma) T A CASE TEMPERATURE C Figure 9. Thermal derating curve, dependence of safety limiting value with case temperature per IEC/EN/DIN EN --.

11 Application Information Bypassing and PC Board Layout The HCPL-X/X optocouplers are extremely easy to use. No external interface circuitry is required because the HCPL-X/X use high-speed CMOS IC technology allowing CMOS logic to be connected directly to the inputs and outputs. As shown in Figure, the only external components required for proper operation are two bypass capacitors. Capacitor values should be between. µf and. µf. For each capacitor, the total lead length between both ends of the capacitor and the power-supply pins should not exceed mm. Figure illustrates the recommended printed circuit board layout for the HPCL- X/X. V DD V I C NC X YWW NC C V DD GND GND C, C =. µf TO. µf Figure. Recommended printed circuit board layout. V DD V DD V I C X YWW C GND GND C, C =. µf TO. µf Figure. Recommended printed circuit board layout. Propagation Delay, Pulse-Width Distortion and Propagation Delay Skew Propagation Delay is a figure of merit which describes how quickly a logic signal propagates through a system. The propagation delay from low to high (t PLH ) is the amount of time required for an input signal to propagate to the output, causing the output to change from low to high. Similarly, the propagation delay from high to low (t PHL ) is the amount of time required for the input signal to propagate to the output, causing the output to change from high to low. See Figure. INPUT V I % V CMOS V t PLH t PHL OUTPUT 9% 9% % % H. V CMOS L Figure.

12 Pulse-width distortion (PWD) is the difference between t PHL and t PLH and often determines the maximum data rate capability of a transmission system. PWD can be expressed in percent by dividing the PWD (in ns) by the minimum pulse width (in ns) being transmitted. Typically, PWD on the order of - % of the minimum pulse width is tolerable. Propagation delay skew, t PSK, is an important parameter to consider in parallel data applications where synchronization of signals on parallel data lines is a concern. If the parallel data is being sent through a group of optocouplers, differences in propagation delays will cause the data to arrive at the outputs of the optocouplers at different times. If this difference in propagation delay is large enough it will determine the maximum rate at which parallel data can be sent through the optocouplers. Propagation delay skew is defined as the difference between the minimum and maximum propagation delays, either t PLH or t PHL, for any given group of optocouplers which are operating under the same conditions (i.e., the same drive current, supply voltage, output load, and operating temperature). As illustrated in Figure, if the inputs of a group of optocouplers are switched either ON or OFF at the same time, t PSK is the difference between the shortest propagation delay, either t PLH or t PHL, and the longest propagation delay, either t PLH or t PHL. As mentioned earlier, t PSK can determine the maximum parallel data transmission rate. Figure is the timing diagram of a typical parallel data application with both the clock and data lines being sent through the optocouplers. The figure shows data and clock signals at the inputs and outputs of the optocouplers. In this case the data is assumed to be clocked off of the rising edge of the clock. V I %. V, CMOS INPUTS DATA CLOCK t PSK V I % DATA OUTPUTS t PSK. V, CMOS CLOCK t PSK Figure. Propagation delay skew waveform. Figure. Parallel data transmission example. Propagation delay skew represents the uncertainty of where an edge might be after being sent through an optocoupler. Figure shows that there will be uncertainty in both the data and clock lines. It is important that these two areas of uncertainty not overlap, otherwise the clock signal might arrive before all of the data outputs have settled, or some of the data outputs may start to change before the clock signal has arrived. From these considerations, the absolute minimum pulse width that can be sent through optocouplers in a parallel application is twice t PSK. A cautious design should use a slightly longer pulse width to ensure that any additional uncertainty in the rest of the circuit does not cause a problem. The HCPL-X/X optocouplers offer the advantage of guaranteed specifications for propagation delays, pulse-width distortion, and propagation delay skew over the recommended temperature and power supply ranges.

13 Digital Field Bus Communication Networks To date, despite its many drawbacks, the - ma analog current loop has been the most widely accepted standard for implementing process control systems. In today s manufacturing environment, however, automated systems are expected to help manage the process, not merely monitor it. With the advent of digital field bus communication networks such as CC-Link, DeviceNet, PROFIBUS, and Smart Distributed Systems (SDS), gone are the days of constrained information. Controllers can now receive multiple readings from field devices (sensors, actuators, etc.) in addition to diagnostic information. The physical model for each of these digital field bus communication networks is very similar as shown in Figure. Each includes one or more buses, an interface unit, optical isolation, transceiver, and sensing and/or actuating devices. CONTROLLER BUS INTERFACE OPTICAL FIELD BUS OPTICAL OPTICAL OPTICAL OPTICAL BUS INTERFACE BUS INTERFACE BUS INTERFACE BUS INTERFACE XXXXXX SENSOR DEVICE CONFIGURATION MOTOR STARTER YYY MOTOR CONTROLLER Figure. Typical field bus communication physical model.

14 Optical Isolation for Field Bus Networks To recognize the full benefits of these networks, each recommends providing galvanic isolation using Avago optocouplers. Since network communication is bi-directional (involving receiving data from and transmitting data onto the network), two Avago optocouplers are needed. By providing galvanic isolation, data integrity is retained via noise reduction and the elimination of false signals. In addition, the network receives maximum protection from power system faults and ground loops. Within an isolated node, such as the DeviceNet Node shown in Figure, some of the node s components are referenced to a ground other than V- of the network. These components could include such things as devices with serial ports, parallel ports, RS and RS type ports. As shown in Figure, power from the network is used only for the transceiver and input (network) side of the optocouplers. Isolation of nodes connected to any of the three types of digital field bus networks is best achieved by using the HCPL-X/X optocouplers. For each network, the HCPL-X/X satisify the critical propagation delay and pulse width distortion requirements over the temperature range of C to + C, and power supply voltage range of. V to. V. AC LINE NODE/APP SPECIFIC up/can LOCAL NODE SUPPLY HCPL x/x HCPL x/x GALVANIC BOUNDARY V REG. DRAIN/SHIELD SIGNAL POWER V+ (SIGNAL) V (SIGNAL) V+ (POWER) V (POWER) NETWORK POWER SUPPLY Figure. Typical DeviceNet Node.

15 Implementing CC-Link with the HCPL X/X CC-Link (Control and Communication Link) is developed to merge control and information in the low-level network (field network) by PCs, thereby making the multivendor environment a reality. It has data control and message-exchange function, as well as bit control function, and operates at the speed up to Mbps. Power Supplies and Bypassing The recommended CC-Link circuit is shown in Figure. Since the HCPL-X/X are fully compatible with CMOS logic level signals, the optocoupler is connected directly to the transceiver. Two bypass capacitors (with values between. µf and. µf) are required and should be located as close as possible to the input and output power supply pins of the HCPL-X/X. For each capacitor, the total lead length between both ends of capacitor and the power supply pins should not exceed mm. The bypass capacitors are required because of the high speed digital nature of the signals inside the optocoupler. DA DB DG SLD FIL SNALSNS V CC V CC A B Y Z R RE DE D GND GND. µ V DD ( V) GND HCPL-# V DD V DD V I GND GND HCPL-# V DD V DD V DD ( V) K. µ GND RD. µ GND V I GND. µ SD FG HCPL-# K K. µ HC E V DD GND NC + NC 9 HC MPU BOARD OUTPUT K HCPL-# E NC K V DD +. µ SDGATEON HC 9 GND NC HC Figure. Recommended CC-Link application circuit.

16 Implementing DeviceNet and SDS with the HCPL X/X With transmission rates up to Mbit/s, both DeviceNet and SDS are based upon the same broadcast-oriented, communications protocol the Controller Area Network (CAN). Three types of isolated nodes are recommended for use on these networks: Isolated Node Powered by the Network (Figure ), Isolated Node with Transceiver Powered by the Network (Figure 9), and Isolated Node Providing Power to the Network (Figure ). Isolated Node Powered by the Network This type of node is very flexible and as can be seen in Figure, is regarded as isolated because not all of its components have the same ground reference. Yet, all components are still powered by the network. This node contains two regulators: one is isolated and powers the CAN controller, node-specific application and isolated (node) side of the two optocouplers while the other is non-isolated. The non-isolated regulator supplies the transceiver and the non-isolated (network) half of the two optocouplers. NODE/APP SPECIFIC up/can HCPL x/x HCPL x/x REG. ISOLATED SWITCHING POWER SUPPLY GALVANIC BOUNDARY DRAIN/SHIELD SIGNAL POWER V+ (SIGNAL) V (SIGNAL) V+ (POWER) V (POWER) NETWORK POWER SUPPLY Figure. Isolated node powered by the network. Isolated Node with Transceiver Powered by the Network Figure 9 shows a node powered by both the network and another source. In this case, the transceiver and isolated (network) side of the two optocouplers are powered by the network. The rest of the node is powered by the AC line which is very beneficial when an application requires a significant amount of power. This method is also desirable as it does not heavily load the network. More importantly, the unique dual-inverting design of the HCPL-X/X ensure the network will not lockup if either AC line power to the node is lost or the node powered-off. Specifically, when input power (V DD ) to the HCPL-X/X located in the transmit path is eliminated, a RECESSIVE bus state is ensured as the HCPL X/ X output voltage ( ) go HIGH. *Bus V+ Sensing It is suggested that the Bus V+ sense block shown in Figure 9 be implemented. A locally powered node with an un-powered isolated Physical Layer will accumulate errors and become bus-off if it attempts to transmit. The Bus V+ sense signal would be used to change the BOI attribute of the DeviceNet Object to the auto-reset () value. Refer to Volume, Section... This would cause the node to continually reset until bus power was detected. Once power was detected, the BOI attribute would be returned to the hold in bus-off () value. The BOI attribute should not be left in the auto-reset () value since this defeats the jabber protection capability of the CAN error confinement. Any inexpensive low frequency optical isolator can be used to implement this feature.

17 AC LINE NODE/APP SPECIFIC NON ISO V up/can HCPL x/x HCPL x/x *HCPL x/x GALVANIC BOUNDARY REG. DRAIN/SHIELD SIGNAL POWER V+ (SIGNAL) V (SIGNAL) V+ (POWER) V (POWER) NETWORK POWER SUPPLY * OPTIONAL FOR BUS V + SENSE Figure 9. Isolated node with transceiver powered by the network. Isolated Node Providing Power to the Network Figure shows a node providing power to the network. The AC line powers a regulator which provides five () volts locally. The AC line also powers a volt isolated supply, which powers the network, and another five-volt regulator, which, in turn, powers the transceiver and isolated (network) side of the two optocouplers. This method is recommended when there are a limited number of devices on the network that don t require much power, thus eliminating the need for separate power supplies. More importantly, the unique dual-inverting design of the HCPL-X/X ensure the network will not lockup if either AC line power to the node is lost or the node powered-off. Specifically, when input power (V DD ) to the HCPL-X/X located in the transmit path is eliminated, a RECESSIVE bus state is ensured as the HCPL X/ X output voltage ( ) go HIGH. AC LINE DEVICENET NODE NODE/APP SPECIFIC V REG. up/can HCPL x/x HCPL x/x V REG. ISOLATED SWITCHING POWER SUPPLY GALVANIC BOUNDARY DRAIN/SHIELD SIGNAL POWER V+ (SIGNAL) V (SIGNAL) V+ (POWER) V (POWER) Figure. Isolated node providing power to the network.

18 Power Supplies and Bypassing The recommended DeviceNet application circuit is shown in Figure. Since the HCPL-X/X are fully compatible with CMOS logic level signals, the optocoupler is connected directly to the CAN transceiver. Two bypass capacitors (with values between. and. µf) are required and should be located as close as possible to the input and output power-supply pins of the HCPL- X/X. For each capacitor, the total lead length between both ends of the capacitor and the power supply pins should not exceed mm. The bypass capacitors are required because of the high-speed digital nature of the signals inside the optocoupler. ISO V GALVANIC BOUNDARY V TX. V IN µf. µf V DD HCPL-x HCPL-x V DD TxD V CC CANH LINEAR OR SWITCHING REGULATOR + + V+ CAN+ RX. µf GND GND GND HCPL-x HCPL-x GND GND V IN. µf + C. µf Rs C CANL REF RXD GND VREF D V C. µf V SHIELD CAN V R M V DD V DD ISO V V Figure. Recommended DeviceNet application circuit. Implementing PROFIBUS with the HCPL-X/X An acronym for Process Fieldbus, PROFIBUS is essentially a twisted-pair serial link very similar to RS- capable of achieving high-speed communication up to MBd. As shown in Figure, a PROFIBUS Controller (PBC) establishes the connection of a field automation unit (control or central processing station) or a field device to the transmission medium. The PBC consists of the line transceiver, optical isolation, frame character transmitter/receiver (UART), and the FDL/APP processor with the interface to the PROFIBUS user. PBC PROFIBUS USER: CONTROL STATION (CENTRAL PROCESSING) OR FIELD DEVICE USER INTERFACE FDL/APP PROCESSOR UART OPTICAL MEDIUM Figure. PROFIBUS Controller (PBC).

19 Power Supplies and Bypassing The recommended PROFIBUS application circuit is shown in Figure. Since the HCPL-X/X are fully compatible with CMOS logic level signals, the optocoupler is connected directly to the transceiver. Two bypass capacitors (with values between. and. µf) are required and should be located as close as possible to the input and output power-supply pins of the HCPL-X/X. For each capacitor, the total lead length between both ends of the capacitor and the power supply pins should not exceed mm. The bypass capacitors are required because of the high-speed digital nature of the signals inside the optocoupler. Being very similar to multi-station RS systems, the HCPL-N optocoupler provides a transmit disable function which is necessary to make the bus free after each master/slave transmission cycle. Specifically, the HCPL-N disables the transmitter of the line driver by putting it into a high state mode. In addition, the HCPL- N switches the RX/TX driver IC into the listen mode. The HCPL-N offers HCMOS compatibility and the high CMR performance ( kv/µs at V CM = V) essential in industrial communication interfaces. GALVANIC BOUNDARY V ISO V V DD V DD ISO V Rx. µf GND HCPL-x HCPL-x V IN GND. µf. µf R D V CC SNB A B RT + SHIELD Tx V V DD V IN V DD ISO V. µf DE RE GND. µf M. µf HCPL-x HCPL-x GND GND ISO V V V CC Tx ENABLE, kω ANODE CATHODE V E. µf Ω GND HCPL-N Figure. Recommended PROFIBUS application circuit. For product information and a complete list of distributors, please go to our website: Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies Limited in the United States and other countries. Data subject to change. Copyright - Avago Technologies Limited. All rights reserved. Obsoletes AV-EN AV-EN - June,