ACPL-W70L-000E and ACPL-K73L-000E Single-channel and Dual-channel High Speed 15 MBd CMOS optocoupler with Glitch-Free Power-Up Feature.

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1 ACPL-W7L-E and ACPL-K7L-E Single-channel and Dual-channel High Speed MBd CMOS optocoupler with Glitch-Free Power-Up Feature Data Sheet Lead (Pb) Free RoHS fully compliant RoHS fully compliant options available; -xxxe denotes a lead-free product Description The ACPL-W7L (single-channel) and ACPL-K7L (dualchannel) are MBd CMOS optocouplers in SSOIC- and SSOIC-8 package respectively. The optocouplers utilize the latest CMOS IC technology to achieve outstanding performance with very low power consumption. Basic building blocks of ACPL-W7L and ACPL-K7L are high speed LEDs and CMOS detector ICs. Each detector incorporates an integrated photodiode, a high speed transimpedance amplifier, and a voltage comparator with an output driver. Component Image Anode NC* Cathode SHIELD ACPL-W7L ACPL-K7L V DD GND Anode 8 V DD Cathode Cathode 7 Vo Vo Vo Features +.V and V CMOS compatibility ns max. pulse width distortion ns max. propagation delay ns max. propagation delay skew High speed: MBd min kv/µs minimum common mode rejection to C temperature range Glitch-Free Power-UP Feature Safety and regulatory approvals: - UL recognized: V rms for min. per UL 77 Option - CSA component acceptance Notice # - IEC/EN/DIN EN 77-- approved Option (pending) Applications Digital field bus isolation: - CANBus, RS8, USB Multiplexed data transmission Computer peripheral interface Microprocessor system interface DC/DC converter Anode SHIELD GND LED OFF ON TRUTH TABLE V O, OUTPUT L H A.µF bypass capacitor must be connected between pins and for ACPL-W7L and pins and 8 for ACPL-K7L. CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD.

2 Ordering Information ACPL-W7L and ACPL-K7L will be UL Recognized with 7 V rms for minute per UL77. Part number Option RoHS Compliant Package Surface Mount Gull Wing Tape& Reel UL V rms / Minute rating IEC/EN/DIN EN 77-- Quantity ACPL-W7L -E SSO- X per tube -E X X per reel -E X X per tube -E X X X per reel -E X X per tube -E X X X per reel ACPL-K7L -E SSO-8 X 8 per tube -E X X per reel -E X X 8 per tube -E X X X per reel -E X X 8 per tube -E X X X per reel To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. Example : ACPL-W7L-E to order product of stretched SO- package in Tape and Reel packaging in RoHS compliant. Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.

3 Package Dimensions ACPL-W7L (Stretched SO- Package) LAND PATTERN RECOMMENDATION.8.7 (..).7 (.) BSG (.8 ) -.. (.98).7 (.). (.8) ( +..8 ) (..) 7.9 (.7).. (.8.).8.7 (..).7. (.9.).. (..) DIMENSIONS IN MILLIMETERS (INCHES). LEAD COPLANARITY =. mm (. INCHES). ACPL-K7L (Stretched S-8 Package).8. (..).7 (.) BSG ( ) LAND PATTERN RECOMMENDATION. (.). (.8) (..) 7.9 (.).. (.8.).8.7 (..).7. (.9.).87.7 (.8.).. (..) DIMENSIONS IN MILLIMETERS (INCHES). LEAD COPLANARITY =. mm (. INCHES).

4 Solder Reflow Thermal Profile TEMPERATURE ( C) PREHEATING RATE C + C/. C/SEC. REFLOW HEATING RATE. C ±. C/SEC. C C C ROOM TEMPERATURE Note: Non-halide flux should be used. C + C/. C. C ±. C/SEC. PREHEATING TIME C, 9 + SEC. PEAK TEMP. C TIME (SECONDS) SEC. SEC. SEC. PEAK TEMP. C SOLDERING TIME C PEAK TEMP. C TIGHT TYPICAL LOOSE Recommended Pb-Free IR Profile TEMPERATURE Tp TL Tsmax Tsmin 7 C TIME WITHIN C of ACTUAL PEAK TEMPERATURE - C RAMP-UP C/SEC. MAX. ts PREHEAT to 8 SEC. t C to PEAK +/- C TIME Notes: The time from C to peak temperature = 8 minutes max. T smax = C, T smin = C Non-halide flux should be used tp tl - SEC. RAMP-DOWN C/SEC. MAX. to SEC. Regulatory Information The ACPL-W7L and ACPL-K7L are approved by the following organizations: UL Recognized under UL 77, component recognition program, File E. CSA Approved under CSA Component Acceptance Notice #, File CA88. IEC/EN/DIN EN 77-- Pending approval under: IEC 77--:997 + A: EN 77--: + A: DIN EN 77-- (VDE 88Teil ):- (Option only)

5 Parameter Symbol Value Units Conditions Minimum External Air Gap (Clearance) Minimum External Tracking (Creepage) Minimum Internal Plastic Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) L(I) 8. mm Measured from input terminals to output terminals, shortest distance through air. L(I) 8. mm Measured from input terminals to output terminals, shortest distance path along body..8 mm Insulation thickness between emitter and detector; also known as distance through insulation. CTI 7 Volts DIN IEC /VDE Part Isolation Group IIIa Material Group (DIN VDE, /89, Table ) All Avago Technologies data sheets report the creepage and clearance inherent to the optocoupler component itself. These dimensions are needed as a starting point for the equipment designer when determining the circuit insulation requirements. However, once mounted on a printed circuit board, minimum creepage and clearance requirements must be met as specified for individual equipment standards. For creepage, the shortest distance path along the surface of a printed circuit board between the solder fillets of the input and output leads must be considered. There are recommended techniques such as grooves and ribs which may be used on a printed circuit board to achieve desired creepage and clearances. Creepage and clearance distances will also change depending on factors such as pollution degree and insulation level. IEC/EN/DIN EN 77-- Insulation Characteristics* Description Symbol Option Units Installation classification per DIN VDE /.89, Table for rated mains voltage V rms for rated mains voltage V rms for rated mains voltage V rms for rated mains voltage V rms for rated mains voltage V rms Climatic Classification // Pollution Degree (DIN VDE /.89) Maximum Working Insulation Voltage V IORM V peak Input to Output Test Voltage, Method b ** V IORM x.87=v PR, % Production Test with t m = sec, Partial discharge < pc Input to Output Test Voltage, Method a ** V IORM x.=v PR, Type and Sample Test, t m = sec, Partial discharge < pc I IV I - III I III I III I III V PR 7 V peak V PR 7 V peak Highest Allowable Overvoltage (Transient Overvoltage t ini = sec) V IOTM V peak Safety-limiting values maximum values allowed in the event of a failure, also see Figure. Case Temperature Input Current Output Power T S I S, INPUT P S, OUTPUT Insulation Resistance at T S, V IO = V R IO >9 W Note: * Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in application. Surface mount classification is class A in accordance with CECCOO8. ** Refer to the optocoupler section of the Isolation and Control Components Designer s Catalog, under Product Safety Regulations section IEC/EN/ DIN EN 77--, for a detailed description of Method a and Method b partial discharge test profiles. These optocouplers are suitable for safe electrical isolation only within the safety limit data. Maintenance of the safety data shall be ensured by means of protective circuits. The surface mount classification is Class A in accordance with CECC 8. 7 C ma mw

6 Absolute Maximum Ratings Parameter Symbol Min. Max. Units Storage Temperature T S + C Ambient Operating Temperature T A + C Supply Voltages V DD Volts Output Voltage V O. V DD +. Volts Average Forward Input Current I F - ma Average Output Current I o - ma Lead Solder Temperature C for sec.,. mm below seating plane Solder Reflow Temperature Profile See Solder Reflow Temperature Profile Section Recommended Operating Conditions Parameter Symbol Min. Max. Units Ambient Operating Temperature T A + C Supply Voltages V DD.. V.. V Input Current (ON) I F 8 ma Supply Voltage Slew Rate [] SR. V/ms Electrical Specifications Over recommended temperature (T A = C to + C),.V V DD.V and. V V DD. V. All typical specifications are at T A =+ C, V DD = +.V. Parameter Symbol Part Number Min. Typ. Max. Units Test Conditions Input Forward Voltage V F...8 V I F = ma Input Reverse Breakdown Voltage Logic High Output Voltage Logic Low Output Voltage Input Threshold Current Logic Low Output Supply Current Logic Low Output Supply Current BV R. V I R = µa V OH V DD - VDD-. V I F = ma, I O = - ma, V DD =. V V DD - VDD-. V I F = ma, I O = - ma, V DD = V V OL..8 V I F = ma, I O = ma, V DD =. V..8 V I F = ma, I O = ma, V DD = V I TH ma I OL = µa I DDL ACPL-W7L.. ma I F = ma ACPL-K7L 8. ma I F = ma I DDH ACPL-W7L.8 ma I F = ma ACPL-K7L 7. ma I F = ma

7 Switching Specifications Over recommended temperature (T A = C to + C),.V V DD.V and. V V DD. V. All typical specifications are at T A =+ C, V DD = +.V. Parameter Symbol Min. Typ. Max. Units Test Conditions Propagation Delay Time t PHL ns I F = ma, C L = pf to Logic Low Output [] CMOS Signal Levels Propagation Delay Time t PLH 7 ns I F = ma, C L = pf to Logic High Output [] CMOS Signal Levels Pulse Width t PW.7 ns Pulse Width Distortion [] PWD ns I F = ma, C L = pf CMOS Signal Levels Propagation Delay Skew [] t PSK ns I F = ma, C L = pf CMOS Signal Levels Output Rise Time (% 9%) Output Fall Time (9% - %) t R. ns I F = ma, C L = pf CMOS Signal Levels t F. ns I F = ma, C L = pf CMOS Signal Levels Common Mode Transient Immunity CM H kv/µs V CM = V, T A = C, I F = ma at Logic High Output [] Common Mode Transient Immunity CM L kv/µs V CM = V, T A = C, I F = ma at Logic Low Output [] Package Characteristics All Typical at T A = C. Parameter Symbol Min. Typ. Max. Units Test Conditions Input-Output Insulation I I-O. µa % RH, t = s V I-O = kv DC, T A = C Input-Output Momentary Withstand Voltage V ISO ( option) V rms RH %, t = min., T A = C Input-Output Resistance R I-O W V I-O = V dc Input-Output Capacitance C I-O. pf f = MHz, T A = C Notes:. Slew rate of supply voltage ramping is recommended to ensure no glitch more than V to appear at the output pin.. t PHL propagation delay is measured from the % level on the rising edge of the input pulse to the % level on the falling edge of the V O signal. t PLH propagation delay is measured from the % level on the falling edge of the input pulse to the % level on the rising edge of the V O signal.. PWD is defined as t PHL - t PLH.. t PSK is equal to the magnitude of the worst case difference in t PHL and/or t PLH that will be seen between units at any given temperature within the recommended operating conditions.. CM H is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state.. CM L is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state. 7

8 I F - FORWARD CURRENT-mA I F T A = C V F V F - FORWARD VOLTAGE-V Figure. Typical input diode forward characteristic I th - INPUT THRESHOLD CURRENT-mA I OL =ua V.V. - - T A -TEMPERATURE- o 8 C Figure. Typical input threshold current vs. temperature IDDH -LOGIC HIGH OUTPUT SUPPLY CURRENT-mA 8 - V DD =V V DD =.V IDDL -LOGIC LOW OUTPUT SUPPLY CURRENT- ma V DD =V V DD =.V - T A -TEMPERATURE- o C T A -TEMPERATURE- o 8 C Figure. Typical logic high output supply current vs. temperature for dual channel (ACPL-K7L) 8 Figure. Typical logic low output supply current vs. temperature for dual channel (ACPL-K7L) tp PROPAGATION DELAY; PWD-Pulse Width h Distortion ns t PHL CH V DD =V T A = C t PLH CH PWD CH PWD CH tphl CH t PLH CH tp PROPAGATION DELAY; PWD-Pulse Width Distortion ns V DD =V T A = C I F PULSE INPUT CURRENT ma IF PULSE INPUT CURRENT ma t PHL CH t PLH CH PWD CH PWD CH t PHL CH t PLH CH Figure. Typical switching speed vs. pulse input current at V supply voltage Figure. Typical switching speed vs. pulse input current at.v supply voltage 8

9 V F FORWARD VOLTAGE-V T A -TEMPERATURE- o 8 C Figure 7. Typical V F vs. temperature. Application Information Bypassing and PC Board Layout The ACPL-W7L and ACPL-K7L optocouplers are extremely easy to use. ACPL-W7L and ACPL-K7L provide CMOS logic output due to the high-speed CMOS IC technology used. The external components required for proper operation are the input limiting resistor and the output bypass capacitor. Capacitor values should be between. µf and. µf. For each capacitor, the total lead length between both ends of the capacitor and the power-supply pins should not exceed mm. Propagation Delay, Pulse-Width Distortion and Propagation Delay Skew Propagation delay is a figure of merit which describes how quickly a logic signal propagates through a system. The propagation delay from low to high (t PLH ) is the amount of time required for an input signal to propagate to the output, causing the output to change from low to high. Similarly, the propagation delay from high to low (t PHL ) is the amount of time required for the input signal to propagate to the output, causing the output to change from high to low (see Figure 9). Pulse-width distortion (PWD) results when t PLH and t PHL differ in value. PWD is defined as the difference between t PLH and t PHL and often PWD is defined as the difference between t PLH and t PHL and often determines the maximum data rate capability of a transmission system. PWD can be expressed in percent by dividing the PWD (in ns) by the minimum pulse width (in ns) being transmitted. Typically, PWD on the order of -% of the minimum pulse width is tolerable; the exact figure depends on the particular application (RS, RS, T-, etc.). Propagation delay skew, t PSK, is an important parameter to consider in parallel data applications where synchronization of signals on parallel data lines is a concern. If the parallel data is being sent through a group of optocouplers, differences in propagation delays will cause the data to arrive at the outputs of the optocouplers at different times. If this difference in propagation delays is large enough, it will determine the maximum rate at which parallel data can be sent through the optocouplers. Propagation delay skew is defined as the difference between the minimum and maximum propagation delays, either t PLH or t PHL, for any given group of optocouplers which are operating under the same conditions (i.e., the same supply voltage, output load, and operating temperature). As illustrated in Figure, if the inputs of a group of optocouplers are switched either ON or OFF at the same 9

10 I F XXX YWW C V DD Vo I F GND GND XXX YWW 8 7 C V DD V O V O GND GND I F GND ACPL-W7L ACPL-K7L Figure 8. Recommended printed circuit board layout C=.µF to.µf V I % DATA V O. V, CMOS INPUTS CLOCK t PSK V I % DATA OUTPUTS t PSK V O. V, CMOS CLOCK t PSK Figure 9. Propagation delay skew waveform Figure. Parallel data transmission example. time, t PSK is the difference between the shortest propagation delay, either t PHL or t PHL, and the longest propagation delay, either t PHL or t PHL. As mentioned earlier, t PSK can determine the maximum parallel data transmission rate. Figure is the timing diagram of a typical parallel data application with both the clock and the data lines being sent through optocouplers. The figure shows data and clock signals at the inputs and outputs of the optocouplers. To obtain the maximum data transmission rate, both edges of the clock signal are being used to clock the data; if only one edge were used, the clock signal would need to be twice as fast. Propagation delay skew represents the uncertainty of where an edge might be after being sent through an optocoupler. Figure shows that there will be uncertainty in both the data and the clock lines. It is important that these two areas of uncertainty not overlap, otherwise the clock signal might arrive before all of the data outputs have settled, or some of the data outputs may start to change before the clock signal has arrived. From these considerations, the absolute minimum pulse width that can be sent through optocouplers in a parallel application is twice t PSK. A cautious design should use a slightly longer pulse width to ensure that any additional uncertainty in the rest of the circuit does not cause a problem. The t PSK specified optocouplers offer the advantages of guaranteed specifications for propagation delays, pulsewidth distortion and propagation delay skew over the recommended temperature, and power supply ranges.

11 Powering Sequence V DD needs to achieve a minimum level of.v before powering up the output connecting component. Input Limiting Resistor ACPL-W7L and ACPL-K7L are direct current driven (Figure 8), and thus eliminate the need for input power supply. To limit the amount of current flowing through the LED, it is recommended that a ohm resistor is connected in series with anode of LED (i.e. Pin for ACPL-W7L, Pin and P for ACPL-K7L) at V input signal. At.V input signal, it is recommended to connect ohm resistor in series with anode of LED. The recommended limiting resistors is based on the assumption that the driver output impedence is Ω (as shown in Figure ). Speed Improvement A peaking capacitor can be placed across the input current limit resistor (Figure ) to achieve enhanced speed performance. The value of the peaking cap is dependent to the rise and fall time of the input signal and supply voltages and LED input driving current (I f ). Figure shows significant improvement of propagation delay and pulse with distortion with added pf peak capacitor at driving current of ma and V power supply. t PLH tphl t PHL With peaking cap Without peaking cap V i + - GND R drv = Ω C peak R limit SHIELD.µF V DD V O GND t PLH PWD (i) V DD =V, C peak =pf, R limit =Ω Figure. Connection of peaking capacitor (C peak ) in parallel of the input limiting resistor (R llimit ) to improve speed performance t PLH PWD t PHL t PHL t PLH With peaking cap Without peaking cap (ii) V DD =.V, C peak =pf, R limit =Ω Figure. Improvement of t p and PWD with added pf peaking capacitor in parallel of input limiting resistor.

12 Common Mode Rejection for ACPL-W7L AND ACPL-K7L Figure shows the recommended driving circuit for the ACPL-W7L and ACPL-K7L for optimal common-mode rejection performance. Two LED-current setting resistors are used instead of one. This is to balance the common mode impedance at LED anode and cathode. Common-mode transients can capacitively couple from the LED anode (or cathode) to the output-side ground causing current to be shunted away from the LED (which can be bad if the LED is on) or conversely cause current to be injected into the LED (bad if the LED is meant to be off). Figure shows the parasitic capacitances which exists between LED anode/ cathode and output ground (C LA and C LC ). Also shown in Figure on the input side is an AC-equivalent circuit. Table indicates the directions of I LP and I LN flow depending on the direction of the common-mode transient. For transients occurring when the LED is on, common-mode rejection (CM L, since the output is in the low state) depends upon the amount of LED current drive (I F ). For conditions where I F is close to the switching threshold (I TH ), CM L also depends on the extent which I LP and I LN balance each other. In other words, any condition where commonmode transients cause a momentary decrease in I F (i.e. when dv CM /dt> and I FP > I FN, referring to Table ) will cause common-mode failure for transients which are fast enough. Likewise for common-mode transients which occur when the LED is off (i.e. CM H, since the output is high ), if an imbalance between I LP and I LN results in a transient I F equal to or greater than the switching threshold of the optocoupler, the transient signal may cause the output to spike below V (which constitutes a CM H failure). By using the recommended circuit in Figure, good CM R can be achieved. The resistors recommended in Figure include both the output impedence of the logic driver circuit and the external limiting resistor. The balanced I LED - setting resistors help equalize the common mode voltage change at anode and cathode to reduce the amount by which I LED is modulated from transient coupling through C LA and C LC. V DD /R total R total =Ω for V DD =.V = 8Ω for V DD =V V DD /R total.µf V O 7LS OR ANY TOTEM- POLE OUTPUT LOGIC GATE GND SHIELD GND Figure. Recommended drive circuit for ACPL-W7L and ACPL-K7L for high-cmr ½ R total I LP V DD ½ R total C LA.µF V O pf I LN SHIELD C LC GND Figure. AC equivalent of ACPL-W7L and ACPL-K7L

13 Table. Effects of Common Mode Pulse Direction on Transient I LED If dv CM /dt Is: then I LP Flows: and I LN Flows: If I LP < I LN, LED I F Current Is Momentarily: If I LP < I LN, LED I F Current Is Momentarily: positive (>) away from LED anode through C LA away from LED cathode through C LC increased decreased negative (<) toward LED anode through C LA toward LED cathode through C LC decreased increased CMR with Other Drive Circuits CMR performance with drive circuits other than that shown in Figure may be enhanced by following these guidelines:. Use of drive circuits where current is shunted from the LED in the LED off state (as shown in Figures and ). This is beneficial for good CM H.. Use of typical I FH = ma per datasheet recommendation. Using any one of the drive circuits in Figures -7 with I F = ma will result in a typical CMR of kv/μs for ACPL- W7L AND ACPL-K7L, as long as the PC board layout practices are followed. Figure shows a circuit which can be used with any totem-pole-output TTL/LSTTL/HCMOS logic gate. The buffer PNP transistor allows the circuit to be used with logic devices which have low current-sinking capability. It also helps maintain the driving-gate powersupply current at a constant level to minimize ground shifting for other devices connected to the input-supply ground. V DD 7HC (OR ANY OPEN-COLLECTOR /OPEN-DRAIN LOGIC GATE) Figure. TTL open-collector/open drain gate drive circuit for ACPL-W7L families. V DD Ω ACPL-W7L ACPL-W7L LED 7L (ANY TTL/CMOS GATE) V DD N9 (ANY PNP) Ω ACPL-W7L LED 7HC (OR ANY TOTEM-POLE OUTPUT LOGIC GATE) Ω Figure 7. CMOS gate drive circuit for ACPL-W7L families. LED Figure. TTL interface circuit for the ACPl-W7L families. When using an open-collector TTL or open-drain CMOS logic gate, the circuit in Figure may be used. When using a CMOS gate to drive the optocoupler, the circuit shown in Figure 7, where the resistor is recommended to connect to the anode of the LED, may be used.

14 V CM R limit A B I F.µF SHIELD Pulse Gen. + - V CM V O V O V V DD GND SWITCH AT A: I = ma F SWITCH AT B: I = ma F V CM (PEAK) V O (min.) V O(max.) CM H CM L Figure 8. Test circuit for common mode transient immunity and typical waveforms. For product information and a complete list of distributors, please go to our web site: Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright -9 Avago Technologies. All rights reserved. AV-7EN - February, 9

15 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Broadcom Limited: ACPL-K7L-E ACPL-K7L-E ACPL-K7L-E ACPL-W7L-E ACPL-W7L-E ACPL-W7L-E ACPL-K7L-E ACPL-K7L-E ACPL-W7L-E ACPL-W7L-E

ACPL-071L and ACPL-074L Single-channel and Dual-channel High Speed 15 MBd CMOS optocoupler with Glitch-Free Power-Up Feature. Features.

ACPL-071L and ACPL-074L Single-channel and Dual-channel High Speed 15 MBd CMOS optocoupler with Glitch-Free Power-Up Feature. Features. ACPL-7L and ACPL-7L Single-channel and Dual-channel High Speed MBd CMOS optocoupler with Glitch-Free Power-Up Feature Data Sheet Lead (Pb) Free RoHS fully compliant RoHS fully compliant options available;