Data Sheet. ACPL-P349 and ACPL-W Amp Output Current SiC/GaN MOSFET and IGBT Gate Drive Optocoupler in Stretched SO6. Features.

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1 ACPL-P349 and ACPL-W349.5 Amp Output Current SiC/GaN MOSFET and IGBT Gate Drive Optocoupler in Stretched SO6 Data Sheet Description The ACPL-P349/W349 contains an AlGaAs LED, which is optically coupled to an integrated circuit with a power output stage. This optocoupler is ideally suited for driving SiC/GaN (Silicon Carbide / Gallium Nitride) MOSFETs and IGBTs used in power conversion applications. The high operating voltage range of the output stage provides the drive voltages required by gate controlled devices. The voltage and high peak output current supplied by this optocoupler make it ideally suited for direct driving SiC/GaN MOSFET and IGBT with ratings up to V/A. Functional Diagram ANODE Note: Design Note: A µf bypass capacitor must be connected between pins V CC and V EE. Truth Table LED NC CATHODE 3 VCC VEE POSITIVE GOING (i.e., TURN-ON) VCC VEE NEGATIVE GOING (i.e., TURN-OFF) OFF - 3 V 3 V LOW ON. V. V LOW ON. 3.9 V.9. V TRANSITION ON 3.9 3V 3.9 V HIGH V CC V OUT V EE VO Features.5 A maximum peak output current Wide operating V CC range: 5 to 3 V ns maximum propagation delay 5 ns maximum propagation delay difference Rail-to-rail output voltage 5 kv/µs minimum Common Mode Rejection (CMR) at V CM = 5 V LED current input with hysteresis I CC = 4. ma maximum supply current Under Voltage Lock-Out protection (UVLO) with hysteresis Industrial temperature range: -4 C to 5 C Safety Approval - UL Recognized 375/5 V RMS for min. - CSA - IEC/EN/DIN EN V IORM = 89/4 V PEAK Applications SiC/GaN MOSFET and IGBT gate drive Motor drives Industrial Inverters Renewable energy inverters Switching power supplies CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD. The components featured in this datasheet are not to be used in military or aerospace applications or environments

2 Ordering Information ACPL-P349 is UL Recognized with 375 V RMS for minute per UL577. ACPL-W347 is UL Recognized with 5 V RMS for minute per UL577. Part numb ACPL-P349 ACPL-W349 Option RoHS Compliant Package Surface Mount Tape & Reel IEC/EN/DIN EN Quantity -E Stretched X per tube -5E SO-6 X X per reel -6E X X per tube -56E X X X per reel To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. Example : ACPL-P349-56E to order product of Stretched SO-6 Surface Mount package in Tape and Reel packaging with IEC/EN/ DIN EN Safety Approval in RoHS compliant. Example : ACPL-W349-E to order product of Stretched SO-6 Surface Mount package in Tube packaging and RoHS compliant. Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.

3 Package Outline Drawings ACPL-P349 Stretched SO-6 Package (7 mm clearance).38 ±.7 (.5 ±.5).7 (.5) BSG ( ) Land Pattern Recommendation.76 (.3).7 (.5).45 (.8) (.3) 6.8 (.68) 7.59 ±.7 (.63 ±.5).7 (.4) 3.8 ±.7 (.5 ±.5).6 (.85) 7 7. ±. (.8 ±.4) 7.54 ±.5 (. ±.) ±.5 (.4 ±.) 5 NOM. 9.7 ±.5 (.38 ±.) Floating Lead Protusions max..5 (.) Dimensions in Millimeters (Inches) Lead Coplanarity =. mm (.4 Inches) ACPL-W349 Stretched SO-6 Package (8 mm clearance).38 ±.7 (.5 ±.5).7 (.5) BSG ( ) Land Pattern Recommendation.76 (.3) (.5) ( ) 7.6 (.3).65 (.5).95 (.75).45 (.8) ±.7 (.63 ±.5) 3.8 ±.7 (.5 ±.5) 7. ±. (.8 ±.4).75 ±.5 (.95 ±.) 7.54 ±.5 (. ±.) 7 35 NOM..5 ±.5 (.453 ±.) Floating Lead Protusions max..5 (.) Dimensions in Millimeters (Inches) Lead Coplanarity =. mm (.4 Inches) 3

4 Recommended Pb-Free IR Profile Recommended reflow condition as per JEDEC Standard, J-STD- (latest revision). Non- Halide Flux should be used. Regulatory Information The ACPL-P349/W349 is approved by the following organizations: UL Recognized under UL 577, component recognition program up to V ISO = 375 V RMS (ACPL-P349) and V ISO = 5 V RMS (ACPL-W349). CSA CSA Component Acceptance Notice #5, File CA 8834 IEC/EN/DIN EN (Option 6 Only) Maximum Working Insulation Voltage V IORM = 89V peak (ACPL-P349) and V IORM = 4 V peak (ACPL- W349) Table. IEC/EN/DIN EN Insulation Characteristics* (Option 6) Description Installation classification per DIN VDE /39, Table for rated mains voltage 5 Vrms for rated mains voltage 3 Vrms for rated mains voltage 45 Vrms for rated mains voltage 6 Vrms for rated mains voltage Vrms Symbol ACPL-P349 Option 6 ACPL-W349 Option 6 Climatic Classification 4/5/ 4/5/ I IV I IV I III I III Pollution Degree (DIN VDE /39) I IV I IV I IV I IV I III Unit Maximum Working Insulation Voltage V IORM 89 4 V PEAK Input to Output Test Voltage, Method b* V IORM x.875=v PR, % Production Test with t m = sec, Partial discharge < 5 pc Input to Output Test Voltage, Method a* V IORM x.6=v PR, Type and Sample Test, t m = sec, Partial discharge < 5 pc Highest Allowable Overvoltage* (Transient Overvoltage t ini = 6 sec) Safety-limiting values maximum values allowed in the event of a failure Case Temperature Input Current Output Power V PR V PEAK V PR V PEAK V IOTM 6 8 V PEAK T S I S, INPUT P S, OUTPUT Insulation Resistance at T S, V IO = 5 V RS > 9 > 9 Ω * Refer to IEC/EN/DIN EN Optoisolator Safety Standard section of the Avago Regulatory Guide to Isolation Circuits, AV-4EN for a detailed description of Method a and Method b partial discharge test profiles. Note: These optocouplers are suitable for safe electrical isolation only within the safety limit data. Maintenance of the safety data shall be ensured by means of protective circuits. Surface mount classification is Class A in accordance with CECC C ma mw 4

5 Table. Insulation and Safety Related Specifications Parameter Symbol ACPL-P349 ACPL-W349 Units Conditions Minimum External Air Gap (Clearance) Minimum External Tracking (Creepage) Minimum Internal Plastic Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) L() mm Measured from input terminals to output terminals, shortest distance through air. L() mm Measured from input terminals to output terminals, shortest distance path along body..8.8 mm Through insulation distance conductor to conductor, usually the straight line distance thickness between the emitter and detector. CTI > 75 > 75 V DIN IEC /VDE 33 Part Isolation Group IIIa IIIa Material Group (DIN VDE, /89, Table ) Notes:. All Avago data sheets report the creepage and clearance inherent to the optocoupler component itself. These dimensions are needed as a starting point for the equipment designer when determining the circuit insulation requirements. However, once mounted on a printed circuit board, minimum creepage and clearance requirements must be met as specified for individual equipment standards. For creepage, the shortest distance path along the surface of a printed circuit board between the solder fillets of the input and output leads must be considered (the recommended Land Pattern does not necessarily meet the minimum creepage of the device). There are recommended techniques such as grooves and ribs which may be used on a printed circuit board to achieve desired creepage and clearances. Creepage and clearance distances will also change depending on factors such as pollution degree and insulation level. Table 3. Absolute Maximum Ratings Parameter Symbol Min. Max. Units Note Storage Temperature T S C Operating Temperature T A -4 5 C Output IC Junction Temperature T J 5 C Average Input Current I F(AVG) 5 ma Peak Transient Input Current (< µs pulse width, 3pps) I F(TRAN) A Reverse Input Voltage V R 5 V High Peak Output Current I OH(PEAK).5 A Low Peak Output Current I OL(PEAK).5 A Total Output Supply Voltage (V CC - V EE ) 35 V Output Voltage V O(PEAK) -.5 V CC V Output IC Power Dissipation P O 5 mw 3 Total Power Dissipation P T 55 mw 4 Table 4. Recommended Operating Conditions Parameter Symbol Min Max. Units Note Operating Temperature T A C Output Supply Voltage (V CC - V EE ) 5 3 V Input Current (ON) I F(ON) 7 ma Input Voltage (OFF) V F(OFF) V 5

6 Table 5. Electrical Specifications (DC) All typical values are at T A = 5 C, V CC - V EE = 5 V, V EE = Ground. All minimum and maximum specifications are at recommended operating conditions (T A = -4 to 5 C, I F(ON) = 7 to ma, V F(OFF) = -3.6 to.8 V, V EE = Ground, V CC = 5 to 3 V), unless otherwise noted. Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note High Level Peak Output Current I OH A V CC V O = 5 V, 3 5 Low Level Peak Output Current I OL. 4.4 A V O - V EE = 5 V 5, 6 5 High Output Transistor R DS(ON) R DS,OH Ω I OH = -. A 7 6 Low Output Transistor R DS(ON) R DS,OL.3.7. Ω I OL =. A 8 6 High Level Output Voltage V OH Vcc-.4 Vcc. V I O = - ma, I F = 9 ma, 3 7, 8 High Level Output Voltage V OH Vcc V I O = ma, I F = 9 ma 3 Low Level Output Voltage V OL..5 V I O = ma 4, 6 High Level Supply Current I CCH.6 4. ma I F = 9 ma 9, Low Level Supply Current I CCL.6 4. ma V F = V Threshold Input Current Low to High Threshold Input Voltage High to Low I FLH ma V O > 5 V, V FHL.8 V Input Forward Voltage V F V I F = 9 ma 8 Temperature Coefficient of Input Forward Voltage Input Reverse Breakdown Voltage ΔV F /ΔT A -.7 mv/ C BV R 5 V I R = ma Input Capacitance C IN 7 pf f = MHz, V F = V UVLO Threshold V UVLO V V O > 5 V, IF = 9 ma V UVLO-..9 UVLO Hysteresis UVLO HYS.5. V 6

7 Table 6. Switching Specifications (AC) All typical values are at T A = 5 C, V CC - V EE = 5 V, V EE = Ground. All minimum and maximum specifications are at recommended operating conditions (T A = -4 to 5 C, I F(ON) = 7 to ma, V F(OFF) = -3.6 to.8 V, V EE = Ground, V CC = 5 to 3 V), unless otherwise noted. Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note Propagation Delay Time to High Output Level Propagation Delay Time to Low Output Level t PLH 3 55 ns Rg = 7.5 Ω, Cg = nf, t f = khz, PHL 3 55 ns Duty Cycle = 5%, V CC = 5 V 3, 4, 5, 6, 7 Pulse Width Distortion PWD 4 ns 9 Propagation Delay Difference Between Any Two Parts PDD (t PHL - t PLH ) -5 5 ns, 3 Propagation Delay Skew t PSK 5 ns Rise Time t R 8 8 ns Cg = nf, Fall Time t f = khz, F 8 8 ns Duty Cycle = 5%, V CC = 5V Output High Level Common Mode Transient Immunity Output Low Level Common Mode Transient Immunity CM H 5 7 kv/µs T A = 5 C, I F = 9 ma, V CC = 3 V, V CM = 5 V with split resistors CM L 5 7 kv/µs T A = 5 C, V F = V, V CC = 3 V, V CM = 5 V with split resistors 9, 3, 4 Table 7. Package Characteristics All typical values are at T A = 5 C. All minimum/maximum specifications are at recommended operating conditions, unless otherwise noted. Parameter Symbol Device Min. Typ. Max. Units Test Conditions Fig. Note Input-Output Momentary Withstand Voltage* V ISO ACPL-P V RMS RH < 5%, t = min., T A = 5 C ACPL-W349 5 V RMS RH < 5%, t = min., T A = 5 C Input-Output Resistance R I-O > 4 Ω V I-O = 5 V DC 7 Input-Output Capacitance C I-O.6 pf f = MHz LED-to-Ambient Thermal Resistance R 35 C/W 8 LED-to-Detector Thermal Resistance R 7 Detector-to-LED Thermal Resistance R 39 Detector-to-Ambient Thermal Resistance R 47 * The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. For the continuous voltage rating, refer to your equipment level safety specification or Avago Technologies Application Note 74 entitled Optocoupler Input-Output Endurance Voltage. 5, 7 6, 7 7

8 Notes:. Derate linearly above 85 C free-air temperature at a rate of.3 ma/ C.. Maximum pulse width = µs. This value is intended to allow for component tolerances for designs with IO peak minimum =. A. See applications section for additional details on limiting I OH peak. 3. Derate linearly above 85 C free-air temperature at a rate of.5 mw/ C. 4. Derate linearly above 85 C free-air temperature at a rate of 3.75 mw/ C. The maximum LED junction temperature should not exceed 5 C. 5. Maximum pulse width = µs. 6. Output is sourced at -. A/. A with a maximum pulse width = µs. 7. In this test V OH is measured with a dc load current. When driving capacitive loads, V OH will approach V CC as I OH approaches zero amps. 8. Maximum pulse width = ms. 9. Pulse Width Distortion (PWD) is defined as t PHL -t PLH for any given device.. Propagation Delay Difference (PDD) is the difference between t PHL and t PLH between any two units under the same test condition.. Propagation Delay Skew (t PSK ) is the difference in t PHL or t PLH between any two units under the same test condition.. Pin needs to be connected to LED common. Split resistor network in the ratio.5: with 3 Ω at the anode and 54 Ω at the cathode. 3. Common mode transient immunity in the high state is the maximum tolerable dv CM /dt of the common mode pulse, V CM, to assure that the output will remain in the high state (i.e., V O > 5. V). 4. Common mode transient immunity in a low state is the maximum tolerable dv CM /dt of the common mode pulse, V CM, to assure that the output will remain in a low state (i.e., V O <. V). 5. In accordance with UL577, each optocoupler is proof tested by applying an insulation test voltage 45 V RMS for second (leakage detection current limit, I I-O 5 µa). 6. In accordance with UL577, each optocoupler is proof tested by applying an insulation test voltage 6 V RMS for second (leakage detection current limit I I-O 5 µa). 7. Device considered a two-terminal device: pins,, and 3 shorted together and pins 4, 5 and 6 shorted together. 8. The device was mounted on a high conductivity test board as per JEDEC

9 (VOH-VCC) - HIGH OUTPUT VOLTAGE DROP - V I F = 9 ma I OUT = - ma V CC = 3 V V EE = V Figure. V OH vs. temperature IOH - OUTPUT HIGH CURRENT - A I F = 9 ma V OUT = V CC -5 V V CC = 5 V V EE = V Figure. I OH vs. temperature IOH - OUTPUT HIGH CURRENT - A I F = 9 ma V CC = 5 V V EE = V T A = 5 C (V OH -V CC ) - HIGH OUTPUT VOLTAGE DROP - V VOL - OUTPUT LOW VOLTAGE - V V F (OFF) = V I OUT = ma V CC = 3 V V EE = V Figure 3. I OH vs. V OH Figure 4. V OL vs. Temperature IOL - OUTPUT LOW CURRENT - A V F (OFF) = V V OUT = 5 V V CC = 5 V.5 V EE = V Figure 5. I OL vs. temperature IOL - OUTPUT LOW CURRENT - A V F (OFF) = V V CC = 5 V.5 V EE = V T A = 5 C V OL - OUTPUT LOW VOLTAGE - V Figure 6. I OL vs. VOL 9

10 RDS,OH - HIGH OUTPUT TRANSISTOR RDS(ON) - Ω Figure 7. R DS,OH vs. temperature I F = 9 ma I OUT = - A V CC = 5 V V EE = V RDS,OL - LOW OUTPUT TRANSISTOR RDS(ON) - Ω V F (OFF) = V.4 I OUT = A. V CC = 5 V V EE = V Figure 8. R DS,OL vs. temperature ICC - SUPPLY CURRENT - ma I F = 9 ma for I CCH V F = V for I CCL I CCL V CC = 5 V I CCH. V EE = V Figure 9. I CC vs. temperature ICC - SUPPLY CURRENT - ma I F = 9 ma for I CCH.5 V F = V for I CCL I CCL T A = 5 C V EE = V I CCH V CC - SUPPLY VOLTAGE - V Figure. I CC vs. V CC VO - OUTPUT VOLTAGE - V T A = 5 C V CC = 5 V V EE = V I FLH OFF I FLH ON I FLH - LOW TO HIGH CURRENT THRESHOLD - ma Figure. I FLH hysteresis IFLH - LOW TO HIGH CURRENT THRESHOLD - ma V CC = 5 V V EE = V I FLH OFF I FLH ON Figure. I FLH vs. temperature

11 TP - PROPAGATION DELAY - ns I F = 9 ma T A = 5 C R g = 7.5 Ω, Cg = nf DUTY CYCLE = 5% f = khz T PLH T PHL TP - PROPAGATION DELAY - ns V CC = 5 V, V EE = V T A = 5 C R g = 7.5 Ω, Cg = nf DUTY CYCLE = 5% f = khz T PLH T PHL V CC - SUPPLY VOLTAGE - V Figure 3. Propagation delay vs. V CC I F - FORWARD LED CURRENT - ma Figure 4. Propagation delay vs. I F TP - PROPAGATION DELAY - ns I F = 9 ma V CC = 5 V, V EE = V R g = 7.5 Ω, Cg = nf T PLH DUTY CYCLE = 5% f = khz T PHL Rg - SERIES LOAD RESISTANCE - Ω TP - PROPAGATION DELAY - ns I F = 9 ma, T A = 5 C V CC = 5 V, V EE = V Cg = nf DUTY CYCLE = 5% f = khz T PLH T PHL Figure 5. Propagation delay vs. temperature Figure 6. Propagation delay vs. Rg TP - PROPAGATION DELAY - ns I F = 9 ma, T A = 5 C V CC = 5 V, V EE = V Rg = 7.5 Ω DUTY CYCLE = 5% f = khz T PLH T PHL IF - FORWARD CURRENT - ma Cg - SERIES LOAD CAPACITANCE - nf Figure 7. Propagation delay vs. Cg V F - FORWARD VOLTAGE - V Figure 8. Input Current vs. forward voltage

12 5 V + _ 3 Ω 6 5 µf V O + _ V CC = 3 V V CM V t δv V CM δt = t 54 Ω 3 4 V O V OH SWITCH AT A: I F = 9 ma + _ V CM = 5V V O SWITCH AT B: I F = ma V OL Figure 9. CMR test circuit with split resistors network and waveforms Application Information Product Overview Description The ACPL-P349/W349 is an optically isolated power output stage capable of driving SiC/GaN MOSFET or IGBT. Based on BCDMOS technology, this gate drive optocoupler delivers higher peak output current, better rail-to-rail output voltage performance and two times faster speed than the previous generation products. The high peak output current and short propagation delay are needed for fast SiC/GaN MOSFET switching to reduce dead time and improve system overall efficiency. Rail-torail output voltage ensures that the SiC/GaN MOSFET or IGBT s gate voltage is driven to the optimum intended level with no power loss. This helps the designer lower the system power which is suitable for bootstrap power supply operation. It has very high CMR(common mode rejection) rating which allows the microcontroller and the SiC/GaN MOS- FET or IGBT to operate at very large common mode noise found in industrial motor drives and other power switching applications. The input is driven by direct LED current and has a hysteresis that prevents output oscillation if insufficient LED driving current is applied. This will eliminates the need of additional Schmitt trigger circuit at the input LED. The stretched SO6 package which is up to 5% smaller than conventional DIP package facilitates smaller more compact design. These stretched packages are compliant to many industrial safety standards such as IEC/EN/DIN EN , UL 577 and CSA. Recommended Application Circuit The recommended application circuit shown in Figure illustrates a typical gate drive implementation using the ACPL-P349/W349. The supply bypass capacitors ( µf) provide the large transient currents necessary during a switching transition. Because of the transient nature of the charging currents, a low current (4. ma) power supply will be enough to power the device. The split resistors (in the ratio of.5:) across the LED will provide a high CMR response by providing a balanced resistance network across the LED. The gate resistor R G serves to limit gate charge current and controls the MOSFET switching times. In PC board design, care should be taken to avoid routing the SiC/GaN MOSFET drain or source traces close to the ACPL-P349/W349 input as this can result in unwanted coupling of transient signals into ACPL-P349/W349 and degrade performance. + _ 3 Ω ANODE NC V CC 6 V OUT 5 µf RG V CC =V + _ Q SiC MOSFET + HVDC 54 Ω CATHODE 3 V EE 4 + _ V EE =5V Q - HVDC Figure. Recommended application circuit with split resistors LED drive.

13 Selecting the Gate Resistor (RG) Step : Calculate R G minimum from the I OL peak specification. The SiC/GaN MOSFET and R G in Figure can be analyzed as a simple RC circuit with a voltage supplied by ACPL-P349/W349. V CC - V R EE G I OLPEAK - R DS,OH(MIN) - (-5)V = -.5Ω.5A = 9.5Ω or V CC - V R EE G I OLPEAK - R DS,OL(MIN) - (-5)V = -.3Ω.5A = 9.7Ω The external gate resistor, R G and internal minimum turn-on resistance, R DSON will ensure the output current will not exceed the device absolute maximum rating of.5 A. In this case, we will use the worst case R G 9.7Ω. Step : Check the ACPL-P349/W349 power dissipation and increase R G if necessary. The ACPL-P349/W349 total power dissipation (P T ) is equal to the sum of the emitter power (P E ) and the output power (P O ). P T P E P O = P E + P O = I F V F Duty Cycle = P O(BIAS) + P O(SWITCHING) = I CC (V CC -V EE ) + P HS + P LS P HS = (V CC *Q G *f) * R DS,OH(MAX) / (R DS,OH(MAX) +R G ) / P LS = (V CC *Q G *f) * R DS,OL(MAX) / (R DS,OL(MAX) +R G ) / Using I F (worst case) = ma, Rg = 9.7 Ω, Max Duty Cycle = 8%, Q G = nc(v 3A SiC/GaN MOSFET), f = khz and T A max = 85 C: P E = ma.95v.8 = 7mW P HS = (5V nc khz) 3.5Ω/(3.5Ω+9.7Ω)/ = 66.3mW P LS = (5V nc khz).ω/(.ω+9.7ω)/ = 4.7mW P O = 4.mA 5V mW + 4.7mW = 4mW < 5 mw (P 85 C) The value of 4. ma for I CC in the previous equation is the maximum I CC over the entire operating temperature range. Since P O is less than P O(MAX), Rg = 9.7 Ω is alright for the power dissipation. LED Drive Circuit Considerations for High CMR Performance Figure shows the recommended drive circuit for the ACPL-P349/W349 that gives optimum common-mode rejection. The two current setting resistors balance the common mode impedances at the LED s anode and cathode. The balanced I LED -setting resistors help equalize the common mode voltage change at the anode and cathode. The shunt drive input circuit will also help to achieve high CML performance by shunting the LED in the off state. +5 V V DD = 5. V: R = 3 Ω ± % R = 54 Ω ± % R /R.5 R ANODE 6 V CC µc 5 V OUT R 3 CATHODE 4 V EE Figure. Recommended high-cmr drive circuit for the ACPL-P349/W349. 3

14 Dead Time and Propagation Delay Specifications The ACPL-P349/W349 includes a Propagation Delay Difference (PDD) specification intended to help designers minimize dead time in their power inverter designs. Dead time is the time period during which both the high and low side power transistors (Q and Q in Figure ) are off. Any overlap in Q and Q conduction will result in large currents flowing through the power devices between the high and low voltage motor rails. To minimize dead time in a given design, the turn on of LED should be delayed (relative to the turn off of LED) so that under worst-case conditions, transistor Q has just turned off when transistor Q turns on, as shown in Figure. The amount of delay necessary to achieve this condition is equal to the maximum value of the propagation delay difference specification, PDD MAX, which is specified to be ns over the operating temperature range of 4 C to 5 C. Delaying the LED signal by the maximum propagation delay difference ensures that the minimum dead time is zero, but it does not tell a designer what the maximum dead time will be. The maximum dead time is equivalent to the difference between the maximum and minimum propagation delay difference specifications as shown in Figure 3. The maximum dead time for the ACPL-P349/W349 is ns (= 5 ns - (-5 ns)) over an operating temperature range of -4 C to 5 C. Note that the propagation delays used to calculate PDD and dead time are taken at equal temperatures and test conditions since the optocouplers under consideration are typically mounted in close proximity to each other and are switching identical MOSFETs. I LED I LED V OUT Q ON Q OFF V OUT Q ON Q OFF Q ON Q ON V OUT Q OFF V OUT Q OFF I LED I LED t PHL MAX t PHL MIN tplh MIN PDD* MAX = (t PHL - t PLH ) MAX = t PHL MAX - t PLH MIN *PDD = PROPAGATION DELAY DIFFERENCE NOTE: FOR PDD CALCULATIONS THE PROPAGATION DELAYS ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS. t PHL MAX (t PHL- t PLH ) MAX PDD* MAX t PLH MIN t PLH MAX MAXIMUM DEAD TIME (DUE TO OPTOCOUPLER) = (t PHL MAX - t PHL MIN ) + (t PLH MAX - t PLH MIN ) = (t PHL MAX - t PLH MIN ) (t PHL MIN - t PLH MAX ) = PDD* MAX PDD* MIN *PDD = PROPAGATION DELAY DIFFERENCE NOTE: FOR DEAD TIME AND PDD CALCULATIONS ALL PROPAGATION DELAYS ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS. Figure. Minimum LED skew for zero dead time. Figure 3. Waveforms for dead time. 4

15 LED Current Input with Hysteresis The detector has optical receiver input stage with built in Schmitt trigger to provide logic compatible waveforms, eliminating the need for additional wave shaping. The hysteresis (Figure ) provides differential mode noise immunity and minimizes the potential for output signal chatter. Thermal Model for ACPL-P347/W347 Stretched SO6 Package Optocoupler Definitions: R : Junction to Ambient Thermal Resistance of LED due to heating of LED R : Junction to Ambient Thermal Resistance of LED due to heating of Detector (Output IC) R : Junction to Ambient Thermal Resistance of Detector (Output IC) due to heating of LED. R : Junction to Ambient Thermal Resistance of Detector (Output IC) due to heating of Detector (Output IC). P : Power dissipation of LED (W). P : Power dissipation of Detector / Output IC (W). T : Junction temperature of LED ( C). T : Junction temperature of Detector ( C). T A : Ambient temperature. Ambient Temperature: Junction to Ambient Thermal Resistances were measured approximately.5 cm above optocoupler at ~3 C in still air Thermal Resistance C/W R 35 R 7 R 39 R 47 This thermal model assumes that an 6-pin single-channel plastic package optocoupler is soldered into a 7.6 cm x 7.6 cm printed circuit board (PCB) per JEDEC standards. The temperature at the LED and Detector junctions of the optocoupler can be calculated using the equations below. T = (R * P + R * P ) + T A -- () T = (R * P + R * P ) + T A -- () Using the given thermal resistances and thermal model formula in this datasheet, we can calculate the junction temperature for both LED and the output detector. Both junction temperatures should be within the absolute maxi mum rating. For example, given P = 7 mw, P = 4 mw, T A = 85 C: LED junction temperature, T = (R * P + R * P ) + T A = (35 * *.4) + 85 = 93. C Output IC junction temperature, T = (R x P + R x P ) + T A = (39 * *.4) + 85 = 95.7 C T and T should be limited to 5 C based on the board layout and part placement. 5

16 Related Application Notes AV-4EN AN-5336 Gate Drive Optocoupler Basic Design for IGBT / MOSFET AV-3698EN AN-43 Common-Mode Noise: Sources and Solutions AV-3EN Reliability Data Plastics Optocouplers Product ESD and Moisture Sensitivity DISCLAIMER: Avago s products and software are not specifically designed, manufactured or authorized for sale as parts, components or assemblies for the planning, construction, maintenance or direct operation of a nuclear facility or for use in medical devices or applications. Customer is solely responsible, and waives all rights to make claims against Avago or its suppliers, for all loss, damage, expense or liability in connection with such use. For product information and a complete list of distributors, please go to our web site: Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright 5-5 Avago Technologies. All rights reserved. AV-4747EN - January 8, 5

17 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Avago Technologies: ACPL-P349-5E ACPL-P349-E ACPL-W349-56E ACPL-W349-E ACPL-W349-6E ACPL-W349-5E ACPL-P349-6E ACPL-P349-56E