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HCPL-, HCPL-, HCPL-,HCPL-, HCPL-, HCPL-, HCPL-, HCPL-, HCNW, HCNW Very High CMR, Wide Logic Gate Optocouplers Data Sheet Description The HCPL-XX, HCPL-XX, and HCNWXX are optically-coupled logic gates.

2 HCPL-, HCPL-, HCPL-,HCPL-, HCPL-, HCPL-, HCPL-, HCPL-, HCNW, HCNW Very High CMR, Wide Logic Gate Optocouplers Data Sheet Description The HCPL-XX, HCPL-XX, and HCNWXX are optically-coupled logic gates. The HCPL-XX, and HCPL-XX contain a GaAsP LED while the HCNWXX contains an AlGaAs LED. The detectors have totem pole output stages and optical receiver input stages with built-in Schmitt triggers to provide logic-compatible waveforms, eliminating the need for additional waveshaping. A superior internal shield on the HCPL-/, HCPL-, HCPL- and HCNW guarantees common mode transient immunity of kv/µs at a common mode voltage of volts. Functional Diagram NC ANODE CATHODE HCPL-/ HCPL-/ HCNW/ V O NC NC ANODE CATHODE HCPL-/ NC V O Features kv/µs minimum Common Mode Rejection (CMR) at V CM = V (HCPL-///, HCNW) Wide operating range:. to Volts ns propagation delay guaranteed over the full temperature range Mbd typical signal rate Low input current (. ma to. ma) Hysteresis Totem pole output (no pullup resistor required) Available in -Pin DIP, SOIC-, widebody packages Guaranteed performance from - C to C Safety approval UL recognized - V rms for minute ( V rms for minute for HCNWXX) per UL CSA approved IEC/EN/DIN EN -- approved with V IORM = V peak (HCPL-/ Option only) and V IORM = V peak (HCNWXX only) MIL-PRF- hermetic version available (HCPL-XX/XX) NC ANODE CATHODE CATHODE ANODE SHIELD HCPL-/ SHIELD V O V O NC SHIELD TRUTH TABLE (POSITIVE LOGIC) LED V O ON HIGH OFF LOW Applications Isolation of high speed logic systems Computer-peripheral interfaces Microprocessor system interfaces Ground loop elimination Pulse transformer replacement High speed line receiver Power control systems A. µf bypass capacitor must be connected between pins and. CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD.

3 The electrical and switching characteristics of the HCPL-XX, HCPL-XX and HCNWXX are guaranteed from - C to + C and a from. volts to volts. Low I F and wide range allow compatibility with TTL, LSTTL, and CMOS logic and result in lower power consumption compared to other high speed couplers. Logic signals are transmitted with a typical propagation delay of ns. Selection Guide Small- Widebody Minimum CMR Input -Pin DIP ( Mil) Outline SO- ( Mil) Hermetic On- Single Dual Single Single Single and dv/dt Current Channel Channel Channel Channel Dual Channel (V/µs) V CM (V) (ma) Package Package Package Package Packages,. HCPL- [,] HCPL- HCNW HCPL- HCPL-. HCPL-,. HCPL-9 [,], [] []. HCPL- HCPL- HCNW HCPL-. HCPL-,. HCPL-XX [] HCPL-XX [] Notes:. HCPL-/9 devices include output enable/disable function.. Technical data for the HCPL-/9, HCPL-XX and HCPL-XX are on separate Avago publications.. Minimum CMR of kv/µs with V CM = V can be achieved with input current, I F, of ma. Schematic I CC I CC I F + V F I O V O + V F I F SHIELD HCPL-/// HCPL-/ HCNW/ I O V O V F + I F SHIELD SHIELD I O V O HCPL-/

4 Ordering Information HCPL-, HCPL-, HCPL-, HCPL-, HCPL-, HCPL-, HCPL-, HCPL- are UL Recognized with Vrms for minute per UL. HCNW and HCNW are UL Recognized with Vrms for minute per UL. All devices listed above are approved under CSA Component Acceptance Notice #, File CA. Option Part RoHS non RoHS Surface Gull Tape UL Vrms/ IEC/EN/DIN Number Compliant Compliant Package Mount Wing & Reel Minute rating EN -- Quantity HCPL- -E no option mil DIP- per tube HCPL- -E - X X per tube HCPL- -E - X X X per reel HCPL- -E - X per tube HCPL- -E - X X X per tube HCPL- -E - X X X X per reel -E no option SO- per tube HCPL- -E - X X X per reel HCPL- -E - X per tube -E - X X X X per reel HCNW -E no option mil per tube HCNW -E - Widebody X X per tube -E - DIP- X X X per reel To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. Example : HCPL--E to order product of mil DIP Gull Wing Surface Mount package in Tape and Reel packaging with IEC/EN/DIN EN -- Safety Approval and RoHS compliant. Example : HCPL- to order product of mil DIP package in Tube packaging and non RoHS compliant. Option datasheets are available. Contact your Avago sales representative or authorized distributor for information. Remarks: The notation #XXX is used for existing products, while (new) products launched since July, and RoHS compliant will use XXXE.

5 UR Package Outline Drawings -Pin DIP Package (HCPL-/////) 9. ±. (. ±.). ±. (. ±.) TYPE NUMBER A XXXXZ OPTION CODE* DATE CODE. ±. (. ±.) YYWW UL RECOGNITION.9 (.) MAX.. ±. (. ±.). (.) MAX.. (.) MAX. TYP (. +.) -.).9 (.) MIN.. (.) MIN.. ±. (. ±.). (.) MAX.. ±. (. ±.) DIMENSIONS IN MILLIMETERS AND (INCHES). * MARKING CODE LETTER FOR OPTION NUMBERS "V" = OPTION OPTION NUMBERS AND NOT MARKED. NOTE: FLOATING LEAD PROTRUSION IS. mm ( mils) MAX. -Pin DIP Package with Gull Wing Surface Mount Option (HCPL-/////) LAND PATTERN RECOMMENDATION 9. ±. (. ±.). (.). ±. (. ±.).9 (.). (.). (.).9 (.) MAX.. (.) MAX.. ±. (. ±.) 9. ±. (. ±.). ±. (. ±.) (. +.) -.). ±. (. ±.).. ±. (.) (. ±.) BSC DIMENSIONS IN MILLIMETERS (INCHES). LEAD COPLANARITY =. mm (. INCHES).. ±. (. ±.) NOM. NOTE: FLOATING LEAD PROTRUSION IS. mm ( mils) MAX.

6 Small-Outline SO- Package (HCPL-/) LAND PATTERN RECOMMENDATION.9 ±. (. ±.) PIN ONE XXX YWW. ±. (. ±.). (.) BSC.99 ±. (. ±.) TYPE NUMBER (LAST DIGITS) DATE CODE. (.).9 (.).9 (.9) *. ±. (. ±.) X. (.). ±. (. ±.). (.) ~. ±. (.9 ±.) * TOTAL PACKAGE LENGTH (INCLUSIVE OF MOLD FLASH). ±. (. ±.) DIMENSIONS IN MILLIMETERS (INCHES). LEAD COPLANARITY =. mm (. INCHES) MAX.. (.) MIN.. ±. (. ±.) NOTE: FLOATING LEAD PROTRUSION IS. mm ( mils) MAX. -Pin Widebody DIP Package (HCNW/). ±. (. ±.) A HCNWXXXX YYWW TYPE NUMBER DATE CODE. MAX. (.) 9. ±. (. ±.). (.) MAX. TYP.. (.) MAX.. (.) TYP (. +.) -.). (.).9 (.). (.) MIN.. (.) TYP.. ±. (. ±.). (.). (.) DIMENSIONS IN MILLIMETERS (INCHES). NOTE: FLOATING LEAD PROTRUSION IS. mm ( mils) MAX.

7 -Pin Widebody DIP Package with Gull Wing Surface Mount Option (HCNW/). ±. (. ±.) LAND PATTERN RECOMMENDATION 9. ±. (. ±.). (.). (.).9 (.9). (.) MAX.. ±. (. ±.). MAX. (.). (.) MAX.. ±. (. ±.). (.) BSC DIMENSIONS IN MILLIMETERS (INCHES).. ±. (. ±.) LEAD COPLANARITY =. mm (. INCHES).. ±. (.9 ±.) NOM (. +.) -.) NOTE: FLOATING LEAD PROTRUSION IS. mm ( mils) MAX. Solder Reflow Temperature Profile TEMPERATURE ( C) PREHEATING RATE C + C/. C/SEC. REFLOW HEATING RATE. C ±. C/SEC. C C C C + C/. C. C ±. C/SEC. PREHEATING TIME C, 9 + SEC. PEAK TEMP. C SEC. SEC. SEC. PEAK TEMP. C SOLDERING TIME C PEAK TEMP. C ROOM TEMPERATURE TIME (SECONDS) TIGHT TYPICAL LOOSE Note: Non-halide flux should be used.

8 Recommended Pb-Free IR Profile TEMPERATURE T p +/- C T L C RAMP-UP C/SEC. MAX. T smax - C T smin t s PREHEAT to SEC. t p t L TIME WITHIN C of ACTUAL PEAK TEMPERATURE - SEC. RAMP-DOWN C/SEC. MAX. to SEC. t C to PEAK TIME NOTES: THE TIME FROM C to PEAK TEMPERATURE = MINUTES MAX. T smax = C, T smin = C Note: Non-halide flux should be used. Regulatory Information The HCPL-XX/XX and HCNWXX have been approved by the following organizations: UL Recognized under UL, Component Recognition Program, File E. CSA Approved under CSA Component Acceptance Notice #, File CA. IEC/EN/DIN EN -- Approved under: IEC --:99 + A: EN --: + A: DIN EN -- (VDE Teil ):- (Option and HCNW only) Insulation and Safety Related Specifications -pin DIP Package -Pin DIP Widebody ( Mil) SO- ( Mil) Parameter Symbol Value Value Value Units Conditions Minimum External L() mm Measured from input terminals Air Gap (External to output terminals, shortest Clearance) distance through air. Minimum External L()... mm Measured from input terminals Tracking (External to output terminals, shortest Creepage) distance path along body. Minimum Internal... mm Through insulation distance, Plastic Gap conductor to conductor, usually (Internal Clearance) the direct distance between the photoemitter and photodetector inside the optocoupler cavity. Minimum Internal NA NA. mm Measured from input terminals Tracking (Internal to output terminals, along Creepage) internal cavity. Tracking Resistance CTI Volts DIN IEC /VDE Part (Comparative Tracking Index) Isolation Group IIIa IIIa IIIa Material Group (DIN VDE, /9, Table ) Option - surface mount classification is Class A in accordance with CECC.

9 IEC/EN/DIN EN -- Insulation Related Characteristics (HCPL-/ Option ONLY) Description Symbol Characteristic Units Installation classification per DIN VDE /.9, Table for rated mains voltage V rms I-IV for rated mains voltage V rms I-III Climatic Classification // Pollution Degree (DIN VDE /.9) Maximum Working Insulation Voltage V IORM V peak Input to Output Test Voltage, Method b* V IORM x. = V PR, % Production Test with t m = sec, V PR V peak Partial Discharge < pc Input to Output Test Voltage, Method a* V IORM x. = V PR, Type and sample test, V PR 9 V peak t m = sec, Partial Discharge < pc Highest Allowable Overvoltage* (Transient Overvoltage, t ini = sec) V IOTM V peak Safety Limiting Values (Maximum values allowed in the event of a failure, also see Figure, Thermal Derating curve.) Case Temperature T S C Input Current I S,OUTPUT ma Output Power P S,OUTPUT mw Insulation Resistance at T S, V IO = V R S 9 Ω *Refer to the front of the optocoupler section of the current catalog, under Product Safety Regulations section IEC/EN/DIN EN --, for a detailed description. Note: Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in application.

10 IEC/EN/DIN EN -- Insulation Related Characteristics (HCNWXX ONLY) Description Symbol Characteristic Units Installation classification per DIN VDE /.9, Table for rated mains voltage V rms I-IV for rated mains voltage V rms I-III Climatic Classification // Pollution Degree (DIN VDE /.9) Maximum Working Insulation Voltage V IORM V peak Input to Output Test Voltage, Method b* V IORM x. = V PR, % Production Test with t m = sec, V PR V peak Partial Discharge < pc Input to Output Test Voltage, Method a* V IORM x. = V PR, Type and sample test, V PR V peak t m = sec, Partial Discharge < pc Highest Allowable Overvoltage* (Transient Overvoltage, t ini = sec) V IOTM V peak Safety Limiting Values (Maximum values allowed in the event of a failure, also see Figure, Thermal Derating curve.) Case Temperature T S C Current (Input Current I F, P S = ) I S,INPUT ma Output Power P S,OUTPUT mw Insulation Resistance at T S, V IO = V R S 9 Ω *Refer to the front of the optocoupler section of the current catalog, under Product Safety Regulations section IEC/EN/DIN EN --, for a detailed description. Note: Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in application. Absolute Maximum Ratings Parameter Symbol Min. Max. Units Note Storage Temperature T S - C Operating Temperature T A - C Average Forward Input Current I F(AVG) ma Peak Transient Input Current ( µs Pulse Width, pps) I F(TRAN). A ( µs Pulse Width, HCNWXX ma < % Duty Cycle) Reverse Input Voltage V R V HCNWXX Average Output Current I O ma Supply Voltage V Output Voltage V O -. V Total Package Power Dissipation P T mw HCPL-X 9 Output Power Dissipation P O See Figure Lead Solder Temperature (Through Hole Parts Only) C for sec.,. mm below seating plane HCNWXX C for sec., up to seating plane Solder Reflow Temperature Profile See Package Outline Drawings section (Surface Mount Parts Only) 9

11 Recommended Operating Conditions Parameter Symbol Min. Max. Units Power Supply Voltage. V Forward Input Current (ON) I F(ON).* ma HCPL-X. Forward Input Voltage (OFF) V F(OFF) -. V Operating Temperature T A - C Junction Temperature T J - C Fan Out N TTL Loads *The initial switching threshold is. ma or less. It is recommended that. ma be used to permit at least a % LED degradation guardband. The initial switching threshold is. ma or less. It is recommended that. ma be used to permit at least a % LED degradation guardband. Electrical Specifications - C T A C,. V V,. ma I F(ON) * ma, V V F(OFF). V, unless otherwise specified. All Typicals at T A = C. See Note. Parameter Sym. Min. Typ. Max. Units Test Conditions Fig. Note Logic Low Output Voltage V OL. V I OL =. ma ( TTL Loads), Logic High Output Voltage V OH. ** V I OH = -. ma,,. I OH = -. ma Output Leakage Current I OHH µa V O =. V I F = ma (V OUT > ) V O = V Logic Low Supply I CCL.. ma =. V V F = V Current.. = V I O = Open HCPL-X.. =. V.. = V Logic High Supply I CCH.. ma =. V I F = ma Current.. = V I O = Open HCPL-X.. =. V.. = V Logic Low Short Circuit I OSL ma V O = =. V V F = V, Output Current V O = = V Logic High Short Circuit I OSH - ma =. V I F = ma, Output Current - = V V O = Input Forward Voltage V F.. V T A = C I F = ma. HCNWXX.. T A = C.9 Input Reverse Breakdown BV R V I R = µa Voltage HCNWXX I R = µa Input Diode Temperature V F -. mv/ C I F = ma Coefficient HCNWXX T A -. Input Capacitance C IN pf f = MHz, V F = V, HCNWXX *For HCPL-X,. ma I F(ON) ma. **Typical V OH = -. V.

12 Switching Specifications (AC) - C T A C,. V V,. ma I F(ON) * ma, V V F(OFF). V. All Typicals at T A = C, = V, I F(ON) = ma unless otherwise specified. Parameter Sym. Min. Typ. Max. Units Test Conditions Fig. Note Propagation Delay Time t PHL ns Without Peaking Capacitor,, to Logic Low HCNWXX Output Level With Peaking Capacitor Propagation Delay Time t PLH ns Without Peaking Capacitor,, to Logic High HCNWXX Output Level 9 With Peaking Capacitor Output Rise Time (-9%) t r ns, 9 Output Fall Time (9-%) t f ns, 9 Parameter Sym. Device Min. Units Test Conditions Fig. Note Logic High CM H HCPL-/, V/µs V CM = V = V, Common Mode HCPL- I F =. ma T A = C Transient HCPL- Immunity HCNW HCPL-/, V/µs V CM = V HCPL- I F =. ma HCPL-, V/µs V CM = kv HCNW I F =. ma Logic Low CM L HCPL-/, V/µs V CM = V V F = V, Common Mode HCPL- = V Transient HCPL- T A = C Immunity HCNW HCPL-/, V/µs V CM = kv HCPL- HCPL- HCNW *For HCPL-X,. ma I F(ON) ma. I F =. ma for HCPL-. I F =. ma for HCPL-.

13 Package Characteristics Parameter Sym. Min. Typ. Max. Units Test Conditions Fig. Note Input-Output Momentary V ISO V rms RH < %, t = min., Withstand HCNWXX T A = C, Voltage * Input-Output Resistance R I-O Ω V I-O = Vdc HCNWXX T A = C T A = C Input-Output Capacitance C I-O. pf f = MHz, HCNWXX.. T A = C V I-O = Vdc Input-Input Insulation I I-I. µa Relative Humidity = %, Leakage Current t = s, V I-I = V Resistance (Input-Input) R I-I Ω V I-I = V Capacitance (Input-Input) C I-I. pf f = MHz *The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. For the continuous voltage rating refer to the IEC/EN/DIN EN -- Insulation Characteristics Table (if applicable), your equipment level safety specification or Avago Application Note entitled Optocoupler Input-Output Endurance Voltage, publication number 9-E. Notes:. Each channel.. Derate total package power dissipation, P T, linearly above C free-air temperature at a rate of. mw/ C.. Duration of output short circuit time should not exceed ms.. For single devices, input capacitance is measured between pin and pin.. Device considered a two-terminal device: pins,,, and shorted together and pins,,, and shorted together.. The t PLH propagation delay is measured from the % point on the leading edge of the input pulse to the. V point on the leading edge of the output pulse. The t PHL propagation delay is measured from the % point on the trailing edge of the input pulse to the. V point on the trailing edge of the output pulse.. CM H is the maximum slew rate of the common mode voltage that can be sustained with the output voltage in the logic high state, V O >. V. CM L is the maximum slew rate of the common mode voltage that can be sustained with the output voltage in the logic low state, V O <. V.. For HCPL-/, V O is on pin. 9. Use of a. µf bypass capacitor connected between pins and is recommended.. In accordance with UL, each optocoupler is proof tested by applying an insulation test voltage V rms for one second (leakage detection current limit, I I-O µa). This test is performed before the % production test for partial discharge (Method b) shown in the IEC/EN/DIN EN -- Insulation Characteristics Table, if applicable.. In accordance with UL, each optocoupler is proof tested by applying an insulation test voltage V rms for one second (leakage detection current limit, I I-O µa). This test is performed before the % production test for partial discharge (Method b) shown in the IEC/EN/DIN EN -- Insulation Characteristics Table.. For HCPL-/ only. Measured between pins and, shorted together, and pins and, shorted together.

14 V OL LOW LEVEL OUTPUT VOLTAGE V =. V V F = V I O =. ma - - T A TEMPERATURE C I OH HIGH LEVEL OUTPUT CURRENT ma V O =. V V O =. V =. V I F = ma - - T A TEMPERATURE C V O OUTPUT VOLTAGE V I O =. ma =. V T A = C. I O = -. ma. I F INPUT CURRENT ma. Figure. Typical logic low output voltage vs. temperature. Figure. Typical logic high output current vs. temperature. Figure. Typical output voltage vs. forward input current. I F FORWARD CURRENT ma... I F + V F HCPL-XX HCPL-XX T A = C I F FORWARD CURRENT ma... HCNWXX T A = C I F + V F V F FORWARD VOLTAGE V V F FORWARD VOLTAGE V Figure. Typical input diode forward characteristic. PULSE GEN. t r = t f = ns f = khz % DUTY CYCLE V O = V Z O = HCPL-/ HCPL-XX HCNWXX * OUTPUT V O MONITORING NODE D V 9 Ω PULSE GEN. t r = t f = ns f = khz % DUTY CYCLE V O = V Z O = HCPL-X OUTPUT V O MONITORING NODE V INPUT MONITORING NODE R C = pf C = pf THE PROBE AND JIG CAPACITANCES ARE INCLUDED IN C AND C. R. kω. kω I F (ON). ma ma Ω ma ALL DIODES ARE N9 OR N. kω D D D INPUT MONITORING NODE R C = pf C = pf THE PROBE AND JIG CAPACITANCES ARE INCLUDED IN C AND C. R.9 kω. kω I F (ON). ma ma * Ω ma D kω 9 Ω D D D INPUT I F I F (ON) % I F (ON) ma ALL DIODES ARE N9 OR N. OUTPUT V O PLH t PHL V OH. V VOL Figure. Circuit for t PLH, t PHL, t r,t f. *. µf BYPASS SEE NOTE 9.

15 t P PROPAGATION DELAY ns t PHL HCPL-XX HCPL-XX =. V, V C ( pf) PEAKING CAPACITOR IS USED. SEE FIGURE. *I F =. ma FOR HCPL-X DEVICES. I F (ma).*.* - t PLH t P PROPAGATION DELAY ns t PHL - HCNWXX =. V, V C ( pf) PEAKING CAPACITOR IS USED. SEE FIGURE. I F (ma) t PLH - -.., P O MAXIMUM OUTPUT POWER PER CHANNEL (mw) T A = C T A = C T A = C T A TEMPERATURE C T A TEMPERATURE C SUPPLY VOLTAGE V Figure. Typical propagation delays vs. temperature. Figure. Maximum output power per channel vs. supply voltage. V OH HIGH LEVEL OUTPUT VOLTAGE V TYPICAL V OH vs. AT I O = -. ma T A = C t r, t f RISE, FALL TIME ns - = V t r t f - - SUPPLY VOLTAGE V T A TEMPERATURE C Figure. Typical logic high output voltage vs. supply voltage. Figure 9. Typical rise, fall time vs. temperature. B R IN + V FF A HCPL-/ HCPL-XX HCNWXX. µf BYPASS OUTPUT V O MONITORING NODE + V FF R B A HCPL-/. µf BYPASS OUTPUT V O MONITORING NODE PULSE GENERATOR + V CM PULSE GENERATOR + V CM V CM V V OH OUTPUT V O V OL V CM (PEAK) SWITCH AT A: I F =. ma** V O (MIN.)* SWITCH AT B: V F = V V O (MAX.)* * SEE NOTE, 9. ** I F =. ma FOR HCPL-/ DEVICES. Figure. Test circuit for common mode transient immunity and typical waveforms.

16 INPUT CURRENT THRESHOLD ma..9.. I F (ON) I F (OFF) HCPL-XX HCPL-XX =. V = V. I F (ON) I F (OFF) INPUT CURRENT THRESHOLD ma..9. I F (ON). I F (OFF). I F (ON) I F (OFF). - HCNWXX =. V = V - - T A TEMPERATURE C T A TEMPERATURE C Figure. Typical input threshold current vs. temperature. OUTPUT POWER P S, INPUT CURRENT I S HCPL-/ OPTION P S (mw) I S (ma) T S CASE TEMPERATURE C OUTPUT POWER P S, INPUT CURRENT I S 9 HCNWXX P S (mw) I S (ma) T S CASE TEMPERATURE C Figure. Thermal derating curve, dependence of safety limiting value with case temperature per IEC/EN/DIN EN --. HCPL-/ HCPL-XX HCNWXX (+ V) (+ V). kω DATA OUTPUT DATA INPUT TTL OR LSTTL * UP TO LSTTL LOADS OR TTL LOADS *. µf BYPASS Figure a. Recommended LSTTL to LSTTL circuit where ns propagation delay is sufficient.

17 (+ V) Ω. kω pf HCPL-/ HCPL-XX HCNWXX (+ V) DATA OUTPUT DATA INPUT TTL OR LSTTL * UP TO LSTTL LOADS OR TTL LOADS *. µf BYPASS Figure b. Recommended LSTTL to LSTTL circuit for applications requiring a maximum allowable propagation delay of ns. (+ V) DATA INPUT TOTEM POLE OUTPUT GATE Ω*. kω TTL OR LSTTL pf* V V V V HCPL-/ HCPL-XX HCNWXX R L. kω. kω. kω. kω ** (. TO V) R L CMOS **. µf BYPASS DATA OUTPUT * pf PEAKING CAPACITOR MAY BE OMITTED AND Ω RESISTOR MAY BE SHORTED WHERE ns PROPAGATION DELAY IS SUFFICIENT. (+ V) DATA INPUT TTL or LSTTL. kω D HCPL-/ HCPL-XX HCNWXX D (N) REQUIRED FOR ACTIVE PULL-UP DRIVER. Figure. LSTTL to CMOS interface circuit. Figure. Alternative LED drive circuit. (+ V) DATA INPUT Ω*. kω pf*. kω TTL OR LSTTL HCPL-/ HCPL-XX HCNWXX OPEN COLLECTOR GATE * pf PEAKING CAPACITOR MAY BE OMITTED AND Ω RESISTOR MAY BE SHORTED WHERE ns PROPAGATION DELAY IS SUFFICIENT. Figure. Series LED drive with open collector gate (. k resistor shunts I OH from the LED).

18 For product information and a complete list of distributors, please go to our website: Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies Limited in the United States and other countries. Data subject to change. Copyright Avago Technologies Limited. All rights reserved. Obsoletes 99-EN AV-EN July,

MIL-STD-1772 Version Available (HCPL-52XX/62XX)

MIL-STD-1772 Version Available (HCPL-52XX/62XX) H Very High CMR, Wide Logic Gate Optocouplers Technical Data HCPL- HCPL- HCPL- HCPL- HCNW HCPL- HCPL- HCPL- HCPL- HCNW Features kv/µs Minimum Common Mode Rejection (CMR) at V CM = V (HCPL-///, HCNW) Wide