HCPL-3150 (Single Channel), HCPL-315J (Dual Channel)

Transcription

1 Data Sheet HCPL- (Single Channel), HCPL-J (Dual Channel). Amp Output Current IGBT Gate Drive Optocoupler Overview The HCPL-X consists of an LED optically coupled to an integrated circuit with a power output stage. This optocoupler is ideally suited for driving power IGBTs and MOSFETs used in motor control inverter applications. The high operating voltage range of the output stage provides the drive voltages required by gate-controlled devices. The voltage and current supplied by this optocoupler makes it ideally suited for directly driving IGBTs with ratings up to V/A. For IGBTs with higher ratings, the HCPL-/J can be used to drive a discrete power stage which drives the IGBT gate. Applications Isolated IGBT/MOSFET gate drive AC and brushless DC motor drives Industrial inverters Switch mode power supplies (SMPSs) Uninterruptable power supplies (UPSs) Features.A maximum peak output current.a minimum peak output current -kv/µs minimum Common Mode Rejection (CMR) at V CM = V.V maximum low level output voltage (V OL ) eliminates need for negative gate drive I CC = ma maximum supply current Under voltage lock-out protection (UVLO) with hysteresis Wide operating V CC range: V to V.-µs maximum propagation delay ±.-µs maximum delay between devices/channels Industrial temperature range: C to C HCPL-J: channel one to channel two output isolation = Vrms/ min. Safety and regulatory approval: UL recognized (UL), Vrms/ min. (HCPL-) Vrms/ min. (HCPL-J) IEC/EN/DIN EN -- approved V IORM = V peak (HCPL- option only) V IORM = V peak (HCPL-J) CSA certified CAUTION! It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation that may be induced by ESD. The components featured in this data sheet are not to be used in military or aerospace applications or environments. AV-EN October,

2 HCPL- (Single Channel), HCPL-J (Dual Channel) Data Sheet. Amp Output Current IGBT Gate Drive Optocoupler Functional Diagram N/C V CC N/C ANODE CATHODE N/C SHIELD HCPL- V CC V O V O V EE ANODE CATHODE ANODE CATHODE N/C SHIELD SHIELD HCPL-J 9 V O V EE V CC V O V EE LED OFF ON ON ON V CC V EE POSITIVE-GOING (i.e. TURN-ON) - V - V -. V. - V TRUTH TABLE V CC V EE NEGATIVE-GOING (i.e. TURN-OFF) - V - 9. V 9. - V - V V O LOW LOW TRANSITION HIGH NOTE: A.-µF bypass capacitor must be connected between the V CC and V EE pins for each channel. Selection Guide: Inverter Gate Drive Optoisolators Package Type -Pin DIP ( mil) Widebody ( mil) Small Outline SO- Part Number HCPL- HCPL- HCPL-J HCPL-J HCNW- HCPL-J HCPL-J HCPL-J Number of Channels IEC/EN/DIN EN -- Approvals V IORM Vpeak Option V IORM Vpeak V IORM Vpeak V IORM Vpeak UL Approval Vrms/ min. Vrms/min. Vrms/ min. Vrms/ min. Output Peak Current.A A A.A A.A A.A CMR (Minimum) kv/µs kv/µs kv/µs kv/µs UVLO Yes No Yes No Fault Status No Yes No AV-EN

3 HCPL- (Single Channel), HCPL-J (Dual Channel) Data Sheet. Amp Output Current IGBT Gate Drive Optocoupler Ordering Information HCPL- is UL Recognized with Vrms for minute per UL. HCPL-J is UL Recognized with Vrms for minute per UL. Option RoHS Non RoHS Surface IEC/EN/DIN Part Number Compliant Compliant Package Mount Gull Wing Tape & Reel EN -- Quantity HCPL- -E No option mil per tube -E # DIP- X X per tube -E # X X X per reel -E # X per tube -E # X X X per tube -E # X X X X per reel -ME No option X X X X per reel HCPL-J -E No option SO- X X per tube -E # X X X per reel To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. Example : HCPL--E to order product of mil DIP Gull Wing Surface Mount package in Tape and Reel packaging with IEC/EN/DIN EN -- Safety Approval in RoHS compliant. Example : HCPL- to order product of mil DIP package in tube packaging and non RoHS compliant. Option data sheets are available. Contact your sales representative or authorized distributor for information. NOTE: The notation #XXX is used for existing products, while (new) products launched since July, and RoHS compliant option use -XXXE. AV-EN

4 HCPL- (Single Channel), HCPL-J (Dual Channel) Data Sheet. Amp Output Current IGBT Gate Drive Optocoupler Package Outline Drawings Standard DIP Package 9. ±. (. ±.) Device Part Number. ±. (. ±.) Avago Lead Free Pin Dot A NNNN YYWW EEE Z P Test Rating Code UL Logo Special Program Code. ±. (. ±.) Date Code Lot ID.9 (.) MAX.. ±. (. ±.). (.) MAX.. (.) MAX. TYP (. +.) -.). (.) MIN..9 (.) MIN.. ±. (. ±.). (.) MAX.. ±. (. ±.) DIMENSIONS IN MILLIMETERS AND (INCHES). OPTION NUMBERS AND NOT MARKED. NOTE: FLOATING LEAD PROTRUSION IS. mm ( mils) MAX. AV-EN

5 HCPL- (Single Channel), HCPL-J (Dual Channel) Data Sheet. Amp Output Current IGBT Gate Drive Optocoupler Gull-Wing Surface-Mount Option 9. ±. (. ±.) Device Part Number LAND PATTERN RECOMMENDATION. (.) Avago Lead Free Pin Dot A NNNN YYWW EEE Z P Test Rating Code. ±. UL Logo (. ±.) Special Program Code.9 (.) Date Code Lot ID. (.). (.).9 (.) MAX.. (.) MAX.. ±. (. ±.) 9. ±. (. ±.). ±. (. ±.) (. +.) -.). ±. (. ±.). (.) BSC. ±. (. ±.). ±. (. ±.) NOM. DIMENSIONS IN MILLIMETERS (INCHES). LEAD COPLANARITY =. mm (. INCHES). NOTE: FLOATING LEAD PROTRUSION IS. mm ( mils) MAX. AV-EN

6 HCPL- (Single Channel), HCPL-J (Dual Channel) Data Sheet. Amp Output Current IGBT Gate Drive Optocoupler -Lead Surface Mount Package. (.). (.) LAND PATTERN RECOMMENDATION. (.) 9 TYPE NUMBER AVAGO LEAD-FREE A XXXX YYWW EEE.9 ±. (.9 ±.) DATE CODE. (.) PIN DOT LOT ID. (.) 9. ±. (. ±.). ±. (. ±.) ALL LEADS TO BE COPLANAR ±. (.). (.). ±. (. ±.) -. (.) MIN.. ±. (. ±.). ±. (. ±.) STANDOFF Dimensions in Millimeters (Inches) Floating lead protrusion is. mm ( mils) Max. Note: Initial and continued variation in color of the white mold compound is normal and does not affect performance or reliability of the device Recommended Pb-Free IR Profile Recommended reflow condition as per JEDEC Standard, J-STD- (latest revision). Non-halide flux should be used. Regulatory Information The HCPL- and HCPL-J have been approved by the following organizations. UL Recognized under UL, Component Recognition Program, File E. CSA Approved under CSA Component Acceptance Notice #, File CA. IEC/EN/DIN EN -- Approved under: DIN EN --(VDE -):- (Option and HCPL-J only) AV-EN

7 HCPL- (Single Channel), HCPL-J (Dual Channel) Data Sheet. Amp Output Current IGBT Gate Drive Optocoupler IEC/EN/DIN EN -- Insulation Characteristics Description Symbol HCPL-# HCPL-J Units Installation classification per DIN VDE /.9, Table For rated mains voltage Vrms For rated mains voltage Vrms For rated mains voltage Vrms For rated mains voltage Vrms Climatic Classification // // Pollution Degree (DIN VDE /.9) Maximum Working Insulation Voltage V IORM Vpeak I - IV I - III I - II I - IV I - IV I - IV I-III Input to Output Test Voltage, Method b a V IORM. = V PR, % Production Test with t m = second, Partial discharge < pc Input to Output Test Voltage, Method a a V IORM. = V PR, Type and Sample Test, t m = seconds, Partial discharge < pc Highest Allowable Overvoltage a (Transient Overvoltage t ini = seconds) V PR Vpeak V PR 9 Vpeak V IOTM Vpeak Safety-Limiting Values Maximum Values Allowed in the Event of a Failure, Also See Figure and Figure. Case Temperature Input Current Output Power T S I S, INPUT P S, OUTPUT C ma mw Insulation Resistance at T S, V IO = V R S 9 9 Ω a. Refer to IEC/EN/DIN EN -- Optoisolator Safety Standard section of the Regulatory Guide to Isolation Circuits, AV-EN for a detailed description of Method a and Method b partial discharge test profiles. NOTE: Isolation characteristics are guaranteed only within the safety maximum ratings that must be ensured by protective circuits in application. AV-EN

8 HCPL- (Single Channel), HCPL-J (Dual Channel) Data Sheet. Amp Output Current IGBT Gate Drive Optocoupler Insulation and Safety Related Specifications Parameter Symbol HCPL- HCPL-J Units Conditions Minimum External Air Gap (External Clearance Minimum External Tracking (External Creepage) Minimum Internal Plastic Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) L().. mm Measured from input terminals to output terminals, shortest distance through air. L().. mm Measured from input terminals to output terminals, shortest distance path along body... mm Through insulation distance conductor to conductor. CTI Volts DIN IEC /VDE Part Isolation Group IIIa IIIa Material Group (DIN VDE, /9, Table ) Option surface mount classification is Class A in accordance with CECC. Absolute Maximum Ratings Parameter Symbol Min. Max. Units Note Storage Temperature T S C Operating Temperature T A C Average Input Current I F(AVG) ma a, b Peak Transient Input Current (<-µs pulse width, pps) I F(TRAN). A Reverse Input Voltage V R Volts High Peak Output Current I OH(PEAK). A b, c Low Peak Output Current I OL(PEAK). A b, c Supply Voltage (V CC V EE ) Volts Output Voltage V O(PEAK) V CC Volts Output Power Dissipation P O mw b, d Total Power Dissipation P T 9 mw b, e Lead Solder Temperature C for seconds,. mm below seating plane Solder Reflow Temperature Profile See Package Outline Drawings Section a. Derate linearly above C free-air temperature at a rate of. ma/ C. b. Each channel. c. Maximum pulse width = µs, maximum duty cycle =.%. This value is intended to allow for component tolerances for designs with I O peak minimum =.A. See the Applications section for additional details on limiting I O H peak. d. Derate linearly above C free-air temperature at a rate of. mw/ C. e. Derate linearly above C free-air temperature at a rate of. mw/ C. The maximum LED junction temperature should not exceed C. AV-EN

9 HCPL- (Single Channel), HCPL-J (Dual Channel) Data Sheet. Amp Output Current IGBT Gate Drive Optocoupler Recommended Operating Conditions Parameter Symbol Min. Max. Units Power Supply Voltage (V CC V EE ) V Input Current (ON) I F(ON) ma Input Voltage (OFF) V F(OFF).. V Operating Temperature T A C AV-EN 9

10 HCPL- (Single Channel), HCPL-J (Dual Channel) Data Sheet. Amp Output Current IGBT Gate Drive Optocoupler Electrical Specifications (DC) Over recommended operating conditions (T A = C to C, I F(ON) = ma to ma, V F(OFF) =.V to.v, V CC = V to V, V EE = Ground, each channel) unless otherwise specified. Parameter Symbol Min. Typ. a Max. Units Test Conditions Figure Note High Level Output Current I OH.. A V O = (V CC V),,. V O = (V CC V) b Low Level Output Current I OL.. A V O = (V EE +.V), c a. All typical values at T A = C and V CC V EE = V, unless otherwise noted. b. Maximum pulse width = µs, maximum duty cycle =.%. This value is intended to allow for component tolerances for designs with I O peak minimum =. A. See Applications section for additional details on limiting I OH peak. c. Maximum pulse width = µs, maximum duty cycle =.%.. V O = (V EE + V) b High Level Output Voltage V OH (V CC ) (V CC ) V I O = ma,, 9 d, e Low Level Output Voltage V OL.. V I O = ma,, High Level Supply Current I CCH.. ma Output Open, I F = to ma, f Low Level Supply Current I CCL.. ma Output Open, V F =. to +.V Threshold Input Current Low to High I FLH.... ma HCPL- HCPL-J I O = ma, V O > V Threshold Input Voltage High V FHL. V to Low Input Forward Voltage V F... V HCPL- I F = ma..9 HCPL-J Temperature Coefficient of ΔV F /ΔT A. mv/ C I F = ma Forward Voltage Input Reverse Breakdown BV R V HCPL- I R = µa Voltage HCPL-J I R = µa Input Capacitance C IN pf f = MHz, V F = V UVLO Threshold V UVLO+... V V O > V, V UVLO I F = ma UVLO Hysteresis UVLO HYS. V d. In this test, V OH is measured with a dc load current. When driving capacitive loads V OH will approach V CC as I OH approaches zero amps. e. Maximum pulse width = ms, maximum duty cycle = %. f. Each channel. 9,, AV-EN

11 HCPL- (Single Channel), HCPL-J (Dual Channel) Data Sheet. Amp Output Current IGBT Gate Drive Optocoupler Switching Specifications (AC) Over recommended operating conditions (T A = to C, I F(ON) = ma to ma, V F(OFF) =.V to.v, V CC = V to V, V EE = Ground, each channel) unless otherwise specified. Parameter Symbol Min. Typ. a Propagation Delay Time to High t PLH... µs Rg = Ω, Cg = nf, Output Level f = khz, Duty Cycle = % Propagation Delay Time to Low Output Level t PHL... µs a. All typical values at T A = C and V CC V EE = V, unless otherwise noted. b. This load condition approximates the gate load of a V/ A IGBT c. Pulse Width Distortion (PWD) is defined as t PHL t PLH for any given device. Max. Units Test Conditions Figure Note,,,,, Pulse Width Distortion PWD. µs c Propagation Delay Difference Between Any Two Parts or Channels PDD (t PHL t PLH ).. µs, 9 d Rise Time t r. µs Fall Time t f. µs UVLO Turn On Delay t UVLO ON. µs V O > V, I F = ma UVLO Turn Off Delay t UVLO OFF. µs V O < V, I F = ma Output High Level Common Mode Transient Immunity Output Low Level Common Mode Transient Immunity CM H kv/µs T A = C, I F = to ma, V CM = V, V CC = V CM L kv/µs T A = C, V CM = V, V F = V, V CC = V d. The difference between t PHL and t PLH between any two parts or channels under the same test condition. b e, f e. Pins and (HCPL-) and pins and (HCPL-J) need to be connected to LED common. f. Common mode transient immunity in the high state is the maximum tolerable dv CM /dt of the common mode pulse, V CM, to assure that the output will remain in the high state (that is, V O >.V). g. Common mode transient immunity in a low state is the maximum tolerable dv CM /dt of the common mode pulse, V CM, to assure that the output will remain in a low state (that is, V O <.V). e, g AV-EN

12 HCPL- (Single Channel), HCPL-J (Dual Channel) Data Sheet. Amp Output Current IGBT Gate Drive Optocoupler Package Characteristics Each channel, unless otherwise specified. Parameter Symbol Device Min. Typ. a Max. Units Test Conditions Figure Note Input-Output Momentary V ISO HCPL- Vrms RH < %, t = min., c, d Withstand Voltage b HCPL-J T A = C Output-Output Momentary V O-O HCPL-J Vrms RH < %, t = min., e Withstand Voltage b T A = C Resistance (Input-Output) R I-O Ω V I-O = V DC f Capacitance (Input-Output) C I-O HCPL-. pf f = MHz HCPL-J. LED-to-Case Thermal Resistance LED-to-Detector Thermal Resistance Detector-to-Case Thermal Resistance θ LC HCPL- 9 C/W Thermocouple located at center θ LD HCPL- 9 C/W underside of package θ DC HCPL- 9 C/W a. All typical values at T A = C and V CC V EE = V, unless otherwise noted. b. The Input-Output/Output-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output/ output-output continuous voltage rating. For the continuous voltage rating, refer to your equipment level safety specification or Application Note, Optocoupler Input-Output Endurance Voltage. c. In accordance with UL, each HCPL- optocoupler is proof tested by applying an insulation test voltage Vrms ( Vrms for the HCPL-J) for second. This test is performed before the % production test for partial discharge (method b) shown in the IEC/ EN/DIN EN -- Insulation Characteristics Table, if applicable. d. Device considered a two-terminal device: pins on input side shorted together and pins on output side shorted together. e. Device considered a two terminal device: Channel one output side pins shorted together, and channel two output side pins shorted together. f. Device considered a two-terminal device: pins on input side shorted together and pins on output side shorted together. g. See the thermal model for the HCPL-J in the application section of this data sheet. 9, g AV-EN

13 HCPL- (Single Channel), HCPL-J (Dual Channel) Data Sheet. Amp Output Current IGBT Gate Drive Optocoupler Figure : V OH vs. Temperature Figure : I OH vs. Temperature Figure : V OH vs. I OH (V OH - V CC ) HIGH OUTPUT VOLTAGE DROP V I F = to ma I OUT = - ma V CC = to V V EE = V I OH OUTPUT HIGH CURRENT A I F = to ma V OUT = V CC - V V CC = to V V EE = V (V OH - V CC ) OUTPUT HIGH VOLTAGE DROP V I F = to ma V CC = to V V EE = V. C C - C.... T A TEMPERATURE C T A TEMPERATURE C I OH OUTPUT HIGH CURRENT A Figure : V OL vs. Temperature Figure : I OL vs. Temperature Figure : V OL vs. I OL V OL OUTPUT LOW VOLTAGE V V F(OFF) = -. to. V I OUT = ma V CC = to V V EE = V - T A TEMPERATURE C I OL OUTPUT LOW CURRENT A V F(OFF) = -. to. V V OUT =. V V CC = to V V EE = V - T A TEMPERATURE C V OL OUTPUT LOW VOLTAGE V V F(OFF) = -. to. V V CC = to V V EE = V.... I OL OUTPUT LOW CURRENT A C C - C. Figure : I CC vs. Temperature Figure : I CC vs. V CC Figure 9: I FLH vs. Temperature I CC SUPPLY CURRENT ma V CC = V V EE = V I F = ma for I CCH I F = ma for I CCL T A TEMPERATURE C I CCH I CCL I CC SUPPLY CURRENT ma..... I F = ma for I CCH I F = ma for I CCL T A = C V EE = V V CC SUPPLY VOLTAGE V I CCH I CCL I FLH LOW TO HIGH CURRENT THRESHOLD ma - - V CC = TO V V EE = V OUTPUT = OPEN T A TEMPERATURE C AV-EN

14 HCPL- (Single Channel), HCPL-J (Dual Channel) Data Sheet. Amp Output Current IGBT Gate Drive Optocoupler Figure : Propagation Delay vs. V CC Figure : Propagation Delay vs. I F Figure : Propagation Delay vs. Temperature T p PROPAGATION DELAY ns I F = ma T A = C Rg = Cg = nf DUTY CYCLE = % f = khz T PLH T PHL T p PROPAGATION DELAY ns V CC = V, V EE = V Rg =, Cg = nf T A = C DUTY CYCLE = % f = khz T p PROPAGATION DELAY ns I F(ON) = ma I F(OFF) = ma V CC = V, V EE = V Rg =, Cg = nf DUTY CYCLE = % f = khz T PLH T PHL - - T PLH T PHL V CC SUPPLY VOLTAGE V I F FORWARD LED CURRENT ma T A TEMPERATURE C Figure : Propagation Delay vs. Rg Figure : Propagation Delay vs. Cg Figure : Transfer Characteristics T p PROPAGATION DELAY ns V CC = V, V EE = V T A = C I F = ma Cg = nf DUTY CYCLE = % f = khz Rg SERIES LOAD RESISTANCE T PLH T PHL T p PROPAGATION DELAY ns V CC = V, V EE = V T A = C I F = ma Rg = DUTY CYCLE = % f = khz Cg LOAD CAPACITANCE nf T PLH T PHL V O OUTPUT VOLTAGE V I F FORWARD LED CURRENT ma Figure : Input Current vs. Forward Voltage T A = C I F FORWARD CURRENT ma... V F + I F V F FORWARD VOLTAGE V. AV-EN

15 HCPL- (Single Channel), HCPL-J (Dual Channel) Data Sheet Figure : I OH Test Circuit Figure : I OL Test Circuit. Amp Output Current IGBT Gate Drive Optocoupler I F = to ma. μf V V CC = to V. μf I OL. V V CC = to V I OH Figure 9: V OH Test Circuit Figure : V OL Test Circuit I F = to ma. μf V OH ma V CC = to V. μf V OL ma V CC = to V Figure : I FLH Test Circuit Figure : UVLO Test Circuit. μf. μf I F + V O > V V CC = to V I F = ma + V O > V V CC AV-EN

16 HCPL- (Single Channel), HCPL-J (Dual Channel) Data Sheet. Amp Output Current IGBT Gate Drive Optocoupler Figure : t PLH, t PHL, t r, and t f Test Circuit and Waveforms KHz % DUTY CYCLE I F = to ma +. μf V O V CC = to V I F t r t f 9% % nf V OUT % t PLH t PHL Figure : CMR Test Circuit and Waveforms V CM V I F A + B. μf V O V CC = V V V O t V V CM = t t V OH SWITCH AT A: I F = ma V O V OL + V CM = V SWITCH AT B: I F = ma Applications Information Eliminating Negative IGBT Gate Drive To keep the IGBT firmly off, the HCPL-/J has a very low maximum V OL specification of.v. The HCPL-/J realizes this very low V OL by using a DMOS transistor with Ω (typical) on resistance in its pull-down circuit. When the HCPL/J is in the low state, the IGBT gate is shorted to the emitter by Rg + Ω. Minimizing Rg and the lead inductance from the HCPL-/J to the IGBT gate and emitter (possibly by mounting the HCPL-/J on a small PC board directly above the IGBT) can eliminate the need for negative IGBT gate drive in many applications as shown in Figure and Figure. Care should be taken with such a PC board design to avoid routing the IGBT collector or emitter traces close to the HCPL-/J input as this can result in unwanted coupling of transient signals into the HCPL-/ J and degrade performance. (If the IGBT drain must be routed near the HCPL-/J input, then the LED should be reverse-biased when in the off state, to prevent the transient signals coupled from the IGBT drain from turning on the HCPL- /J.) AV-EN

17 HCPL- (Single Channel), HCPL-J (Dual Channel) Data Sheet. Amp Output Current IGBT Gate Drive Optocoupler Figure : Recommended LED Drive and Application Circuit + V HCPL-. μf V CC = V + HVDC Rg CONTROL INPUT Q -PHASE AC XXX OPEN COLLECTOR Q - HVDC Figure : Recommended LED Drive and Application Circuit (HCPL-J) + V CONTROL INPUT XX OPEN COLLECTOR HCPL-J. μf FLOATING SUPPLY V CC = V Rg + HVDC GND -PHASE AC + V CONTROL INPUT XX OPEN COLLECTOR. μf 9 V CC = V Rg GND - HVDC AV-EN

18 HCPL- (Single Channel), HCPL-J (Dual Channel) Data Sheet. Amp Output Current IGBT Gate Drive Optocoupler Selecting the Gate Resistor (Rg) to Minimize IGBT Switching Losses Step : Calculate Rg Minimum From the IOL Peak Specification. The IGBT and Rg in Figure and Figure can be analyzed as a simple RC circuit with a voltage supplied by the HCPL-/J. Rg = = (V CC V EE - V OL ) I OLPEAK (V CC V EE -. V) I OLPEAK ( V + V -. V). A =. Ω The V OL value of V in the previous equation is a conservative value of V OL at the peak current of.a (see Figure ). At lower Rg values the voltage supplied by the HCPL-/J is not an ideal voltage step. This results in lower peak currents (more margin) than predicted by this analysis. When negative gate drive is not used V EE in the previous equation is equal to zero volts. Step : Check the HCPL-/J Power Dissipation and Increase Rg if Necessary. The HCPL-/J total power dissipation (P T ) is equal to the sum of the emitter power (P E ) and the output power (P O ): P T = P E + P O P E = I V F Duty Cycle F P O = P O(BIAS) + P O (SWITCHING) = I (V - V ) + E (R, Q ) CC f CC EE SW G G For the circuit in Figure and Figure with I F (worst case) = ma, Rg =.Ω, Max Duty Cycle = %, Qg = nc, f = khz, and T A max = 9 C: P E = ma. V. = mw P O =. ma V +. μj khz = mw + mw = mw > mw (P 9 C = mw C. mw/c) Figure : HCPL- Typical Application Circuit with Negative IGBT Gate Drive + V HCPL-. μf V CC = V + HVDC Rg CONTROL INPUT XXX OPEN COLLECTOR + V EE = - V Q Q -PHASE AC - HVDC AV-EN

19 HCPL- (Single Channel), HCPL-J (Dual Channel) Data Sheet. Amp Output Current IGBT Gate Drive Optocoupler Figure : HCPL-J Typical Application Circuit with Negative IGBT Gate Drive + V CONTROL INPUT XX OPEN COLLECTOR GND HCPL-J. μf FLOATING SUPPLY V CC = V + Rg V EE = - V + HVDC -PHASE AC + V CONTROL INPUT XX OPEN COLLECTOR GND. μf 9 V CC = V + Rg V CC = - V - HVDC Table : P E and P O Parameters P E Parameter Description P O Parameter Description I F LED Current I CC Supply Current V F LED On Voltage V CC Positive Supply Voltage Duty Cycle Maximum LED Duty Cycle V EE Negative Supply Voltage E SW (Rg,Qg) Energy Dissipated in the HCPL-/J for each IGBT Switching Cycle (see Figure ) f Switching Frequency AV-EN 9

20 HCPL- (Single Channel), HCPL-J (Dual Channel) Data Sheet The value of. ma for I CC in the previous equation was obtained by derating the I CC max of ma (which occurs at C) to I CC max at 9 C (see Figure ). Since P O for this case is greater than P O(MAX), Rg must be increased to reduce the HCPL- power dissipation. P O(SWITCHING MAX) = P O(MAX) - P O(BIAS) E SW(MAX) = = mw - mw = 9 mw P O(SWITCHINGMAX) f 9 mw = =. μj khz. Amp Output Current IGBT Gate Drive Optocoupler Thermal Model (HCPL-) The steady state thermal model for the HCPL- is shown in Figure 9. The thermal resistance values given in this model can be used to calculate the temperatures at each node for a given operating condition. As shown by the model, all heat generated flows through θ CA which raises the case temperature T C accordingly. The value of θ CA depends on the conditions of the board design and is, therefore, determined by the designer. The value of θ CA = C/W was obtained from thermal measurements using a. in.. in. PC board, with small traces (no ground plane), a single HCPL- soldered into the center of the board and still air. The absolute maximum power dissipation derating specifications assume a θ CA value of C/W. For Qg = nc, from Table, a value of E SW =. µj gives a Rg = Ω. Figure 9: Thermal Model LD = 9 C/W T JE LC = 9 C/W T C T JD DC = 9 C/W CA = C/W* T A T JE = LED JUNCTION TEMPERATURE T JD = DETECTOR IC JUNCTION TEMPERATURE T C = CASE TEMPERATURE MEASURED AT THE CENTER OF THE PACKAGE BOTTOM LC = LED-TO-CASE THERMAL RESISTANCE LD = LED-TO-DETECTOR THERMAL RESISTANCE DC = DETECTOR-TO-CASE THERMAL RESISTANCE CA = CASE-TO-AMBIENT THERMAL RESISTANCE * CA WILL DEPEND ON THE BOARD DESIGN AND THE PLACEMENT OF THE PART. AV-EN

21 HCPL- (Single Channel), HCPL-J (Dual Channel) Data Sheet From the thermal mode in Figure 9, the LED and detector IC junction temperatures can be expressed as: T JE = P E ( LC ( LD + DC ) + CA ) LC DC + P D ( + CA ) + T A LC + DC + LD LC T DC JD = P ( + E LC + DC + LD CA) + P D ( DC ( LD + LC ) + CA ) + T A Inserting the values for θ LC and θ DC shown in Figure 9 gives:. Amp Output Current IGBT Gate Drive Optocoupler Thermal Model Dual-Channel (SOIC-) HCPL-J Optoisolator Definitions θ, θ, θ, θ, θ, θ, θ, θ, θ 9, θ : Thermal impedances between nodes as shown in Figure. Ambient Temperature: Measured approximately. cm above the optocoupler with no forced air. Figure : Thermal Impedance Model for HCPL-J LED LED T JE = P ( C/W + ) + P (9 C/W + ) + T E CA D CA A T JD = P (9 C/W + ) + P ( C/W + ) + T E CA D CA A For example, given P E = mw, P O = mw, T A = C and θ CA = C/W: DETECTOR DETECTOR 9 T JE = P E C/W + P D C/W + T A = mw C/W + mw C/W + C = C T JD = P E C/W + P D C/W + T A = mw C/W + mw C/W + C = C AMBIENT T JE and T JD should be limited to C based on the board layout and part placement (θ CA ) specific to the application. Figure : Power Dissipation P E P D P E P D Description This thermal model assumes that a -pin dual-channel (SOIC-) optocoupler is soldered into an. cm. cm printed circuit board (PCB). These optocouplers are hybrid devices with four die: two LEDs and two detectors. The temperature at the LED and the detector of the optocoupler can be calculated by using the equations below. AV-EN

22 HCPL- (Single Channel), HCPL-J (Dual Channel) Data Sheet. Amp Output Current IGBT Gate Drive Optocoupler T EA = A P E + A P E +A P D +A P D T EA = A P E + A P E +A P D +A P D T DA = A P E + A P E +A P D +A P D T DA = A P E + A P E +A P D +A P D where: ΔT EA = Temperature difference between ambient and LED ΔT EA = Temperature difference between ambient and LED ΔT DA = Temperature difference between ambient and detector ΔT DA = Temperature difference between ambient and detector P E = Power dissipation from LED ; P E = Power dissipation from LED ; P D = Power dissipation from detector ; P D = Power dissipation from detector A xy thermal coefficient (units in C/W) is a function of thermal impedances θ through θ. Table : Thermal Coefficient Data (units in C/W) Part Number A, A A, A A, A A, A A, A A, A A, A A, A HCPL-J NOTE: Maximum junction temperature for above part: C. AV-EN

23 HCPL- (Single Channel), HCPL-J (Dual Channel) Data Sheet LED Drive Circuit Considerations for Ultra High CMR Performance Without a detector shield, the dominant cause of optocoupler CMR failure is capacitive coupling from the input side of the optocoupler, through the package, to the detector IC as shown in Figure. The HCPL-/J improves CMR performance by using a detector IC with an optically transparent Faraday shield, which diverts the capacitively coupled current away from the sensitive IC circuitry. How ever, this shield does not eliminate the capacitive coupling between the LED and optocoupler pins to as shown in Figure. This capacitive coupling causes perturbations in the LED current during common mode transients and becomes the major source of CMR failures for a shielded optocoupler. The main design objective of a high CMR LED drive circuit becomes keeping the LED in the proper state (on or off) during common mode transients. For example, the recommended application circuit (Figure and Figure ), can achieve kv/µs CMR while minimizing component complexity. Techniques to keep the LED in the proper state are discussed in the next two sections. CMR with the LED On (CMR H ) A high CMR LED drive circuit must keep the LED on during common mode transients. This is achieved by overdriving the LED current beyond the input threshold so that it is not pulled below the threshold during a transient. A minimum LED current of ma provides adequate margin over the maximum I FLH of ma to achieve kv/µs CMR. Figure : Energy Dissipated in the HCPL- for Each IGBT Switching Cycle.. Amp Output Current IGBT Gate Drive Optocoupler CMR with the LED Off (CMR L ) A high CMR LED drive circuit must keep the LED off (V F V F(OFF) ) during common mode transients. For example, during a dv CM /dt transient in Figure, the current flowing through C LEDP also flows through the R SAT and V SAT of the logic gate. As long as the low state voltage developed across the logic gate is less than V F(OFF), the LED will remain off and no common mode failure will occur. The open collector drive circuit, shown in Figure, cannot keep the LED off during a +dv CM /dt transient, since all the current flowing through C LEDN must be supplied by the LED, and it is not recommended for applications requiring ultra-high CMR L performance. Figure is an alternative drive circuit which, like the recommended application circuit (Figure and Figure ), does achieve ultra-high CMR performance by shunting the LED in the off state. Under Voltage Lockout Feature The HCPL-/J contains an under voltage lockout (UVLO) feature that is designed to protect the IGBT under fault conditions that cause the HCPL-/J supply voltage (equivalent to the fully-charged IGBT gate voltage) to drop below a level necessary to keep the IGBT in a low resistance state. When the HCPL-/J output is in the high state and the supply voltage drops below the HCPL-/J V UVLO- threshold (9. < V UVLO- <.), the optocoupler output will go into the low state with a typical delay, UVLO Turn Off Delay, of. µs. When the HCPL-/J output is in the low state and the supply voltage rises above the HCPL-/J V UVLO+ threshold (. < V UVLO+ <.), the optocoupler will go into the high state (assuming LED is ON ) with a typical delay, UVLO TURN On Delay, of. µs. Esw ENERGY PER SWITCHING CYCLE μj Qg = nc Qg = nc Qg = nc V CC = 9 V V EE = -9 V Rg GATE RESISTANCE AV-EN

24 HCPL- (Single Channel), HCPL-J (Dual Channel) Data Sheet. Amp Output Current IGBT Gate Drive Optocoupler IPM Dead Time and Propagation Delay Specifications The HCPL-/J includes a Propagation Delay Difference (PDD) specification intended to help designers minimize dead time in their power inverter designs. Dead time is the time period during which both the high and low side power transistors (Q and Q in Figure ) are off. Any overlap in Q and Q conduction will result in large currents flowing through the power devices from the high- to the lowvoltage motor rails. To minimize dead time in a given design, the turn on of LED should be delayed (relative to the turn off of LED) so that under worst-case conditions, transistor Q has just turned off when transistor Q turns on, as shown in Figure. The amount of delay necessary to achieve this condition is equal to the maximum value of the propagation delay difference specification, PDD MAX, which is specified to be ns over the operating temperature range of C to C. Delaying the LED signal by the maximum propagation delay difference ensures that the minimum dead time is zero, but it does not tell a designer what the maximum dead time will be. The maximum dead time is equivalent to the difference between the maximum and minimum propagation delay difference specifications as shown in Figure 9. The maximum dead time for the HCPL-/J is ns (= ns ( ns)) over an operating temperature range of C to C. Note that the propagation delays used to calculate PDD and dead time are taken at equal temperatures and test conditions since the optocouplers under consideration are typically mounted in close proximity to each other and are switching identical IGBTs. Figure : Optocoupler Input to Output Capacitance Model for Unshielded Optocouplers Figure : Optocoupler Input to Output Capacitance Model for Shielded Optocouplers C LEDO C LEDP C LEDP C LEDO C LEDN C LEDN SHIELD Figure : Equivalent Circuit for Figure During Common Mode Transient + V + V SAT C LEDP I LEDP C LEDN. μf + Rg V CC = V SHIELD * THE ARROWS INDICATE THE DIRECTION OF CURRENT FLOW DURING dv CM /dt. AV-EN

25 HCPL- (Single Channel), HCPL-J (Dual Channel) Data Sheet. Amp Output Current IGBT Gate Drive Optocoupler Figure : Not Recommended Open Collector Drive Circuit Figure : Recommended LED Drive Circuit for Ultra-High CMR + V + V C LEDP C LEDP Q C LEDN C LEDN I LEDN SHIELD SHIELD Figure : Minimum LED Skew for Zero Dead Time Figure 9: Waveforms for Dead Time I LED I LED V OUT Q ON Q OFF V OUT Q ON Q OFF Q ON Q ON V OUT Q OFF V OUT Q OFF I LED I LED t PHL MAX t PHL MIN tplh MIN PDD* MAX = (t PHL - t PLH ) MAX = t PHL MAX - t PLH MIN *PDD = PROPAGATION DELAY DIFFERENCE NOTE: FOR PDD CALCULATIONS THE PROPAGATION DELAYS ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS. t PHL MAX (t PHL- t PLH ) MAX = PDD* MAX t PLH MIN t PLH MAX *PDD = PROPAGATION DELAY DIFFERENCE NOTE: FOR DEAD TIME AND PDD CALCULATIONS ALL PROPAGATION DELAYS ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS. MAXIMUM DEAD TIME (DUE TO OPTOCOUPLER) = (t PHL MAX - t PHL MIN ) + (t PLH MAX - t PLH MIN ) = (t PHL MAX - t PLH MIN ) (t PHL MIN - t PLH MAX ) = PDD* MAX PDD* MIN AV-EN

26 HCPL- (Single Channel), HCPL-J (Dual Channel) Data Sheet. Amp Output Current IGBT Gate Drive Optocoupler Figure : Under Voltage Lock Out Figure : HCPL-: Thermal Derating Curve, Dependence of Safety Limiting Value with Case Temperature per IEC/EN/DIN EN -- Figure : HCPL-J: Thermal Derating Curve, Dependence of Safety Limiting Value with Case Temperature per IEC/EN/DIN EN -- V O OUTPUT VOLTAGE V (.,.) (., 9.) (.,.) (.,.) OUTPUT POWER P S, INPUT CURRENT I S P S (mw) I S (ma) P SI POWER mw P SI OUTPUT P SI INPUT (V CC - V EE ) SUPPLY VOLTAGE V T S CASE TEMPERATURE C T S CASE TEMPERATURE C AV-EN

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