HCPL Amp Output Current, High Speed, Gate Drive Optocoupler

Transcription

1 HCPL-. Amp Output Current, High Speed, Gate Drive Optocoupler Data Sheet Lead (Pb) Free RoHS fully compliant RoHS fully compliant options available; -xxxe denotes a lead-free product Description This family of devices consists of a GaAsP LED. The LED is optically coupled to an integrated circuit with a power stage. These optocouplers are ideally suited for high frequency driving of power IGBTs and MOSFETs used in Plasma Display Panels, high performance DC/DC converters, and motor control inverter applications. Functional Diagram N/C ANODE CATHODE N/C SHIELD V CC V O V O V EE A. µf bypass capacitor must be connected between pins V CC and Ground. Features. A maximum peak output current. A minimum peak output current khz maximum switching speed High speed response: ns maximum propagation delay over temperature range kv/µs minimum Common Mode Rejection (CMR) at V CM = V Under Voltage Lock-Out protection (UVLO) with hysteresis Wide operating temperature range: C to C Wide V CC operating range: V to V ns typical pulse width distortion Safety approvals: UL approval, V rms for minute CSA approval IEC/EN/DIN EN -- approval Applications Plasma Display Panel (PDP) Distributed Power Architecture (DPA) Switch Mode Rectifier (SMR) High performance DC/DC converter High performance Switching Power Supply (SPS) High performance Uninterruptible Power Supply (UPS) Isolated IGBT/Power MOSFET gate drive CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation, which may be induced by ESD.

2 Ordering Information HCPL- is UL Recognized with Vrms for minute per UL. Part Number HCPL- RoHS Compliant Option Non RoHS Compliant -E No option Package Surface Mount Gull Wing Tape & Reel IEC/EN/DIN EN -- Quantity per tube -E - X X per tube -E - mil X X X per reel -E - DIP- X per tube -E - X X X X per tube -E - X X X X per reel To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. Example : HCPL--E to order product of mil DIP Gull Wing Surface Mount package in Tape and Reel packaging with IEC/EN/DIN EN -- Safety Approval in RoHS compliant. Example : HCPL- to order product of mil DIP package in tube packaging and non RoHS compliant. Option datasheets are available. Contact your Avago sales representative or authorized distributor for information. Remarks: The notation #XXX is used for existing products, while (new) products launched since th July and RoHS compliant option will use -XXXE. Package Outline Drawings HCPL- Standard DIP Package TYPE NUMBER 9. ±. (. ±.) A XXXXZ OPTION CODE* DATE CODE. ±. (. ±.). ±. (. ±.) YYWW.9 (.) MAX.. (.) MAX.. ±. (. ±.). (.) MAX. TYP (. +.) -.). ±. (. ±.).9 (.) MIN.. (.) MAX.. ±. (. ±.). (.) MIN. DIMENSIONS IN MILLIMETERS AND (INCHES). * MARKING CODE LETTER FOR OPTION NUMBERS "V" = OPTION OPTION NUMBERS AND NOT MARKED. NOTE: FLOATING LEAD PROTRUSION IS. mm ( mils) MAX.

3 HCPL- Gull Wing Surface Mount Option 9. ±. (. ±.) LAND PATTERN RECOMMENDATION. (.). ±. (. ±.).9 (.). (.). (.).9 (.) MAX.. (.) MAX.. ±. (. ±.) 9. ±. (. ±.). ±. (. ±.) (. +.) -.). ±. (. ±.). (.) BSC DIMENSIONS IN MILLIMETERS (INCHES). LEAD COPLANARITY =. mm (. INCHES).. ±. (. ±.) NOTE: FLOATING LEAD PROTRUSION IS. mm ( mils) MAX.. ±. (. ±.) NOM. Solder Reflow Temperature Profile TEMPERATURE ( C) PREHEATING RATE C + C/. C/SEC. REFLOW HEATING RATE. C ±. C/SEC. C C C C + C/. C. C ±. C/SEC. PREHEATING TIME C, 9 + SEC. PEAK TEMP. C SEC. SEC. SEC. PEAK TEMP. C SOLDERING TIME C PEAK TEMP. C ROOM TEMPERATURE TIME (SECONDS) TIGHT TYPICAL LOOSE Note: Non-halide flux should be used.

4 Recommended Pb-Free IR Profile TEMPERATURE T p T L T smax T smin C RAMP-UP C/SEC. MAX. - C t s PREHEAT to SEC. t C to PEAK +/- C - SEC. RAMP-DOWN C/SEC. MAX. to SEC. TIME NOTES: THE TIME FROM C to PEAK TEMPERATURE = MINUTES MAX. T smax = C, T smin = C Note: Non-halide flux should be used. t p t L TIME WITHIN C of ACTUAL PEAK TEMPERATURE Regulatory Information The HCPL- has been approved by the following organizations: IEC/EN/DIN EN -- Approved under: IEC --:99 + A: EN --: + A: DIN EN -- (VDE Teil ):- (Option only) UL Approval under UL, component recognition program up to V ISO = Vrms. File E. CSA Approval under CSA Component Acceptance Notice #, File CA. IEC/EN/DIN EN -- Insulation Characteristics (HCPL- Option ) Description Symbol HCPL- Unit Installation classification per DIN EN 99- for rated mains voltage V rms for rated mains voltage V rms for rated mains voltage V rms I - IV I - III I-II Climatic Classification // Pollution Degree (DIN EN 99-) Maximum Working Insulation Voltage V IORM V peak Input to Output Test Voltage, Method b* V IORM x.=v PR, % Production Test with V PR V peak t m = sec, Partial Discharge < pc Input to Output Test Voltage, Method a* V IORM x.=v PR, Type and Sample Test, t m = sec, V PR 9 V peak Partial Discharge < pc Highest Allowable Overvoltage V IOTM V peak (Transient Overvoltage t ini = sec) Safety-limiting values maximum values allowed in the event of a failure. Case Temperature T S C Input Current** I S,INPUT ma Output Power** P S, OUTPUT mw Insulation Resistance at T S, V IO = V R S > 9 Ω * Refer to the optocoupler section of the Isolation and Control Components Designer s Catalog, under Product Safety Regulations section IEC/ EN/DIN EN -- for a detailed description of Method a and Method b partial discharge test profiles. ** Refer to the following figure for dependence of P S and I S on ambient temperature.

5 OUTPUT POWER P S, INPUT CURRENT I S P S (mw) I S (ma) T S CASE TEMPERATURE C Insulation and Safety Related Specifications Parameter Symbol HCPL- Units Conditions Minimum External Air Gap L(). mm Measured from input terminals to output (Clearance) terminals, shortest distance through air. Minimum External Tracking L(). mm Measured from input terminals to output (Creepage) terminals, shortest distance path along body. Minimum Internal Plastic Gap. mm Through insulation distance conductor to (Internal Clearance) conductor, usually the straight line distance thickness between the emitter and detector. Tracking Resistance CTI > V DIN IEC /VDE Part (Comparative Tracking Index) Isolation Group IIIa Material Group (DIN VDE, /9, Table ) Note: Option surface mount classification is Class A in accordance with CECC. Absolute Maximum Ratings Parameter Symbol Min. Max. Units Note Storage Temperature T S - C Junction Temperature T J - C Average Input Current I F(AVG) ma Peak Transient Input Current I F(TRAN). A (< µs pulse width, pps) Reverse Input Voltage V R V High Peak Output Current I OH(PEAK). A Low Peak Output Current I OL(PEAK). A Supply Voltage V CC -V EE -. V Output Voltage V O(PEAK) V CC V Output Power Dissipation P O mw Total Power Dissipation P T 9 mw Lead Solder Temperature Solder Reflow Temperature Profile C for sec.,. mm below seating plane See Package Outline Drawings section

6 Recommended Operating Conditions Parameter Symbol Min. Max. Units Note Power Supply V CC -V EE V Input Current (ON) I F(ON) ma Input Voltage (OFF) V F(OFF) -.. V Operating Temperature T A - C Electrical Specifications (DC) Over recommended operating conditions unless otherwise specified. Test Parameter Symbol Min. Typ. Max. Units Conditions Fig. Note High Level Output Current I OH. A V O = V CC -,,. A V O = V CC -,, Low Level Output Current I OL. A V O = V EE +.,,. A V O = V EE +,, High Level Output Voltage V OH V CC - V I O = - ma,, 9, Low Level Output Voltage V OL. V I O = ma,, High Level Supply Current I CCH.. ma Output Open, I F = to ma Low Level Supply Current I CCL.. ma Output Open, V F =. to. ma Threshold Input Current I FLH. ma Low to High I O = ma, 9,, Threshold Input Voltage V FHL. V V O > V High to Low Input Forward Voltage V F... V I F = ma Temperature Coefficient of DV F /DT A. mv/ C I F = ma Input Forward Voltage UVLO Threshold V UVLO+.9 V I F = ma, V UVLO. V V O > V, UVLO Hysteresis UVLO HYST. V Input Reverse Breakdown BV R V I R = µa Voltage Input Capacitance C IN pf f = MHz, V F = V

7 Switching Specifications (AC) Over recommended operating conditions unless otherwise specified. Test Parameter Symbol Min. Typ. Max. Units Conditions Fig. Note Propagation Delay Time to t PLH ns,, High Output Level I F = ma,,, Propagation Delay Time to t PHL ns R g = Ω,, Low Output Level f = khz, Pulse Width Distortion PWD ns Duty Cycle = %, Propagation Delay PDD -9 9 ns C g = nf, Difference Between Any (t PHL- t PLH ) Two Parts or Channels Rise Time t r ns CL = nf, Fall Time t f ns R g = Ω UVLO turn On Delay t UVLO ON. µs UVLO turn Off Delay t UVLO OFF. µs Output High Level Common CM H kv/µs T A = C,, Mode Transient Immunity I F = to ma, Output Low Level Common CM L kv/µs V CM =. kv,, Mode Transient Immunity V CC = V Package Characteristics Test Parameter Symbol Min. Typ. Max. Units Conditions Fig. Note Input-Output Momentary V ISO Vrms T A = C,,9 Withstand Voltage RH < % Input-Output Resistance R I-O [] Ω V I-O = V 9 Input-Output Capacitance C I-O pf Freq = MHz Notes:. Derate linearly above + C free air temperature at a rate of. ma/ C.. Maximum pulse width = µs, maximum duty cycle =.%. This value is intended to allow for component tolerances for designs with IO peak minimum =. A. See Application section for additional details on limiting IOL peak.. Derate linearly above + C, free air temperature at the rate of. mw/ C.. Derate linearly above + C, free air temperature at the rate of. mw/ C. The maximum LED junction temperature should not exceed + C.. Maximum pulse width = µs, maximum duty cycle =.%.. In this test, V OH is measured with a dc load current. When driving capacitive load V OH will approach V CC as I OH approaches zero amps.. Maximum pulse width = ms, maximum duty cycle = %.. In accordance with UL, each optocoupler is proof tested by applying an insulation test voltage > V rms for second (leakage detection current limit I I-O < µa). 9. Device considered a two-terminal device: pins on input side shorted together and pins on output side shorted together.. PWD is defined as t PHL - t PLH for any given device.. Pin and need to be connected to LED common.. Common mode transient immunity in the high state is the maximum tolerable dv CM /dt of the common mode pulse V CM to assure that the output will remain in the high state (i.e. V O >. V).. Common mode transient immunity in a low state is the maximum tolerable dv CM /dt of the common mode pulse, V CM, to assure that the output will remain in a low state (i.e. V O <. V).. t PHL propagation delay is measured from the % level on the falling edge of the input pulse to the % level of the falling edge of the V O signal. t PLH propagation delay is measured from the % level on the rising edge of the input pulse to the % level of the rising edge of the V O signal.. The difference between t PHL and t PLH between any two HCPL- parts under same test conditions.

8 (V OH V CC ) HIGH OUTPUT VOLTAGE DROP V I F = to ma I OUT = - ma V CC = to V V EE = V I OH OUTPUT HIGH CURRENT A I F = to ma V OUT = (V CC - V) V CC = to V V EE = V (V OH V CC ) OUTPUT HIGH VOLTAGE DROP V I F = to ma V CC = to V V EE = V C C - C T A TEMPERATURE C T A TEMPERATURE C I OH OUTPUT HIGH CURRENT A Figure. V OH vs. temperature. Figure. I OH vs. temperature. Figure. V OH vs. I OH. V OL OUTPUT LOW VOLTAGE V V F (OFF) = -. TO. V I OUT = ma V CC = TO V V EE = V T A TEMPERATURE C I OL OUTPUT LOW CURRENT A V F (OFF) = -. TO. V V OUT =. V V CC = TO V V EE = V T A TEMPERATURE C V OL OUTPUT LOW VOLTAGE V C C C. V F(OFF) = -. to. V V CC = to V V EE = V... I OL OUTPUT LOW CURRENT A. Figure. V OL vs. temperature. Figure. I OL vs. temperature. Figure. V OL vs. I OL. I CC SUPPLY CURRENT ma V CC = V V EE = V I F = ma for I CCH I F = ma for I CCL - T A TEMPERATURE C I CCH I CCL I CC SUPPLY CURRENT ma V CC SUPPLY VOLTAGE V I CCH I CCL I F = ma for I CCH I F = ma for I CCL T A = C V EE = V I FLH LOW TO HIGH CURRENT THRESHOLD ma - - V CC = to V V EE = V OUTPUT = OPEN T A TEMPERATURE C Figure. I CC vs. temperature. Figure. I CC vs. V CC. Figure 9. I FLH vs. temperature.

9 t p PROPAGATION DELAY ns I F = ma T A = C R g = Ω C g = nf DUTY CYCLE = % f = khz t PHL t PLH t p PROPAGATION DELAY ns V CC = V, V EE = V R g = Ω, C g = nf T A = C f = khz DUTY CYCLE = % t PLH t PHL t p PROPAGATION DELAY ns - I F = ma V CC = V, V EE = V R g = Ω, C g = nf f = khz DUTY CYCLE = % - t PHL t PLH V CC SUPPLY VOLTAGE V I F FORWARD LED CURRENT ma T A TEMPERATURE C Figure. Propagation delay vs. V CC. Figure. Propagation delay vs. I F. Figure. Propagation delay vs. temperature. t p PROPAGATION DELAY ns I F = ma T A = C f = khz C g = nf DUTY CYCLE = % t PLH t PHL R g SERIES LOAD RESISTANCE Ω t p PROPAGATION DELAY ns I F = ma T A = C Rg = Ω f = khz C g = nf DUTY CYCLE = % t PHL t PLH C g LOAD CAPACITANCE nf V O OUTPUT VOLTAGE V I F FORWARD LED CURRENT ma Figure. Propagation delay vs. R g. Figure. Propagation delay vs. C g. Figure. Transfer characteristics. T A = C I F FORWARD CURRENT ma... V F + I F V F FORWARD VOLTAGE VOLTS. Figure. Input current vs. forward voltage. 9

10 I F = to ma. µf I OH V/ V CC = to V. µf I OL. V/ V V CC = to V Figure. I OH test circuit. Figure. I OL test circuit. I F = to ma. µf. µf V OH ma V CC = to V V OL ma V CC = to V Figure 9. V OH test circuit. Figure. V OL test circuit.. µf. µf I F + V O > V V CC = to V I F = ma + V O > V V CC Figure. I FLH test circuit. Figure. UVLO test circuit.

11 I F = to ma. µf I F KHz % DUTY CYCLE Ω + V O Ω V CC = V t r t f 9% % nf V OUT % t PLH t PHL Figure. t PLH, t PHL, t r and t f test circuit and waveform. V CM V I F A + B. µf V O V CC = V V t δv V CM = δt t V O V OH SWITCH AT A: I F = ma V O V OL + V CM = V SWITCH AT B: I F = ma Figure. CMR test circuit and waveform. Applications Information Eliminating Negative IGBT Gate Drive To keep the IGBT firmly off, the HCPL- has a very low maximum V OL specification of. V. The HCPL- realizes the very low V OL by using a DMOS transistor with W (typical) on resistance in its pull down circuit. When the HCPL- is in the low state, the IGBT gate is shorted to the emitter by R g + W. Minimizing R g and the lead inductance from the HCPL- to the IGBT gate and emitter (possibly by mounting HCPL- on a small PC board directly above the IGBT) can eliminate the need for negative IGBT gate drive in many applications as shown in Figure. Care should be taken with such a PC board design to avoid routing the IGBT collector or emitter traces close to the HCPL- input as this can result in unwanted coupling of transient signals into the input of HCPL- and degrade performance. (If the IGBT drain must be routed near the HCPL- input, then the LED should be reverse biased when in the off state to prevent the transient signals coupled from the IGBT drain from turning on the HCPL-.) + V Ω. µf V CC = V + HVDC Rg CONTROL INPUT Q -PHASE AC XXX OPEN COLLECTOR Q - HVDC Figure. Recommended LED drive and application circuit for HCPL-.

12 Selecting the Gate Resistor (R g ) for HCPL- Step : Calculate R g minimum from the I OL peak specification. The IGBT and R g in Figure can be analyzed as a simple RC circuit with a voltage supplied by the HCPL-. R g V CC V OL I OLPEAK = =. Ω The V OL value of V in the previous equation is the V OL at the peak current of A. (See Figure.) Step : Check the HCPL- power dissipation and increase R g if necessary. The HCPL- total power dissipation (P T ) is equal to the sum of the emitter power (P E ) and the output power (P O ). Esw ENERGY PER SWITCHING CYCLE µj Q g = nc R g GATE RESISTANCE Ω Figure. Energy dissipated in the HCPL- and for each IGBT. PT = PE + PO PE = IF * VF * Duty Cycle PO = PO(BIAS) + PO(SWITCHING) = ICC * VCC + ESW (R g ;Q g ) * f For the circuit in Figure with IF (worst case) = ma, R g = Ω, Max Duty Cycle = %, Q g = nc, f = khz and T AMAX = + C: PE = ma *. V *. = mw PO =. ma * V +. µ * khz = mw mw C = mw ( C *. mw/ C)) The value of. ma for I CC in the previous equation was obtained by derating the I CC max of ma to I CC max at + C. Since P O for this case is greater than the P O(MAX), R g must be increased to reduce the HCPL- power dissipation. PO(SWITCHING MAX) = PO(MAX) PO(BIAS) = mw 9 mw = mw ESW(MAX) = PO(SWITCHING MAX) f = mw khz =. µw For Q g = nc, a value of E sw =. µw gives a R g = W.

13 Thermal Model (Discussion applies to HCPL-) The steady state thermal model for the HCPL- is shown in Figure. The thermal resistance values given in this model can be used to calculate the temperatures at each node for a given operating condition. As shown by the model, all heat generated flows through q CA which raises the case temperature TC accordingly. The value of q CA depends on the conditions of the board design and is, therefore, determined by the designer. The value of q CA = + C/W was obtained from thermal measurements using a. x. inch PC board, with small traces (no ground plane), a single HCPL- soldered into the center of the board and still air. The absolute maximum power dissipation derating specifications assume a q CA value of + C/W. From the thermal mode in Figure, the LED and detector IC junction temperatures can be expressed as: T JE = P E * (q LC //q LD + q DC ) + q CA ) + P D * [ q LC * q DC + q CA ] + T q A LC + q DC + q LD q T JD = P E * [ LC * q DC + q CA ] + P D * (q LC //q LD + q DC ) + q CA ) + T q A LC + q DC + q LD T JE θ LC = C/W θ LD = C/W T JD θ DC = C/W T C θ CA = C/W* T A T JE = LED JUNCTION TEMPERATURE T JD = DETECTOR IC JUNCTION TEMPERATURE T C = CASE TEMPERATURE MEASURED AT THE CENTER OF THE PACKAGE BOTTOM θ LC = LED-TO-CASE THERMAL RESISTANCE θ LD = LED-TO-DETECTOR THERMAL RESISTANCE θ DC = DETECTOR-TO-CASE THERMAL RESISTANCE θ CA = CASE-TO-AMBIENT THERMAL RESISTANCE *θ CA WILL DEPEND ON THE BOARD DESIGN AND THE PLACEMENT OF THE PART. Figure. Thermal model. T JE = P E * ( C/W + q CA ) + P D * ( C/W + q CA ) + T A T JD = P E * ( C/W + q CA ) + P D * ( C/W + q CA ) + T A For example, given P E = mw, P O = mw, T A = + C and q CA = + C/W: T JE = P E * 9 C/W + P D * C/W + T A = mw * 9 C/W + mw * C/W + C = C T JD = P E * C/W + P D * 9 C/W + T A = mw * C/W + mw * 9 C/W + C = C T JE and T JD should be limited to + C based on the board layout and part placement (q CA ) specific to the application.

14 LED Drive Circuit Considerations for Ultra High CMR Performance Without a detector shield, the dominant cause of optocoupler CMR failure is capacitive coupling from the input side of the optocoupler, through the package, to the detector IC as shown in Figure. The HCPL- improves CMR performance by using a detector IC with an optically transparent Faraday shield, which diverts the capacitively coupled current away from the sensitive IC circuitry. However, this shield does not eliminate the capacitive coupling between the LED and optocoupler pins - as shown in Figure 9. This capacitive coupling causes perturbations in the LED current during common mode transients and becomes the major source of CMR failures for a shielded optocoupler. The main design objective of a high CMR LED drive circuit becomes keeping the LED in the proper state (on or off ) during common mode transients. For example, the recommended application circuit (Figure ), can achieve kv/µs CMR while minimizing component complexity. Techniques to keep the LED in the proper state are discussed in the next two sections. CMR with the LED On (CMR H ) A high CMR LED drive circuit must keep the LED on during common mode transients. This is achieved by over-driving the LED current beyond the input threshold so that it is not pulled below the threshold during a transient. A minimum LED current of ma provides adequate margin over the maximum I FLH of ma to achieve kv/µs CMR. + V + V SAT C LEDP I LEDP C LEDN SHIELD * THE ARROWS INDICATE THE DIRECTION OF CURRENT FLOW DURING dv CM /dt. V CM. µf + V CC = V R g Figure. Equivalent circuit for Figure during common mode transient. C LEDP C LEDN Figure. Optocoupler input to output capacitance model for unshielded optocouplers. C LEDP C LEDN C LEDO SHIELD C LEDO CMR with the LED Off (CMR L ) A high CMR LED drive circuit must keep the LED off (V F V F(OFF) ) during common mode transients. For example, during a -dv CM /dt transient in Figure, the current flowing through C LEDP also flows through the R SAT and V SAT of the logic gate. As long as the low state voltage developed across the logic gate is less than V F(OFF), the LED will remain off and no common mode failure will occur. The open collector drive circuit, shown in Figure, cannot keep the LED off during a +dv CM /dt transient, since all the current flowing through C LEDN must be supplied by the LED, and it is not recommended for applications requiring ultra high CMR L performance. Figure is an alternative drive circuit, which like the recommended application circuit (Figure ), does achieve ultra high CMR performance by shunting the LED in the off state. Figure 9. Optocoupler input to output capacitance model for shielded optocouplers.

15 + V + V C LEDP C LEDP Q C LEDN C LEDN I LEDN SHIELD SHIELD Figure. Not recommended open collector drive circuit. Figure. Recommended LED drive circuit for ultra-high CMR. Under Voltage Lockout Feature The HCPL- contains an under voltage lockout (UVLO) feature that is designed to protect the IGBT under fault conditions which cause the HCPL- supply voltage (equivalent to the fully charged IGBT gate voltage) to drop below a level necessary to keep the IGBT in a low resistance state. When the HCPL- output is in the high state and the supply voltage drops below the HCPL- V UVLO- threshold (typ. V) the optocoupler output will go into the low state. When the HCPL- output is in the low state and the supply voltage rises above the HCPL- V UVLO+ threshold (typ. V) the optocoupler output will go into the high state (assume LED is ON ). IPM Dead Time and Propagation Delay Specifications The HCPL- includes a Propagation Delay Difference (PDD) specification intended to help designers minimize dead time in their power inverter designs. Dead time is the time during which the high and low side power transistors are off. Any overlap in Q and Q conduction will result in large currents flowing through the power devices from the high voltage to the low-voltage motor rails. To minimize dead time in a given design, the turn on of LED should be delayed (relative to the turn off of LED) so that under worst-case conditions, transistor Q has just turned off when transistor Q turns on, as shown in Figure. The amount of delay necessary to achieve this condition is equal to the maximum value of the propagation delay difference specification, PDD MAX, which is specified to be 9 ns over the operating temperature range of - C to + C. I LED V OUT Q ON Q OFF V O OUTPUT VOLTAGE V V OUT I LED Q OFF t PHL MAX tplh MIN Q ON PDD* MAX = (t PHL - t PLH ) MAX = t PHL MAX - t PLH MIN (V CC - V EE ) SUPPLY VOLTAGE V *PDD = PROPAGATION DELAY DIFFERENCE NOTE: FOR PDD CALCULATIONS, THE PROPAGATION DELAYS ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS. Figure. Under voltage lock out. Figure. Minimum LED skew for zero dead time.

16 Delaying the LED signal by the maximum propagation delay difference ensures that the minimum dead time is zero, but it does not tell a designer what the maximum dead time will be. The maximum dead time is equivalent to the difference between the maximum and minimum propagation delay difference specification as shown in Figure. The maximum dead time for the HCPL- is ns (= 9 ns-(- 9 ns)) over the operating temperature range of C to + C. Note that the propagation delays used to calculate PDD and dead time are taken at equal temperatures and test conditions since the optocouplers under consideration are typically mounted in close proximity to each other and are switching identical IGBTs. I LED V OUT Q ON Q OFF V OUT Q OFF Q ON I LED t PHL MIN t PHL MAX t PLH MIN t PLH MAX (t PHL- t PLH ) MAX PDD* MAX MAXIMUM DEAD TIME (DUE TO OPTOCOUPLER) = (t PHL MAX - t PHL MIN ) + (t PLH MAX - t PLH MIN ) = (t PHL MAX - t PLH MIN ) (t PHL MIN - t PLH MAX ) = PDD* MAX PDD* MIN *PDD = PROPAGATION DELAY DIFFERENCE NOTE: FOR DEAD TIME AND PDD CALCULATIONS, ALL PROPAGATION DELAYS ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS. Figure. Waveforms for dead time. For product information and a complete list of distributors, please go to our website: Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright -9 Avago Technologies. All rights reserved. AV-EN - March, 9