HCPL-5300, HCPL-5301, HCPL-530K,

Transcription

1 HCPL-00, HCPL-0, HCPL-0K, 9-9 Intelligent Power Module and Gate Drive Interface Hermetically Sealed Optocouplers Description The HCPL-0x devices consist of a GaAsP LED optically coupled to an integrated high gain photo detector in a hermetically sealed package. The products are capable of operation and storage over the full military temperature range and can be purchased as either commercial product or with full MIL-PRF- Class Level H or K testing or from the DLA Standard Microcircuit Drawing (SMD) 9-9. All devices are manufactured and tested on a MIL-PRF- certified line, and Class H and K devices are included in the DLA Qualified Manufacturers List QML- for Hybrid Microcircuits. Minimized propagation delay difference between devices makes these optocouplers excellent solutions for improving inverter efficiency through reduced switching dead time. An on-chip 0-kΩ output pull-up resistor can be enabled by shorting output pins and, thus eliminating the need for an external pull-up resistor in common IPM applications. Specifications and performance plots are given for typical IPM applications. Features Performance specified over full military temperature Range: C to + C Fast maximum propagation delays = 0 ns = 0 ns Minimized pulse width distortion (PWD = 0 ns) High common mode rejection (CMR): 0 kv/μs at V CM = 000V CTR > 0% at I F = 0 ma 00 Vdc withstand test voltage Manufactured and tested on a MIL-PRF- certified line Hermetically sealed packages Dual marked with device part number and DLA Standard Microcircuit Drawing (SMD) QML-, Class H and K HCPL-0 function compatibility CAUTION It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD. Applications Military and space High reliability systems Harsh industrial environments Transportation, medical, and life critical systems IPM isolation Isolated IGBT/MOSFET gate drive AC and brushless DC motor drives Industrial inverters. See Selection Guide Lead Configuration Options for available extensions. - -

2 Schematic Diagram Schematic Diagram LED ON OFF NOTE Truth Table V O L H 0 k The connection of a 0.-μF bypass capacitor between pins and is recommended. Selection Guide Lead Configuration Options Part Numbers and Options Commercial HCPL-00 MIL-PRF-, Class H HCPL-0 MIL-PRF-, Class K HCPL-0K Standard Lead Finish a Gold Plate Solder Dipped b Option #00 Butt Cut/Gold Plate a Option #00 Gull Wing/Soldered b Option #00 Class H SMD Part # Prescript for all below 9- Gold Plate a 90HPC Solder Dipped b 90HPA Butt Cut/Gold Plate a 90HYC Butt Cut/Soldered b 90HYA Gull Wing/Soldered b 90HXA Class K SMD Part # Prescript for all below 9- Gold Plate a 90KPC Solder Dipped b 90KPA Butt Cut/Gold Plate a 90KYC Butt Cut/Soldered b 90KYA Gull Wing/Soldered b 90KXA a. Gold Plate lead finish: Maximum gold thickness of leads is <00 micro inches. Typical is 0 to 90 micro inches. b. Solder lead finish: Sn/Pb. Outline Drawing -Pin DIP, Through Hole, Channel 0.0 (0.9) 0.9 (0.0).0 (0.00). (0.00). (0.0). (0.). (0.9). (0.0) 0. (0.00) MIN.. (0.0) MIN. 0.0 (0.00) 0. (0.0).9 (0.090).9 (0.0) 0. (0.00) NOTE: DIMENSIONS IN MILLIMETERS (INCHES).. (0.90). (0.0) - -

3 Device Marking Device Marking Avago DESIGNATOR Avago P/N DLA SMD [] DLA SMD [] PIN ONE/ ESD IDENT A QYYWWZ XXXXXX XXXXXXX XXX XXX 0 COMPLIANCE INDICATOR, [] DATE CODE, SUFFIX (IF NEEDED) COUNTRY OF MFR. Avago CAGE CODE [] [] QML PARTS ONLY Hermetic Optocoupler Options Option Description 00 Surface-mountable hermetic optocoupler with leads trimmed for butt joint assembly. This option is available on Commercial, Class H and Class K product in -pin DIP.. (0.0) 0. (0.00) MIN..9 (0.090).9 (0.0). (0.0).0 (0.0) 0. (0.00) NOTE: DIMENSIONS IN MILLIMETERS (INCHES). 0.0 (0.00) 0. (0.0). (0.90). (0.0) 00 Lead finish is solder dipped rather than gold plated. This option is available on Commercial, Class H and Class K product in -pin DIP. DLA Drawing (SMD) part numbers contain provisions for lead finish. 00 Surface-mountable hermetic optocoupler with leads cut and bent for gull wing assembly. This option is available on Commercial, Class H and Class K product in -pin DIP. This option has solder-dipped leads.. (0.0). (0.0) 0. (0.00) MIN..9 (0.090).9 (0.0).0 (0.0). (0.0) 0. (0.00) 0.0 (0.00) 0. (0.0) 9. (0.0) 9.9 (0.90).0 (0.0). (0.0) NOTE: DIMENSIONS IN MILLIMETERS (INCHES). - -

4 Absolute Maximum Ratings Absolute Maximum Ratings Parameter Symbol Min Max Unit Storage Temperature T S +0 C Operating Temperature T A + C Junction Temperature T J + C Lead Solder Temperature 0 for 0 sec C Average Input Current I F(AVG) ma Peak Input Current (0% duty cycle, μs pulse width) I F(PEAK) 0 ma Peak Transient Input Current ( μs pulse width, 00 pps).0 A Reverse Input Voltage (Pin -) V R V Average Output Current (Pin ) I O(AVG) ma Resistor Voltage (Pin ) V 0. V CC V Output Voltage (Pin -) V O 0. 0 V Supply Voltage (Pin -) V CC 0. 0 V Output Power Dissipation P O 00 mw Total Power Dissipation P T mw ESD Classification (MIL-STD-, Method 0), Class Recommended Operating Conditions Parameter Symbol Min Max Unit Power Supply Voltage V CC. 0 V Output Voltage V O 0 0 V Input Current (ON) I F(ON) 0 0 ma Input Voltage (OFF) V F(OFF) 0. V - -

5 Electrical Specifications Electrical Specifications Over recommended operating conditions (T A = C to + C, V CC = +.V to 0V, I F(ON) = 0 ma to 0 ma, V F(OFF) = V to 0.V) unless otherwise specified. Parameter Symbol Group A Subgroups a Min Typ b Max Unit Test Conditions Fig Note Current Transfer Ratio CTR,, 0 90 % I F = 0 ma, V O = 0.V c Low Level Output Current I OL,, ma I F = 0 ma, V O = 0.V, Low Level Output Voltage V OL,, V I O =. ma Input Threshold Current I TH,,..0 ma V O = 0.V, I O = 0. ma d High Level Output Current I OH,, μa V F = 0.V High Level Supply Current I CCH,, 0.. ma V F = 0.V, V O = Open Low Level Supply Current I CCL,, 0.. ma I F = 0 ma, V O = Open d d Input Forward Voltage V F,,.0.. V I F = 0 ma Temperature Coefficient of ΔV F /ΔT A. mv/ C I F = 0 ma Forward Voltage Input Reverse Breakdown BV R,, V I R = 00 μa Voltage Input Capacitance C IN 90 pf f = MHz, V F = 0V Input-Output Insulation Leakage Current I I-O.0 μa RH %, t = sec, V I-O = 00 Vdc, T A = C e Resistance (Input-Output) R I-O 0 Ω V I-O = 00 Vdc e Capacitance (Input-Output) C I-O. pf f = MHz e Internal Pull-up Resistor R L 0 kω T A = C f, g, h Internal Pull-up Resistor Temperature Coefficient ΔR L /ΔT A 0.0 kω/ C a. Commercial parts receive 00% testing at C (Subgroups and 9). SMD, Class H and K parts receive 00% testing at C, + C, and C (Subgroups and 9, and 0, and respectively). b. All typical values at C, V CC = V. c. Current Transfer Ratio in percent is defined as the ratio of output collector current (I O ) to the forward LED input current (I F ) times 00. d. Use of a 0. μf bypass capacitor connected between pins and can improve performance by filtering power supply line noise. e. Device considered a two-terminal device: Pins,,, and shorted together and Pins,,, and shorted together. f. The internal 0 kω resistor can be used by shorting pins and together. g. Due to the tolerance of the internal resistor, and since propagation delay is dependent on the load resistor value, performance can be improved by using an external 0 kω % load resistor. For more information on how propagation delay varies with load resistance, see Figure. h. The RL = 0 kω, C L = 00 pf represents a typical IPM (Intelligent Power Module) load. - -

6 Switching Specifications (R L = 0 kω External) Switching Specifications (R L = 0 kω External) Over recommended operating conditions (T A = C to + C, V CC = +.V to 0V, I F(ON) = 0 ma to 0 ma, V F(OFF) = V to 0.V) unless otherwise specified. Parameter Propagation Delay Time to Low Output Level Propagation Delay Time to High Output Level Symbol Group A Subgroups a Min Typ b Max Unit Test Conditions Fig Note 9, 0, ns C L = 00 pf I F(on) = 0 ma, V F(off) = 0.V, 00 ns C L = 0 pf V CC =.0V, 9, 0, ns ns C L = 00 pf C L = 0 pf V THLH =.0V, V THHL =.V,, 9,- c, d, e, f, g Pulse Width Distortion PWD 9, 0, 0 0 ns C L = 00 pf h Propagation Delay Difference Between Any Two Parts Output High Level Common Mode Immunity Transient Output Low Level Common Mode Transient Immunity - 9, 0, ns i CM H 9 0 kv/µs I F = 0 ma, V O >.0V CM L 9 0 kv/µs I F = 0 ma V O <.0V V CC =.0V, C L = 00 pf, V CM = 000 V P-P T A = C,,, j, k l, k a. Commercial parts receive 00% testing at C (Subgroups and 9). SMD, Class H and K parts receive 00% testing at C, + C, and C (Subgroups and 9, and 0, and respectively). b. All typical values at C, V CC = V. c. Pulse: f = 0 khz, Duty Cycle = 0%. d. The internal 0 kω resistor can be used by shorting pins and together. e. Due to the tolerance of the internal resistor, and since propagation delay is dependent on the load resistor value, performance can be improved by using an external 0 kω % load resistor. For more information on how propagation delay varies with load resistance, see Figure. f. The R L = 0 kω, C L = 00 pf represents a typical IPM (Intelligent Power Module) load. g. Use of a 0.-μF bypass capacitor connected between pins and can improve performance by filtering power supply line noise. h. Pulse Width Distortion (PWD) is defined as the difference between and for any given device. i. The difference in and between any two parts under the same test condition. (See IPM Dead Time and Propagation Delay Specifications.) j. Common mode transient immunity in a Logic High level is the maximum tolerable dv CM /dt of the common mode pulse, V CM, to assure that the output remains in a Logic High state (i.e., V O >.0V). k. Parameters are tested as part of device initial characterization and after design and process changes. Parameters are guaranteed to limits specified for all lots not specifically tested. l. Common mode transient immunity in a Logic Low level is the maximum tolerable dv CM /dt of the common mode pulse, V CM, to assure that the output remains in a Logic Low state (i.e., V O <.0V). - -

7 Switching Specifications (R L = Internal Pull-up) Switching Specifications (R L = Internal Pull-up) Over recommended operating conditions (T A = C to + C, V CC = +.V to 0V, I F(ON) = 0 ma to 0 ma, V F(OFF) = V to 0.V) unless otherwise specified. Parameter Propagation Delay Time to Low Output Level Propagation Delay Time to High Output Level Symbol Group A Subgroups a Min Typ b Max Unit Test Conditions Fig Note 9, 0, 9, 0, ns ns I F(on) = 0 ma, V F(off) = 0.V, V CC =.0V, C L = 00 pf, V THLH =.0V, c, d, e, f, g - 9, 0, 0 0 ns V THHL =.V i Pulse Width Distortion PWD 9, 0, 0 00 ns h Propagation Delay Difference Between Any Two Parts Output High Level Common Mode Transient Immunity Output Low Level Common Mode Transient Immunity CM H 0 kv/µs I F = 0 ma, V O >.0V CM L 0 kv/µs I F = ma V O <.0V V CC =.0V, C L = 00 pf, V CM = 000 V P-P T A = C Power Supply Rejection PSR.0 V P-P Square Wave, t RISE, t FALL > ns, no bypass capacitors. a. Commercial parts receive 00% testing at C (Subgroups and 9). SMD, Class H and K parts receive 00% testing at C, + C, and C (Subgroups and 9, and 0, and respectively). b. All typical values at C, V CC = V. c. Pulse: f = 0 khz, Duty Cycle = 0%. d. The internal 0 kω resistor can be used by shorting pins and together. e. Due to the tolerance of the internal resistor, and since propagation delay is dependent on the load resistor value, performance can be improved by using an external 0 kω % load resistor. For more information on how propagation delay varies with load resistance, see Figure. f. The R L = 0 kω, C L = 00 pf represents a typical IPM (Intelligent Power Module) load. g. Use of a 0.-μF bypass capacitor connected between pins and can improve performance by filtering power supply line noise. h. Pulse Width Distortion (PWD) is defined as the difference between and for any given device. i. The difference in and between any two parts under the same test condition. (See IPM Dead Time and Propagation Delay Specifications.), j j. Common mode transient immunity in a Logic High level is the maximum tolerable dv CM /dt of the common mode pulse, V CM, to assure that the output remains in a Logic High state (i.e., V O >.0V). k. Common mode transient immunity in a Logic Low level is the maximum tolerable dv CM /dt of the common mode pulse, V CM, to assure that the output remains in a Logic Low state (i.e., V O <.0V). k g - -

8 LED Drive Circuit Considerations for Ultra High CMR Performance LED Drive Circuit Considerations for Ultra High CMR Performance Without a detector shield, the dominant cause of optocoupler CMR failure is capacitive coupling from the input side of the optocoupler, through the package, to the detector IC as shown in Figure. The HCPL-0x improves CMR performance by using a detector IC with an optically transparent Faraday shield, which diverts the capacitively coupled current away from the sensitive IC circuitry. However, this shield does not eliminate the capacitive coupling between the LED and the optocoupler output pins and output ground as shown in Figure. This capacitive coupling causes perturbations in the LED current during common mode transients and becomes the major source of CMR failures for a shielded optocoupler. The main design objective of a high CMR LED drive circuit becomes keeping the LED in the proper state (on or off) during common mode transients. For example, the recommended application circuit (Figure ), can achieve 0 kv/μs CMR while minimizing component complexity. Note that a CMOS gate is recommended in Figure to keep the LED off when the gate is in the high state. Another cause of CMR failure for a shielded optocoupler is direct coupling to the optocoupler output pins through C LEDO and C LEDO in Figure. Many factors influence the effect and magnitude of the direct coupling including the use of an internal or external output pull-up resistor, the position of the LED current setting resistor, the connection of the unused input package pins, and the value of the capacitor at the optocoupler output (CL). Techniques to keep the LED in the proper state and minimize the effect of the direct coupling are discussed in the next two sections. CMR With the LED on (CMR L ) A high CMR LED drive circuit must keep the LED on during common mode transients. This is achieved by overdriving the LED current beyond the input threshold so that it is not pulled below the threshold during a transient. The recommended minimum LED current of 0 ma provides adequate margin over the maximum I TH of.0 ma (see Figure ) to achieve 0 kv/μs CMR. Capacitive coupling is higher when the internal load resistor is used (due to C LEDO ) and an I F = ma is required to obtain 0 kv/μs CMR. The placement of the LED current setting resistor affects the ability of the drive circuit to keep the LED on during transients and interacts with the direct coupling to the optocoupler output. For example, the LED resistor in Figure is connected to the anode. Figure shows the AC equivalent circuit for Figure during common mode transients. During a +dv CM/dt in Figure, the current available at the LED anode (I TOTAL ) is limited by the series resistor. The LED current (I F ) is reduced from its DC value by an amount equal to the current that flows through C LEDP and C LEDO. The situation is made worse because the current through C LEDO has the effect of trying to pull the output high (toward a CMR failure) at the same time the LED current is being reduced. For this reason, the recommended LED drive circuit (Figure ) places the current setting resistor in series with the LED cathode. Figure is the AC equivalent circuit for Figure during common mode transients. In this case, the LED current is not reduced during a +dv CM/dt transient because the current flowing through the package capacitance is supplied by the power supply. During a dv CM/dt transient, however, the LED current is reduced by the amount of current flowing through C LEDN. But better CMR performance is achieved since the current flowing in C LEDO during a negative transient acts to keep the output low. Coupling to the LED and output pins is also affected by the connection of pins and. If CMR is limited by perturbations in the LED on current, as it is for the recommended drive circuit (Figure ), pins and should be connected to the input circuit common. However, if CMR performance is limited by direct coupling to the output when the LED is off, pins and should be left unconnected. - -

9 CMR with the LED Off (CMR H ) CMR with the LED Off (CMR H ) A high CMR LED drive circuit must keep the LED off (V F V F(OFF) ) during common mode transients. For example, during a +dv CM/dt transient in Figure, the current flowing through C LEDN is supplied by the parallel combination of the LED and series resistor. As long as the voltage developed across the resistor is less than V F(OFF), the LED remains off and no common mode failure occurs. Even if the LED momentarily turns on, the 00 pf capacitor from pins - will keep the output from dipping below the threshold. The recommended LED drive circuit (Figure ) provides about 0V of margin between the lowest optocoupler output voltage and a V IPM threshold during a 0 kv/μs transient with V CM = 000V. Additional margin can be obtained by adding a diode in parallel with the resistor, as shown by the dashed line connection in Figure, to clamp the voltage across the LED below V F(OFF). Since the open collector drive circuit, shown in Figure 9, cannot keep the LED off during a +dv CM/dt transient, it is not desirable for applications requiring ultra high CMR H performance. Figure 0 is the AC equivalent circuit for Figure during common mode transients. Essentially all the current flowing through C LEDN during a +dv CM/dt transient must be supplied by the LED. CMR H failures can occur at dv/dt rates where the current through the LED and C LEDN exceeds the input threshold. Figure is an alternative drive circuit which does achieve ultra high CMR performance by shunting the LED in the off state. IPM Dead Time and Propagation Delay Specifications These devices include a Propagation Delay Difference specification intended to help designers minimize dead time in their power inverter designs. Dead time is the time period during which both the high and low side power transistors (Q and Q in Figure ) are off. Any overlap in Q and Q conduction results in large currents flowing through the power devices between the high and low voltage motor rails. To minimize dead time, the designer must consider the propagation delay characteristics of the optocoupler as well as the characteristics of the IPM IGBT gate drive circuit. Considering only the delay characteristics of the optocoupler (the characteristics of the IPM IGBT gate drive circuit can be analyzed in the same way), it is important to know the minimum and maximum turn-on ( ) and turn-off ( ) propagation delay specifications, preferably over the desired operating temperature range. The limiting case of zero dead time occurs when the input to Q turns off at the same time that the input to Q turns on. This case determines the minimum delay between LED turn-off and LED turn-on, which is related to the worst-case optocoupler propagation delay waveforms, as shown in Figure. A minimum dead time of zero is achieved in Figure when the signal to turn on LED is delayed by (max - min ) from the LED turn off. This delay is the maximum value for the propagation delay difference specification which is specified at 00 ns for the HCPL-0x over an operating temperature range of C to + C. Delaying the LED signal by the maximum propagation delay difference ensures that the minimum dead time is zero, but it does not tell a designer what the maximum dead time will be. The maximum dead time occurs in the highly unlikely case where one optocoupler with the fastest and another with the slowest are in the same inverter leg. The maximum dead time in this case becomes the sum of the spread in the and propagation delays as shown in Figure. The maximum dead time is also equivalent to the difference between the maximum and minimum propagation delay difference specifications. The maximum dead time (due to the optocouplers) for the HCPL-0x is 0 ns (= 00 ns ( 0 ns)) over an operating temperature range of C to + C

10 IPM Dead Time and Propagation Delay Specifications Figure Typical Transfer Characteristics 0 Figure Normalized Output Current vs. Temperature.0 I O OUTPUT CURRENT ma 0 0 V O = 0. V C C - C 0 0 NORMALIZED OUTPUT CURRENT I F = 0 ma V O = 0. V I F FORWARD LED CURRENT ma T A TEMPERATURE C Figure High Level Output Current vs. Temperature Figure Input Current vs. Forward Voltage I OH HIGH LEVEL OUTPUT CURRENT A 0 0 V F = 0. V V CC = V O = 0 V T A TEMPERATURE C I F FORWARD CURRENT ma V F + I F T A = C V F FORWARD VOLTAGE VOLTS.0 Figure Propagation Delay Test Circuit I F(ON) =0 ma + V 0 k 0. μf 0 k I f + V O V CC = V V OUT t f 90% 90% t r C L * V THHL 0% 0% V THLH *TOTAL LOAD CAPACITANCE - 0 -

11 IPM Dead Time and Propagation Delay Specifications Figure CMR Test Circuit. Typical CMR Waveform B I F A 0 k 0. μf 0 k V OUT + V CC = V V CM OV t V t = V CM t 00 pf* + V FF *00 pf TOTAL CAPACITANCE V O SWITCH AT A: I F = 0 ma V O SWITCH AT B: I F = 0 ma V CC V OL + V CM = 000 V Figure Propagation Delay with External 0 kω R L vs. Temperature Figure Propagation Delay with Internal 0 kω R L vs. Temperature t P PROPAGATION DELAY ns I F = 0 ma V CC = V CL = 00 pf RL = 0 k (EXTERNAL) T A TEMPERATURE C t P PROPAGATION DELAY ns I F = 0 ma V CC = V CL = 00 pf RL = 0 k (INTERNAL) T A TEMPERATURE C Figure 9 Propagation Delay vs. Load Resistance Figure 0 Propagation Delay vs. Load Capacitance t P PROPAGATION DELAY ns I F = 0 ma V CC = V CL = 00 pf T A = C RL LOAD RESISTANCE K t P PROPAGATION DELAY ns I F = 0 ma V CC = V RL = 0 k T A = C CL LOAD CAPACITANCE pf - -

12 IPM Dead Time and Propagation Delay Specifications Figure Propagation Delay vs. Supply Voltage Figure Propagation Delay vs. Input Current t P PROPAGATION DELAY ns I F = 0 ma CL = 00 pf RL = 0 k T A = C V CC SUPPLY VOLTAGE V 0 t P PROPAGATION DELAY ns V CC = V CL = 00 pf RL = 0 k T A = C 0 0 I F FORWARD LED CURRENT ma Figure Recommended LED Drive Circuit Figure Optocoupler Input to Output Capacitance Model for Unshielded Optocouplers 0 k 0. μf 0 k + V 0 V OUT + V CC = V C LEDP 0 k CMOS 00 pf *00 pf TOTAL CAPACITANCE C LEDN Figure Optocoupler Input to Output Capacitance Model for Shielded Optocouplers Figure LED Drive Circuit with resistor Connected to LED Anode (not recommended) 0 k C LEDP C LED0 + V 0 0 k 0. μf 0 k + V CC = V C LEDN C LED0 CMOS 00 pf V OUT *00 pf TOTAL CAPACITANCE - -

13 IPM Dead Time and Propagation Delay Specifications Figure AC Equivalent Circuit for Figure During Common Mode Transients Figure AC Equivalent Circuit for Figure During Common Mode Transients I TOTAL* 00 I CLEDP C LED0 I F C LEDP I CLED0 C LEDN 0 k C LED0 V OUT 0 k 00 pf 00 + V R ** C LEDP C LED0 C LEDN I CLEDN* 0 k C LED0 V OUT 0 k 00 pf * THE ARROWS INDICATE THE DIRECTION OF CURRENT FLOW FOR +dv CM /dt TRANSIENTS. + V CM * THE ARROWS INDICATE THE DIRECTION OF CURRENT FLOW FOR +dv CM /dt TRANSIENTS. ** OPTIONAL CLAMPING DIODE FOR IMPROVED CMH PERFORMANCE. V R < V F (OFF) DURING +dv CM /dt. + V CM Figure 9 Not Recommended Open Collector LED Drive Circuit Figure 0 AC Equivalent Circuit for Figure 9 During Common Mode Transients + V 0 k C LEDP C LED0 0 k 0 k Q Q C LEDN C LED0 V OUT I CLEDN* 00 pf * THE ARROWS INDICATE THE DIRECTION OF CURRENT FLOW FOR +dv CM /dt TRANSIENTS. + V CM Figure Recommended LED Drive Circuit for Ultra High CMR + V 0 k - -

14 IPM Dead Time and Propagation Delay Specifications Figure Typical Application Circuit HCPL-0x V CC + V I LED 0 k 0. μf 0 k IPM +HV 0 V OUT CMOS Q M HCPL-0x V CC HCPL-0x Q + V I LED 0 k 0. μf 0 k HCPL-0x HCPL-0x -HV 0 V OUT HCPL-0x CMOS HCPL-0x Figure Minimum LED Skew for Zero Dead Time I LED V OUT V OUT Q ON Q OFF Q OFF Q ON I LED MIN. PDD* = (- ) = - MIN. *PDD = PROPAGATION DELAY DIFFERENCE NOTE: THE PROPAGATION DELAYS USED TO CALCULATE PDD ARE TAKEN AT EQUAL TEMPERATURES. - -

15 IPM Dead Time and Propagation Delay Specifications Figure Waveforms for Dead Time Calculations I LED V OUT V OUT Q ON Q OFF Q OFF Q ON I LED MIN. PDD* MIN. DEAD TIME MAXIMUM DEAD TIME (DUE TO OPTOCOUPLER) = ( - MIN. )+( - MIN. ) = ( - MIN. ) - ( MIN. - ) = PDD* - PDD* MIN. *PDD = PROPAGATION DELAY DIFFERENCE NOTE: THE PROPAGATION DELAYS USED TO CALCULATE THE MAXIMUM DEAD TIME ARE TAKEN AT EQUAL TEMPERATURES. - -

16 For product information and a complete list of distributors, please go to our web site: the pulse logo, Connecting everything, Avago Technologies, Avago, and the A logo are among the trademarks of in the United States, certain other countries and/or the EU. Copyright All Rights Reserved. The term "" refers to Limited and/or its subsidiaries. For more information, please visit reserves the right to make changes without further notice to any products or data herein to improve reliability, function, or design. Information furnished by is believed to be accurate and reliable. However, does not assume any liability arising out of the application or use of this information, nor the application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others. AV0-9EN January, 0