6N140A, HCPL-675x, 83024, HCPL-570x, HCPL-177K, , HCPL-573x, HCPL-673x, ,

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1 N0A, HCPL-x, 0, HCPL-0x, HCPL-K, 9-90, HCPL-x, HCPL-x, Hermetically Sealed, Low I F, Wide V CC, High Gain Optocouplers Description These units are single, dual, and quad channel, hermetically sealed optocouplers. The products are capable of operation and storage over the full military temperature range and can be purchased as either commercial product or with full MIL-PRF- Class Level H or K testing or from the appropriate DLA Standard Microcircuit Drawing (SMD). All devices are manufactured and tested on a MIL-PRF- certified line, and Class H and K devices are included in the DLA Qualified Manufacturers List QML- for Hybrid Microcircuits. Each channel contains a GaAsP light emitting diode that is optically coupled to an integrated high gain photon detector. The high gain output stage features an open collector output, providing both lower saturation voltage and higher signaling speed than possible with conventional photo-darlington optocouplers. The shallow depth and small junctions offered by the IC process provides better radiation immunity than conventional photo transistor optocouplers. The supply voltage can be operated as low as.0v without adversely affecting the parametric performance. These devices have a 00% minimum CTR at an input current of only 0. ma making them ideal for use in low input current applications such as MOS, CMOS, low power logic interfaces or line receivers. Compatibility with high-voltage CMOS logic systems is assured by specifying I CCH and I OH at Volts. CAUTION It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD.. See Selection Guide Package Styles and Lead Configuration Options for available extensions. Features Dual marked with device part number and DLA Standard Microcircuit Drawing (SMD) Manufactured and tested on a MIL-PRF- Certified Line QML-, Class H and K Five hermetically sealed package configurations Performance guaranteed over full military temperature range: C to + C Low input current requirement: 0. ma High current transfer ratio: 00% typical at I F = 0. ma Low output saturation voltage: 0.V typical 00 Vdc withstand test voltage High radiation immunity N/9, HCPL-0/ function compatibility Reliability data Applications Military and aerospace High reliability systems Microprocessor system interface Transportation, medical, and life critical systems Isolated input line receiver EIA RS--C line receiver Voltage level shifting Isolated input line receiver Isolated output line driver Logic ground isolation Harsh industrial environments Current loop receiver System test equipment isolation Process control input/output isolation - -

2 Functional Diagram Functional Diagram Multiple channel devices available. Truth Table Package styles for these parts are -pin and -pin DIP through hole (case outlines P and E respectively), -pin DIP flat pack (case outline F), and leadless ceramic chip carrier (case outline ). Devices may be purchased with a variety of lead bend and plating options. See Selection Guide Package Styles and Lead Configuration Options for details. Standard Military Drawing (SMD) parts are available for each package and lead style. Because the same electrical die (emitters and detectors) are used for each channel of each device listed in this data sheet, absolute maximum ratings, recommended operating conditions, electrical specifications, and performance characteristics shown in the figures are similar for all parts except as noted. Additionally, the same package assembly processes and materials are used in all devices. These similarities justify the use of a common data base for die related reliability and certain limited radiation test results. (Positive Logic) Input On (H) Off (L) L H Output NOTE The connection of a 0.-μF bypass capacitor between V CC and GND is recommended. Selection Guide Package Styles and Lead Configuration Options Package -pin DIP -pin DIP -pin DIP -pin Flat Pack 0-Pad LCCC Lead Style Through Hole Through Hole Through Hole Unformed Leads Surface Mount Channels Common Channel Wiring V CC, GND None V CC, GND V CC, GND None Part Number and Options Commercial N0A HCPL-00 HCPL-0 HCPL-0 HCPL-0 MIL-PRF- Class H N0A/B HCPL-0 HCPL- HCPL- HCPL- MIL-PRF- Class K HCPL-K HCPL-0K HCPL-K HCPL-K HCPL-K Standard Lead Finish Gold Plate a Gold Plate a Gold Plate a Gold Plate a Solder Pads b Solder Dipped b Option #00 Option #00 Option #00 Butt Cut/Gold Plate a Option #00 Option #00 Option #00 Gull Wing/Soldered b Option #00 Option #00 Option #00 Crew Cut/Gold Plate a Option #00 Option #00 Option #00 Class H SMD Part Number Prescript for all below None 9-9- None 9- Gold Plate a 00EC 900PC 90PC 00FC Solder Dipped b 00EA 900PA 90PA 90A - -

3 Functional Diagrams Package -pin DIP -pin DIP -pin DIP -pin Flat Pack 0-Pad LCCC Butt Cut/Gold Plate a 00YC 900YC 90YC Butt Cut/Soldered b 00YA 900YA 90YA Gull Wing/Soldered b 00XA 900XA 90ZA Crew Cut/Gold Plate a 00ZC Crew Cut/Soldered b 00ZA Class K SMD Part Number Prescript for all below Gold Plate a 9000KEC 900KPC 90KPC 9000KFC Solder Dipped b 9000KEA 900KPA 90KPA 90KA Butt Cut/Gold Plate a 9000KYC 900KYC 90KYC Butt Cut/Soldered b 9000KYA 900KYA 90KYA Gull Wing/Soldered b 9000KXA 900KXA 90KZA Crew Cut/Gold Plate a 9000KZC Crew Cut/Soldered b 9000KZA a. Gold Plate lead finish: Maximum gold thickness of leads is <00 micro inches. Typical is 0 to 90 micro inches. b. Solder lead finish: Sn/Pb. Functional Diagrams -pin DIP -pin DIP -pin DIP -pin Flat Pack 0-Pad LCCC Through Hole Through Hole Through Hole Unformed Leads Surface Mount Channels Channel Channels Channels Channels 9 0 VCC VO GND GND VCC VO NOTE All DIP and flat pack devices have common V CC and ground. LCCC (leadless ceramic chip carrier) package has isolated channels with separate V CC and ground connections. All diagrams are top view. - -

4 Leaded Device Marking Leaded Device Marking Leadless Device Marking Avago LOGO Avago P/N DLA SMD [] DLA SMD [] PIN ONE/ ESD IDENT A QYYWWZ XXXXXX XXXXXXX XXX XXX X 0 [] QML PARTS ONLY COMPLIANCE INDICATOR, [] DATE CODE, SUFFIX (IF NEEDED) COUNTRY OF MFR. Avago CAGE CODE [] Avago LOGO Avago P/N PIN ONE/ ESD IDENT COUNTRY OF MFR. A QYYWWZ XXXXXX X XXXX XXXXXX XXX 0 [] QML PARTS ONLY COMPLIANCE INDICATOR, [] DATE CODE, SUFFIX (IF NEEDED) DLA SMD [] DLA SMD [] Avago CAGE CODE [] Outline Drawings -Pin DIP Through Hole, Channels 0.9 (0.0). (0.0) 0.0 (0.90) 0. (0.0). (0.0). (0.). (0.0) 0.0 (0.00) 0. (0.0).9 (0.090).9 (0.0). (0.90). (0.0) Note: Dimensions in millimeters (inches). -Pin Flat Pack, Channels. (0.).99 (0.).9 (0.090). (0.00) REF.. (0.) 0. (0.) 0. (0.0) 0. (0.0). (0.). (0.0) 0.9 (0.0) 0.9 (0.0). (0.0) 0. (0.0) 9. (0.0). (0.0) 0.0 (0.0) 0. (0.009) Note: Dimensions in millimeters (inches). - -

5 Outline Drawings 0-Terminal LCCC Surface Mount, Channels. (0.00).0 (0.00).9 (0.) 9.09 (0.).9 (0.9). (0.0). (0.00).0 (0.00). (0.00).0 (0.00).9 (0.) 9.09 (0.).9 (0.9). (0.0) 0. (0.0) (0 PLCS).0 (0.00) ( PLCS). (0.0).0 (0.0) TERMINAL IDENTIFIER. (0.0) METALIZED CASTILLATIONS (0 PLCS) Note: Dimensions in millimeters (inches). Solder Thickness 0. (0.00) Max. -Pin DIP Through Hole, and Channel 0.0 (0.9) 0.9 (0.0).0 (0.00). (0.00). (0.0). (0.). (0.9). (0.0). (0.0) 0.0 (0.00) 0. (0.0).9 (0.090).9 (0.0). (0.90). (0.0) Note: Dimensions in millimeters (inches). - -

6 Hermetic Optocoupler Options Hermetic Optocoupler Options Option Description 00 Surface-mountable hermetic optocoupler with leads trimmed for butt joint assembly. This option is available on Commercial, Class H, and Class K product in -pin and -pin DIP.. (0.0). (0.0).0 (0.0).9 (0.090).9 (0.0). (0.0).9 (0.090).9 (0.0). (0.0).0 (0.0) 0.0 (0.00) 0. (0.0). (0.90). (0.0) Note: Dimensions in millimeters (inches). 00 Lead finish is solder dipped rather than gold plated. This option is available on Commercial, Class H, and Class K product in -pin and -pin DIP. DLA Drawing (SMD) part numbers contain provisions for lead finish. All leadless chip carrier devices are delivered with solder-dipped terminals as a standard feature. 00 Surface-mountable hermetic optocoupler with leads cut and bent for gull wing assembly. This option is available on Commercial, Class H, and Class K product in -pin and -pin DIP. This option has solder-dipped leads.. (0.0).9 (0.090).9 (0.0).0 (0.0). (0.0). (0.0). (0.0).9 (0.090).9 (0.0).0 (0.0). (0.0) 0.0 (0.00) 0. (0.0) 9. (0.0) 9.9 (0.90).0 (0.0). (0.0) Note: Dimensions in millimeters (inches). 00 Surface-mountable hermetic optocoupler with leads trimmed for butt joint assembly. This option is available on Commercial, Class H, and Class K product in -pin and -pin DIP. Contact factory for the availability of this option on DLA part types.. (0.0). (0.0).9 (0.090).9 (0.0). (0.0). (0.09) 0.0 (0.00) 0. (0.0). (0.90). (0.0).9 (0.090).9 (0.0).0 (0.00) TYP. Note: Dimensions in millimeters (inches). - -

7 Absolute Maximum Ratings Absolute Maximum Ratings Parameter Symbol Min Max Unit Notes Storage Temperature T S +0 C Operating Temperature T A + C Case Temperature T C +0 C Junction Temperature T J + C Lead Solder Temperature 0 for 0 sec C Output Current (each channel) I O 0 ma Output Voltage (each channel) V O 0. 0 V a Supply Voltage V CC 0. 0 V a Output Power Dissipation (each channel) 0 mw b Peak Input Current (each channel, < ms duration) 0 ma Average Input Current (each channel) I F 0 ma c Reverse Input Voltage (each channel) V R V Package Power Dissipation (each channel) P D 00 mw a. GND pin should be the most negative voltage at the detector side. Keeping V CC as low as possible, but greater than.0v, provides the lowest total I OH over temperature. b. Output power is collector output power plus total supply power for the single-channel device. For the dual-channel device, output power is collector output power plus one half the total supply power. For the quad-channel device, output power is collector output power plus one fourth of total supply power. Derate at. mw/ C above 0 C. c. Derate I F at 0. ma/ C above 0 C. -Pin Ceramic DIP Single Channel Schematic ANODE + I F V CC I CC V F CATHODE I O V O ESD Classification GND (MIL-STD-, Method 0) HCPL-00/0/0K and 0//K, Class N0A, N0A/B, HCPL-K, HCPL-0//K and HCPL-0//K, Class Recommended Operating Conditions Parameter Symbol Min Max Unit Input Voltage, Low Level (Each Channel) V F(OFF) 0. V Input Current, High Level (Each Channel) I F(ON) 0. ma Supply Voltage V CC.0 V Output Voltage V O.0 V - -

8 Electrical Characteristics Electrical Characteristics T A = C to + C, unless otherwise specified. Parameter Symbol Test Conditions Group A a Subgroup Limits Min Typ b Max Unit Fig Notes Current Transfer Ratio Logic Low Output Voltage Logic High Output Current Logic Low Supply Single Channel Current and LCCC Dual Channel Quad Channel Logic High Supply Single Channel Current and LCCC Dual Channel Quad Channel Input Forward Voltage Single and Dual Channel LCCC Quad Channel Input Reverse Breakdown Voltage Input-Output Insulation Leakage Current CTR V OL I F = 0. ma, V O = 0.V, V CC =.V I F =. ma, V O = 0.V, V CC =. V I F = ma, V O = 0.V, V CC =.V I F = 0. ma, I OL =. ma, V CC =.V I F =. ma, I OL =. ma, V CC =.V I F = ma, I OL = 0 ma, V CC =.V,, % c, d ,, V c c, e c I OH I F = μa, V O = V,,, μa c I OHX V CC = V 0 μa c, f I CCL I F =. ma, V CC = V,,.0 ma g I F = I F =. ma, V CC = V I F = I F = I F = I F =. ma, V CC = V.0. I CCH I F = 0 ma, V CC = V,, μa g I F = I F = 0 ma, V CC = V I F = I F = I F = I F = 0 ma, V CC = V 0 0 V F I F =. ma.0.. V c..,,.0..,... B VR I R = 0 μa,, V c I I-O % Relative Humidity T A = C, t = s, V I-O = 00 VDC.0 μa h, i - -

9 Electrical Characteristics Parameter Symbol Test Conditions Group A a Subgroup Limits Min Typ b Max Unit Fig Notes Capacitance Between Input-Output C I-O f = MHz, T A = C pf c, j k, l Propagation Delay Time to Logic Low at Output t PHL I F = 0. ma, R L =. kω, V CC = V 9, 0, 0 00 μs,,, c I F =. ma, R L =. kω, V CC = V I F = ma, R L = 0Ω, V CC = V 9, 0, 0 c, e 9 c, l 0, 0 9, 0, 0 c, e Propagation Delay Time to Logic High at Output t PLH I F = 0. ma, R L =. kω, V CC = V 9, 0, 0 μs,,, c I F =. ma, R L =. kω, V CC = V I F = ma, R L = 0 Ω, V CC = V 9, 0, 0 c, e 9 0 c, l 0, 0 9, 0, 0 c, e Common Mode Transient Immunity at Low Output Level CM L V CC = V, I F =. ma R L =. kω, V CM = V P-P l V CM = 0 V P-P e 9, 0, V/μs 9 c, m, n, o Common Mode Transient Immunity at High Output Level CM H V CC = V, I F =0 ma R L =. kω, V CM = V P-P l V CM = 0 V P-P e 9, 0, V/μs 9 c, m, n, o a. Commercial parts receive 00% testing at C (Subgroups and 9). SMD, Class H and Class K parts receive 00% testing at,, and C (Subgroups and 9, and 0, and, respectively). b. All typical values are at V CC = V, T A = C. c. Each channel. d. Current Transfer Ratio is defined as the ratio of output collector current, I O, to the forward LED input current, I F, times 00%. e. Not required for N0A, N0A/B, HCPL-K, HCPL-0//K, 00, and types. f. I OHX is the leakage current resulting from channel-to-channel optical crosstalk. I F = μa for channel under test. For all other channels, I F = 0 ma. g. The HCPL-0, HCPL-, and HCPL-K dual-channel parts function as two independent single channel units. Use the single channel parameter limits. h. All devices are considered two-terminal devices; measured between all input leads or terminals shorted together and all output leads or terminals shorted together. i. This is a momentary withstand test, not an operating condition. j. Measured between each input pair shorted together and all output connections for that channel shorted together. k. Parameters tested as part of device initial characterization and after design and process changes. Parameters guaranteed to limits specified for all lots not specifically tested. l. Required for N0A, N0A/B, HCPL-K, HCPL-0//K, 00, and types. m. CM L is the maximum rate of rise of the common mode voltage that can be sustained with the output voltage in the logic low state (V O < 0. V). CM H is the maximum rate of fall of the common mode voltage that can be sustained with the output voltage in the logic high state (V O >.0 V)

10 Typical Characteristics n. In applications where dv/dt may exceed 0,000 V/μs (such as a static discharge), a series resistor, R CC, should be included to protect the detector ICs from destructively high surge currents. The recommended value is: For single channel: R CC For dual channel: R CC For quad channel: R CC = = = (V) kω 0. I F (ma) (V) kω 0. I F (ma) (V) kω 0. I F (ma) o. Parameters tested as part of device initial characterization and after design and process changes. Parameters guaranteed to limits specified for all lots not specifically tested. Typical Characteristics T A = C, V CC = V. Parameter Symbol Typ Unit Test Conditions Note Input Capacitance C IN 0 pf V F = 0V, f = MHz a Input Diode Temperature Coefficient ΔV F /ΔT A. mv/ C I F =. ma a Resistance (Input-Output) R I-O 0 Ω V I-O = 00V a, b Capacitance (Input-Output) C I-O.0 pf f = MHz a, b Dual and Quad Channel Product Only Input-Input Leakage Current I I-I 0. na Relative Humidity = %, V I-I = 00V, t = s c Resistance (Input-Input) R I-I 0 Ω V I-I = 00V c Capacitance (Input-Input) C I-I.0 pf f = MHz c a. Each channel. b. Measured between each input pair shorted together and all output connections for that channel shorted together. c. Measured between adjacent input pairs shorted together for each multichannel device

Typical Characteristics Figure Input Diode Forward Current vs. Forward Voltage Figure Normalized DC Transfer Characteristics Figure Normalized Current Transfer Ratio vs.

11 Typical Characteristics Figure Input Diode Forward Current vs. Forward Voltage Figure Normalized DC Transfer Characteristics Figure Normalized Current Transfer Ratio vs. Input Diode Forward Current Figure Normalized Supply Current vs. Input Diode Forward Current Figure Propagation Delay to Logic Low vs. Input Pulse Period Figure Propagation Delay vs. Temperature - -

* SEE NOTE Figure Switching Test Circuit PULSE GEN. Z O = 0 t r, t f = 0 ns f = 00 Hz t PULSE = 0.ms I F R CC *.

12 Typical Characteristics Figure Propagation Delay vs. Input Diode Forward Current Figure 9 Test Circuit for Transient Immunity and Typical Waveforms I F B A R CC *.0 F R L + V V O V FF V CM + PULSE GEN. * SEE NOTE Figure Switching Test Circuit PULSE GEN. Z O = 0 t r, t f = 0 ns f = 00 Hz t PULSE = 0.ms I F R CC *.0 F R L + V I F MONITOR V O Rm C L ** Figure 0 Recommended Drive Circuitry Using TTL Open-Collector Logic * SEE NOTE ** C L INCLUDES PROBE AND STRAY WIRING CAPACITANCE. V CC R I LEAK R. VF R I F R VCC V F I F R I F + I LEAK R MAY BE OMITTED IF ADDITIONAL FANOUT IS NOT USED. - -

13 Typical Characteristics Figure Operating Circuit for Burn-In and Steady State Life Tests V CC + V (EACH INPUT) 0.0 F V OC V IN + (EACH OUTPUT) CONDITIONS: I F = 0 ma I O = 0 ma T A = + C * ALL CHANNELS TESTED SIMULTANEOUSLY. - -

14 For product information and a complete list of distributors, please go to our web site: the pulse logo, Connecting everything, Avago Technologies, Avago, and the A logo are among the trademarks of in the United States, certain other countries and/or the EU. Copyright All Rights Reserved. The term "" refers to Limited and/or its subsidiaries. For more information, please visit reserves the right to make changes without further notice to any products or data herein to improve reliability, function, or design. Information furnished by is believed to be accurate and reliable. However, does not assume any liability arising out of the application or use of this information, nor the application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others. AV0-EN January, 0

Features. Applications. and GND is recommended.

Features. Applications. and GND is recommended. 6N134,* 81028, HCPL-563X, HCPL-663X, HCPL-565X, 5962-98001, HCPL-268K, HCPL-665X, 5962-90855, HCPL-560X Hermetically Sealed, High Speed, High CMR, Logic Gate Optocouplers Data Sheet *See matrix for available