Data Sheet. Hermetically Sealed, Very High Speed, Logic Gate Optocouplers HCPL-540X,* , HCPL-543X, HCPL-643X,

Size: px

Start display at page:

Download "Data Sheet. Hermetically Sealed, Very High Speed, Logic Gate Optocouplers HCPL-540X,* , HCPL-543X, HCPL-643X,"

Phebe Gibson
6 years ago
Views:

1 Hermetically Sealed, Very High Speed, Logic Gate Optocouplers Data Sheet HCPL-540X,* , HCPL-543X, HCPL-643X, *See matrix for available extensions. Description These units are single and dual channel, hermetically sealed optocouplers. The products are capable of operation and storage over the full military temperature range and can be purchased as either standard product or with full MIL-PRF Class Level H or K testing or from the appropriate DSCC Drawing. All devices are manufactured and tested on a MIL-PRF certified line and are included in the DSCC Qualified Manufacturers List, QML for Hybrid Microcircuits. Truth Tables (Positive Logic) Multichannel Devices Input On (H) Off (L) Single Channel DIP Input Enable Output On (H) L L Off (L) L H On (H) H Z Off (L) H Z Functional Diagram Multiple channel devices available V E Output L H Features Dual marked with device part number and DSCC standard microcircuit drawing Manufactured and tested on a MIL-PRF certified line QML-38534, Class H and K Three hermetically sealed package configurations Performance guaranteed over full military temperature range: -55 C to +5 C High Speed: 40 M bit/s High common mode rejection 500 V/µs guaranteed 500 Vdc withstand test voltage Active (totem pole) outputs Three stage output available High radiation immunity HCPL-400/30 function compatibility Reliability data Compatible with TTL,, L, and HCMOS logic families Applications Military and space High reliability systems Transportation, medical, and life critical systems Isolation of high speed logic systems Computer-peripheral interfaces Switching power supplies Isolated bus driver (networking applications)- (5400//K only) Pulse transformer replacement Ground loop elimination Harsh industrial environments High speed disk drive I/O Digital isolation for A/D, D/A conversion V O The connection of a 0. µf bypass capacitor between and is recommended. CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD.

2 Each channel contains an AlGaAs light emitting diode which is optically coupled to an integrated high gain photon detector. This combination results in very high data rate capability. The detector has a threshold with hysteresis, which typically provides 0.5 ma of differential mode noise immunity and minimizes the potential for output signal chatter. The detector in the single channel units has a three state output stage which eliminates the need for a pull-up resistor and allows for direct drive of a data bus. All units are compatible with TTL,, L, and HCMOS logic families. The 35 ns pulse width distortion specification guarantees a 0 MBd signaling rate at +5 C with 35% pulse width distortion. Figures 3 through 6 show recommended circuits for reducing pulse width distortion and optimizing the signal rate of the product. Package styles for these parts are 8 pin DIP through hole (case outlines P), and leadless ceramic chip carrier (case outline ). Devices may be purchased with a variety of lead bend and plating options. See Selection Guide Table for details. Standard Microcircuit Drawing (SMD) parts are available for each package and lead style. Because the same electrical die (emitters and detectors) are used for each channel of each device listed in this data sheet, absolute maximum ratings, recommended operating conditions, electrical specifications, and performance characteristics shown in the figures are similar for all parts. Occasional exceptions exist due to package variations and limitations and are as noted. Additionally, the same package assembly processes and materials are used in all devices. These similarities give justification for the use of data obtained from one part to represent other part s performance for die related reliability and certain limited radiation test results. Selection Guide Package Styles and Lead Configuration Options Package 8 Pin DIP 8 Pin DIP 0 Pad LCCC Lead Style Through Hole Through Hole Surface Mount Channels Common Channel Wiring None, None Avago Part # & Options Commercial HCPL-5400 HCPL-5430 HCPL-6430 MIL-PRF-38534, Class H HCPL-540 HCPL-543 HCPL-643 MIL-PRF-38534, Class K HCPL-540K HCPL-543K HCPL-643K Standard Lead Finish Gold Plate Gold Plate Solder Pads* Solder Dipped* Option 00 Option 00 Butt Cut/Gold Plate Option 00 Option 00 Gull Wing/Soldered* Option 300 Option 300 Class H SMD Part # Prescript for all below Either Gold or Solder PX 89570PX 89570X Gold Plate PC 89570PC Solder Dipped* PA 89570PA 89570A Butt Cut/Gold Plate YC 89570YC Butt Cut/Soldered* YA 89570YA Gull Wing/Soldered* XA 89570XA Class K SMD Part # Prescript for all below Either Gold of Solder KPX KPX KX Gold Plate KPC KPC Solder Dipped* KPA KPA KA Butt Cut/Gold Plate KYC KYC Butt Cut/Soldered* KYA KYA Gull Wing/Soldered* KXA KXA *Solder contains lead.

3 Functional Diagrams 8 Pin DIP 8 Pin DIP 0 Pad LCCC Through Hole Through Hole Surface Mount Channel Channels Channels 5 V E 8 7 V O V O V O V O V O Note: All DIP devices have common and ground. LCCC (leadless ceramic chip carrier) package has isolated channels with separate and ground connections. Outline Drawings 0 Terminal LCCC Surface Mount, Channels.78 (0.070).03 (0.080) 8.70 (0.34) 9.0 (0.358) 4.95 (0.95) 5. (0.05).78 (0.070).03 (0.080).5 (0.060).03 (0.080) 8.70 (0.34) 9.0 (0.358) 4.95 (0.95) 5. (0.05) 0.64 (0.05) (0 PLCS).0 (0.040) (3 PLCS).4 (0.045).40 (0.055) TERMINAL IDENTIFIER.6 (0.085) METALLIZED CASTILLATIONS (0 PLCS) 0.5 (0.00) NOTE: DIMENSIONS IN MILLIMETERS (INCHES). SOLDER THICKNESS 0.7 (0.005) 8 Pin DIP Through Hole, and Channel 9.40 (0.370) 9.9 (0.390) 0.76 (0.030).7 (0.050) 8.3 (0.30) 7.6 (0.8) 7.57 (0.98) 4.3 (0.70) 0.5 (0.00) MIN. 3.8 (0.50) MIN. 0.0 (0.008) 0.33 (0.03).9 (0.090).79 (0.0) 0.5 (0.00) NOTE: DIMENSIONS IN MILLIMETERS (INCHES) (0.90) 7.87 (0.30) 3

4 Leaded Device Marking Leadless Device Marking Avago DESIGNATOR Avago P/N DSCC SMD* DSCC SMD* PIN ONE/ ESD IDENT A QYYWWZ XXXXXX XXXXXXX XXX XXX COMPLIANCE INDICATOR,* DATE CODE, SUFFIX (IF NEEDED) COUNTRY OF MFR. Avago CAGE CODE* Avago DESIGNATOR Avago P/N PIN ONE/ ESD IDENT COUNTRY OF MFR. A QYYWWZ XXXXXX XXXX XXXXXX XXX COMPLIANCE INDICATOR,* DATE CODE, SUFFIX (IF NEEDED) DSCC SMD* DSCC SMD* Avago CAGE CODE* * QUALIFIED PARTS ONLY * QUALIFIED PARTS ONLY Hermetic Optocoupler Options Option Description 00 Surface mountable hermetic optocoupler with leads trimmed for butt joint assembly. This option is available on commercial and hi-rel product in 8 pin DIP (see drawings below for details). 4.3 (0.70) 0.5 (0.00) MIN..9 (0.090).79 (0.0).4 (0.045).40 (0.055) 0.5 (0.00) NOTE: DIMENSIONS IN MILLIMETERS (INCHES). 0.0 (0.008) 0.33 (0.03) 7.36 (0.90) 7.87 (0.30) 00 Lead finish is solder dipped rather than gold plated. This option is available on commercial and hi-rel product in 8 pin DIP. DSCC Drawing part numbers contain provisions for lead finish. All leadless chip carrier devices are delivered with solder dipped terminals as a standard feature. 300 Surface mountable hermetic optocoupler with leads cut and bent for gull wing assembly. This option is available on commercial and hi-rel product in 8 pin DIP (see drawings below for details). This option has solder dipped leads (0.80) 4.57 (0.80) 0.5 (0.00) MIN..9 (0.090).79 (0.0).40 (0.055).65 (0.065) 0.5 (0.00) (0.008) 0.33 (0.03) 9.65 (0.380) 9.9 (0.390) NOTE: DIMENSIONS IN MILLIMETERS (INCHES). *Solder contains lead. 4

5 Absolute Maximum Ratings No derating required up to +5 C. Parameter Symbol Min. Max. Units Note Storage Temperature T S C Operating Temperature T A C Case Temperature T C +70 C Junction Temperature T J +75 C Lead Solder Temperature 60 for 0 sec C Average Forward Current (each channel) I F(AVG) 0 ma Peak Input Current (each channel) I F(PEAK) 0 ma Reverse Input Voltage (each channel) V R 3 V Supply Voltage V Average Output Current (each channel) I O(AVG) -5 5 ma Output Voltage (each channel) V O V Output Power Dissipation (each channel) P O 30 mw Package Power Dissipation (each channel) P D 00 mw Single Channel Product Only Three State Enable Voltage V E V 8 Pin Ceramic DIP Single Channel Schematic ANODE + V F 3 CATHODE I F I CC I E 8 7 V E 6 V O 5 Note enable pin 7. An external 0.0 µf to 0. µf bypass capacitor must be connected between and ground for each package type. ESD Classification (MIL-STD-883, Method 305) HCPL-5400/0/0K ( ), Class HCPL-5430/3/3K and HCPL-6430/3/3K (Dot), Class 3 Recommended Operating Conditions Parameter Symbol Min. Max. Units Input Current (High) I F(ON) 6 0 ma Supply Voltage, Output V Input Voltage (Low) V F(OFF) 0.7 V Fan Out (Each Channel) N 5 TTL Loads Single Channel Product Only High Level Enable Voltage V EH.0 V Low Level Enable Voltage V EL V 5

6 Electrical Characteristics T A = -55 C to +5 C, 4.75 V 5.5 V, 6 ma I F(ON) 0 ma, 0 V V F(OFF) 0.7 V, unless otherwise specified. Group A [0] Limits Parameter Sym. Test Conditions Subgroups Min. Typ.* Max. Units Fig. Notes Low Level Output Voltage V OL I OL = 8.0 ma (5 TTL Loads),, V 9 High Level Output Voltage V OH I OH = -4.0 ma,, 3.4 V 9 Output Leakage Current I OHH V O = 5.5 V, V F = 0.7 V,, 3 00 µa 9 Logic High Single I CCH = 5.5 V, V E = 0 V,, ma Supply Channel Current Dual Channel Logic Low Single I CCL,, ma Supply Channel Current Dual Channel Input Forward Voltage V F I F = 0 ma,, V 4 9 Input Reverse Breakdown V R I R = 0 µa,, V 9 Voltage Input-Output Insulation I I-O V I-O = 500 Vdc, RH 65%,.0 µa, 3 Leakage Current t = 5 s Propagation Delay Time t PHL 9, 0, ns 5, 4, 9 Logic Low Output 6, 7 Propagation Delay Time t PLH 9, 0, ns 5, 4, 9 Logic High Output 6, 7 Pulse Width PWD 9, 0, 3 35 ns 5, 4, 9 Distortion 6, 7 Logic High Common CM H V CM = 50 V P-P, I F = 0 ma 9, 0, V/µs 5, 9, Mode Transient Immunity Logic Low Common CM L V CM = 50 V P-P, I F = 6 ma 9, 0, V/µs 5, 9, Mode Transient Immunity Single Channel Product Only Group A [0] Limits Parameter Sym. Test Conditions Subgroups Min. Typ.* Max. Units Fig. Notes Logic High Enable V EH,, 3.0 V Voltage Logic Low Enable V EL,, V Voltage Logic High Enable I EH V E =.4 V,, 3 0 µa Current V E = 5.5 V,, 3 00 Logic Low Enable I EL V E = 0.4 V,, ma Current High Impedance State I CCZ = 5.5 V,,, 3 8 ma Supply Current V E = 5.5 V High Impedance State I OZL V O = 0.4 V, V E = V,, 3-0 µa Output Current I OZH V O =.4 V, V E = V 0 *All typical values are at = 5 V, T A = 5 C, I F = 8 ma except where noted. V O = 5.5 V, V E = V 00 6

7 Typical Characteristics All typical values are at T A = 5 C, = 5 V, I F = 8 ma, unless otherwise specified. Parameter Symbol Typ. Units Test Conditions Fig. Notes Input Current Hysteresis I HYS 0.5 ma = 5 V 3 Input Diode Temperature V F -. mv/ C I F = 0 ma 4 Coefficient T A Resistance (Input-Output) R I-O 0 Ω V I-O = 500 V Capacitance (Input-Output) C I-O 0.6 pf f = MHz, V I-O = 0 V Logic Low Short Circuit Output Current I OSL 65 ma V O = = 5.5 V, I F = 0 ma 6, 9 Logic High Short Circuit I OSH -50 ma = 5.5 V, I F = 0 ma, 6, 9 Output Current V O = Output Rise Time (0-90%) t r 5 ns 5 Output Fall Time (90-0%) t f 0 ns 5 Propagation Delay Skew t PSK 30 ns 0 Power Supply Noise Immunity PSNI 0.5 V P-P 48 Hz f ac 50 MHz 7 Single Channel Product Only Parameter Symbol Typ. Units Test Conditions Fig. Notes Input Capacitance C IN 5 pf f = MHz, V F = 0 V, Pins and 3 Output Enable Time to Logic High t PZH 5 ns 8, 9 Output Enable Time to Logic Low t PZL 30 ns 8, 9 Output Disable Time from Logic High t PHZ 0 ns 8, 9 Output Disable Time from Logic Low t PLZ 5 ns 8, 9 Dual and Quad Channel Product Only Input Capacitance C IN 5 pf f = MHz, V O = 0 V Input-Input Leakage Current I I-I 0.5 na RH 65%, V I-I = 500 Vdc 8 Input-Input Resistance R I-I 0 Ω V I-I = 500 V 8 Input-Input Capacitance C I-I.3 pf f = MHz, V F = 0 V 8 7

8 Notes:. Not to exceed 5% duty factor, not to exceed 50 µsec pulse width.. All devices are considered two-terminal devices: measured between all input leads or terminals shorted together and all output leads or terminals shorted together. 3. This is a momentary withstand test, not an operating condition. 4. t PHL propagation delay is measured from the 50% point on the rising edge of the input current pulse to the.5 V point on the falling edge of the output pulse. The t PLH propagation delay is measured from the 50% point on the falling edge of the input current pulse to the.5 V point on the rising edge of the output pulse. Pulse Width Distortion, PWD = t PHL - t PLH. 5. CM L is the maximum slew rate of the common mode voltage that can be sustained with the output voltage in the logic low state (V O(MAX) < 0.8 V). CM H is the maximum slew rate of the common mode voltage that can be sustained with the output voltage in the logic high state (V O(MIN) >.0 V). 6. Duration of output short circuit time not to exceed 0 ms. 7. Power Supply Noise Immunity is the peak to peak amplitude of the ac ripple voltage on the line that the device will withstand and still remain in the desired logic state. For desired logic high state, V OH(MIN) >.0 V, and for desired logic low state, V OL(MAX) < 0.8 V. 8. Measured between adjacent input pairs shorted together for each multichannel device. 9. Each channel. 0. Standard parts receive 00% testing at 5 C (Subgroups and 9). SMD, Class H and Class K parts receive 00% testing at 5, 5, and 55 C (Subgroups and 9, and 0, 3 and, respectively).. Parameters are tested as part of device initial characterization and after design and process changes. Parameters are guaranteed to limits specified for all lots not specifically tested.. Propagation delay skew is defined as the difference between the minimum and maximum propagation delays for any given group of optocouplers with the same part number that are all switching at the same time under the same operating conditions. 3. The HCPL-6430, HCPL-643, and HCPL-643K dual channel parts function as two independent single channel units. Use the single channel parameter limits. Figure. Typical logic low output voltage vs. logic low output current Figure. Typical logic high output voltage vs. logic high output current Figure 3. Typical output voltage vs. input forward current Figure 4. Typical diode input forward current characteristic 8

9 INPUT MONITORING NODE PULSE GEN. t r = t f = 5 ns f = 500 khz 5 % DUTY CYCLE C 5 pf I F 00 Ω D.U.T. V O OUTPUT MONITORING NODE 0. µf 30 pf C.5 KΩ 5.0 V.3 KΩ THE PROBE AND JIG CAPACITANCES ARE REPRESENTED BY C AND C. ALL DIODES ARE N450 OR EQUIVALENT. Figure 5. Test circuit for t PLH, t PHL, t r, and t f Figure 6. Typical propagation delay vs. ambient temperature Figure 7. Typical propagation delay vs. input forward current PULSE GENERATOR Z O = 50 Ω t r = t f = 5 ns D.U.T µf 5.0 V S I F 7 V O D.3 KΩ C 30 pf D INPUT V E MONITORING NODE.5 KΩ D 3 D 4 S Figure 8. Test circuit for t PHZ, t PZH, t PLZ, and t PZL. (single channel product only) 9

10 Figure 9. Typical enable propagation delay vs. ambient temperature. (single channel product only) Figure 0. Propagation delay skew, t PSK, waveform I F B D.U.T. = 5.0 V + V FF A 0. µf* OUTPUT V O MONITORING NODE C L 5 pf V CM = 5.5 V + PULSE GEN. I F D.U.T.* I CC V IN +. V 00 Ω TYP. I O 00 Ω 0.0 µf CONDITIONS: I F = 0 ma T A = +5 C I O = 5 ma V DC = 3.0 V * FOR SINGLE CHANNEL UNITS, GROUND ENABLE PIN. Figure. Test diagram for common mode transient immunity and typical waveforms Figure. Operating circuit for burn-in and steady state life tests 0

11 MIL-PRF Class H, Class K, and DSCC SMD Test Program Avago Technologies Hi-Rel Optocouplers are in compliance with MIL-PRF Classes H and K. Class H and Class K devices are also in compliance with DSCC drawings , and Testing consists of 00% screening and quality conformance inspection to MIL-PRF Data Rate and Pulse-Width Distortion Definitions Propagation delay is a figure of merit which describes the finite amount of time required for a system to translate information from input to output when shifting logic levels. Propagation delay from low to high (t PLH ) specifies the amount of time required for a system s output to change from a Logic 0 to a Logic, when given a stimulus at the input. Propagation delay from high to low (t PHL ) specifies the amount of time required for a system s output to change from a Logic to a Logic 0, when given a stimulus at the input (see Figure 5). When t PLH and t PHL differ in value, pulse width distortion results. Pulse width distortion is defined as t PHL -t PLH and determines the maximum data rate capability of a distortion-limited system. Maximum pulse width distortion on the order of 5-35% is typically used when specifying the maximum data rate capabilities of systems. The exact figure depends on the particular application (RS-3, PCM, T-, etc.). These high performance optocouplers offer the advantages of specified propagation delay (t PLH, t PHL ), and pulse width distortion ( t PLH -t PHL ) over temperature and power supply voltage ranges. Applications = +5 V IN A 30 pf 6 Ω 74 Ω HCPL µf TTL L HCMOS = 5 V OUT Y TOTEM POLE OUTPUT GATE (e.g. 54AS000) Y = A Figure 3. Recommended HCPL-5400 interface circuit

12 = +5 V IN A 464 Ω OPEN COLLECTOR OUTPUT GATE (e.g. 54S05) HCPL-5400 Y = A 0. µf TTL L = 5 V OUT Y Figure 4. Alternative HCPL-5400 interface circuit = 5 V 30 pf 6 Ω HCPL-5430 IN A TOTEM POLE OUTPUT GATE (e.g. 54AS000) 74 Ω 74 Ω 0. µf TTL L HCMOS TTL L HCMOS = +5 V OUT Y OUT Y IN A 6 Ω 30 pf Y = A Figure 5. Recommended HCPL-5430 and HCPL-6430 interface circuit = +5 V 464 Ω HCPL-5430 IN A OPEN COLLECTOR OUTPUT GATE (e.g. 54AS05) IN A 464 Ω Y = A 0. µf TTL L HCMOS TTL L HCMOS = +5 V OUT Y OUT Y Figure 6. Alternative HCPL-5430 and HCPL-6430 interface circuit For product information and a complete list of distributors, please go to our website: Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies Limited in the United States and other countries. Data subject to change. Copyright 007 Avago Technologies Limited. All rights reserved. Obsoletes E E June, 007

HCPL-520x, HCPL-523x, HCPL-623x, HCPL-625x, and Hermetically Sealed Low IF, Wide VCC, Logic Gate Optocouplers.

HCPL-520x, HCPL-523x, HCPL-623x, HCPL-625x, 5962-88768 and 5962-88769 Hermetically Sealed Low IF, Wide VCC, Logic Gate Optocouplers Data Sheet Description These units are single, dual and quad channel,