ACPL-P480 and ACPL-W480

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1 High CMR Intelligent Power Module and Gate Drive Interface Optocoupler Description The high-speed ACPL-P48/W48 optocoupler contains a GaAsP LED, a photo detector, and a Schmitt trigger that eliminates the requirement for external waveform conditioning circuits. The totem pole output eliminates the need for a pull-up resistor and allows for a direct-drive Intelligent Power Module or gate drive. Propagation delay difference between devices has been minimized to maximize inverter efficiency through reduced switching dead time. Applications IPM Interface Isolation Isolated IGBT/MOSFET Gate Drive AC and Brushless DC Motor Drives Industrial Inverters General Digital Isolation Functional Diagram Features Performance Specified for Common IPM Applications Over Industrial Temperature Range Short Maximum Propagation Delays Minimized Pulse Width Distortion (PWD) Very High Common Mode Rejection (CMR) Hysteresis Totem Pole Output (No Pull-up Resistor Required) Available in Stretched SO- Package Package Clearance/Creepage at 8 mm (ACPL-W48) Safety Approval: UL Recognized with 375V RMS for minute (5V RMS for minute for all ACPL-W48 devices and Option 2 device for ACPL-P48) per UL577 CSA Approved IEC/EN/DIN EN approved with V IORM = 89V peak for ACPL-P48 and V IORM = 4V peak for ACPL-W48 ANODE V CC Specifications N.C. CATHODE 2 3 SHIELD Ground Note: A. μf bypass capacitor must be connected between pins 4 and. 5 4 V O Wide Operating Temperature Range: 4 C to C Maximum Propagation Delay t PHL /t PLH = 35 ns Maximum Pulse Width Distortion (PWD) = 25 ns Propagation Delay Difference: Min. ns, Max. 25 ns Wide Operating V CC Range: 4.5V to 2V 2 kv/μs Minimum Common Mode Rejection (CMR) at V CM = V Truth Table (Non-Inverting Logic) LED V ON HIGH CAUTION It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD. OFF LOW - -

2 Ordering Information ACPL-P48 is UL Recognized with 375V RMS for minute and ACPL-W48 is UL Recognized with 5V RMS for minute per UL577. Both are approved under CSA Component Acceptance Notice #5, File CA Part Number Option RoHS Compliant Package Surface Mount Tape and Reel IEC/EN/DIN EN Quantity -E X per tube -5E X X per tube ACPL-P48-2E 7 mm Stretched X per tube -52E SO- X X per tube -E X X per tube -5E X X X per tube -E X per tube ACPL-W48-5E 8 mm Stretched X X per tube -E SO- X X per tube -5E X X X per tube To order, choose a part number from the part number column and combine with the desired option from the option column to form an ordering part number. Example : ACPL-P48-5E to order product of Stretched SO- package in Tape and Reel packaging with IEC/EN/DIN EN Safety Approval in RoHS compliant. Example 2: ACPL-P48-E to order product of Stretched SO- package in tube packaging and RoHS compliant. Option data sheets are available. Contact your sales representative or authorized distributor for information. Solder Reflow Profile The recommended reflow profile is per JEDEC Standard, J-STD-2 (latest revision). Non-halide flux should be used. Regulatory Information The ACPL-P48 and ACPL-W48 are approved by the following organizations: IEC/EN/DIN EN (Option only): IEC : 27 EN : 2 DIN EN (VDE 884-5): 2- UL: ACPL-P48: Approval under UL 577, component recognition program up to V ISO = 375V RMS. File E553. ACPL-W48 and ACPL-P48 (option 2): Approval under UL 577, component recognition program up to V ISO = 5V RMS. File E553. CSA: Approval under CSA Component Acceptance Notice #5, File CA

3 Package Outline Drawings ACPL-P48 Stretched SO- Package (7 mm Clearance).38 ±.27.5 ±.5.27 BSG * ±.27.3 ± ± ± ±..8 ±.4 ±.25.4 ±. 5 NOM. 9.7 ± ±..254 ±.5. ±.2 Floating Lead protusion max. =.25 mm [. inches] Lead Coplanarity =. mm [.4 inches] Dimensions in millimeters [inches] *Total Package Width = ±.254 mm (inclusive of mold flash) ACPL-W48 Stretched SO- Package (8 mm Clearance).38 ±.27.5 ±.5.27 BSG * [.3] ±.27.3 ± ± ± ±..8 ±.4.75 ±.25 [.295 ±.] 35 NOM..5 ± ±..254 ±.5. ±.2 Floating Lead protusion max. =.25 mm [. inches] Lead Coplanarity =. mm [.4 inches] Dimensions in millimeters [inches] *Total Package Width = ±.254 mm (inclusive of mold flash) - 3 -

4 IEC/EN/DIN EN Insulation Characteristics (Option ) Description Symbol ACPL-P48 ACPL-W48 Unit Installation Classification per DIN VDE /39, Table for rated mains voltage 5V RMS for rated mains voltage 3V RMS for rated mains voltage V RMS I IV I IV I III I IV I IV I IV Climatic Classification 55//2 Pollution Degree (DIN VDE /39) 2 Maximum Working Insulation Voltage V IORM 89 4 V peak Input to Output Test Voltage, Method b a V IORM x.875 = V PR, % Production Test with t m = sec, Partial Discharge < 5 pc Input to Output Test Voltage, Method a a V IORM x.=v PR, Type and Sample Test, t m = sec, V PR V peak V PR V peak Partial Discharge < 5 pc Highest Allowable Overvoltage (Transient Overvoltage t ini = sec) V IOTM 8 V peak Safety-limiting Values maximum values allowed in the event of a failure Case Temperature T S 75 C Input Current I S, INPUT 23 ma Output Power P S, OUTPUT mw Insulation Resistance at T S, V IO = 5V R S > 9 Ω a. Refer to the optocoupler section of the Isolation and Control Components Designer s Catalog, under the Product Safety Regulations section, (IEC/EN/DIN EN ), for a detailed description of Method a and Method b partial discharge test profiles. Insulation and Safety Related Specifications Parameter Symbol ACPL-P48 ACPL-W48 Unit Condition Minimum External Air Gap (External Clearance) Minimum External Tracking (External Creepage) Minimum Internal Plastic Gap (Internal Clearance) Minimum Internal Tracking (Internal Creepage) Tracking Resistance (Comparative Tracking Index) L() mm Measured from input terminals to output terminals, shortest distance through air. L(2) mm Measured from input terminals to output terminals, shortest distance path along body..8 mm Through insulation distance conductor to conductor, usually the straight line distance thickness between the emitter and detector. N/A mm Measured from input terminals to output terminals, along internal cavity. CTI >75 V DIN IEC 2/VDE 33 Part. Isolation Group IIIa Material Group (DIN VDE, /89, Table )

5 UL 577 Specification Sheet Model Package Type Current, ma Absolute Maximum Ratings Power, mw Emitter Sensor Emitter Sensor Isolation Voltage min, V RMS Maximum Operating Temperature, C Maximum Junction Temperature, C Maximum Storage Temperature, C P Parameter Symbol Min. Max. Unit Storage Temperature T S C Operating Temperature T A 4 + C Average Input Current I F(AVG) ma Peak Transient Input Current (< μs pulse width, 3 pps) (<2 μs pulse width, <% duty cycle) I F(TRAN). 4 Reverse Input Voltage V R 5 V Average Output Current I O 25 ma Supply Voltage V CC 25 V Output Voltage V O V Total Package Power Dissipation a a. Derate total package power dissipation, PT, linearly above 7 C free-air temperature at a rate of 4.5 mw/ C. A ma P T 2 mw Recommended Operating Conditions Parameter Symbol Min. Max. Unit Note Power Supply Voltage V CC V Forward Input Current (OFF) I F(OFF) ma Forward Input Voltage (ON) V F(ON).8 V Operating Temperature T A 4 + C Electrical Specifications Over recommended operating conditions T A = 4 C to + C, V CC = +4.5V to 2V, I F(ON) = ma to ma, V F(OFF) = V to.8v, unless otherwise specified. All typicals at T A = 25 C. Parameter Symbol Min. Typ. Max. Unit Test Conditions Fig. Note Logic Low Output Voltage V OL.5 V I OL =.4 ma, 3, 9, Logic High Output Voltage V OH 2.4 V CC. V I OH = 2. ma 2, 3, 7, 9, ACPL-P I OH =.4 ma ACPL-W I OH =. ma - 5 -

6 Parameter Symbol Min. Typ. Max. Unit Test Conditions Fig. Note Threshold Input Current Low to High Output Leakage Current (V O = V CC +.5V) ma I OHH μa V CC = 5V, I F = ma 5 μa V CC = 2V, I F = ma Logic Low Supply Current I CCL.9 3. ma V CC = 5.5V, V F = V, I O = Open ma V CC = 2V, V F = V, I O = Open Logic High Supply Current I CCH ma V CC = 5.5V, I F = ma, I O = Open. 2.5 ma V CC = 2V, I F = ma, I O = Open Logic Low Short Circuit Output Current Logic High Short Circuit Output Current I OSL 25 ma V O = V CC = 5.5V, V F = V a 5 ma V O = V CC = 2V, V F = V I OSH 25 ma V CC = 5.5V, I F = ma, I O = Open a 5 ma V CC = 2V, I F = ma, I O = Open Input Forward Voltage V F.5.7 V T A = 25 C, I F = ma 4.85 V I F = ma Input Reverse Breakdown Voltage BV R 5 V I R = μa Input Diode Temperature ΔV F /ΔT A.7 mv/ C I F = ma Coefficient Input Capacitance C IN pf f = MHz, V F = V b a. Duration of output short circuit time should not exceed ms. b. Input capacitance is measured between pin and pin 3. Switching Specifications Over recommended operating conditions T A = 4 C to + C, V CC = +4.5V to 2V, I F(ON) = ma to ma, V F(OFF) = V to.8v, unless otherwise specified. All typicals at T A = 25 C. Parameter Symbol Min. Typ. Max. Unit Test Conditions Fig. Note Propagation Delay Time to t PHL 5 35 ns with Peaking Capacitor 5, Logic Low Output Level Propagation Delay Time to t PLH 35 ns with Peaking Capacitor 5, Logic High Output Level Pulse Width Distortion t PHL t PLH = PWD 25 ns 2 Propagation Delay Difference Between Any Two Parts PDD +25 ns 3 Output Rise Time (% to 9%) t r ns 5, 8 Output Fall Time (9% to %) t f 2 ns 5, 8 Logic High Common Mode Transient Immunity Logic Low Common Mode Transient Immunity CM H 2 kv/μs V CM = V, I F =. ma V CC = 5V, T A = 25 C CM L 2 kv/μs V CM = V, V F = V, V CC = 5V, T A = 25 C

7 Package Characteristics Parameter Symbol Min. Typ. Max. Unit Test Conditions Fig. Note Input-Output Momentary Withstand Voltage a V ISO 375 b 5 c a. The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. For the continuous voltage rating refer to the IEC/EN/DIN EN Insulation Characteristics Table (if applicable). b. For all ACPL-P48 devices except Option 2. c. For ACPL-W48 and Option 2 of ACPL-P48) V RMS RH < 5%, t = min. T A = 25 C Input-Output Resistance R I-O 2 V I-O = 5V DC 5 Input-Output Capacitance C I-O. f = MHz, V I-O = V DC 5 5, Notes:. The t PLH propagation delay is measured from the 5% point on the leading edge of the input pulse to the.3v point on the leading edge of the output pulse. The t PHL propagation delay is measured from the 5% point on the trailing edge of the input pulse to the.3v point on the trailing edge of the output pulse. 2. Pulse Width Distortion (PWD) is defined as t PHL t PLH for any given device. 3. The difference between t PLH and t PHL between any two devices under the same test condition. 4. CM H is the maximum slew rate of the common mode voltage that can be sustained with the output voltage in the logic high state, V O > 2.V. CM L is the maximum slew rate of the common mode voltage that can be sustained with the output voltage in the logic low state, V O <.8V. 5. Device considered a two-terminal device: pins, 2, and 3 shorted together and pins 4, 5, and shorted together.. In accordance with UL 577, each optocoupler is proof tested by applying an insulation test voltage 45V RMS for one second (leakage detection current limit, I I-O 5 μa); each optocoupler with option 2 is proof tested by applying an insulation test voltage. V RMS for second (leakage detection current limit, I I-O 5 μa). This test is performed before the % production test for partial discharge (Method b) shown in the IEC/EN/DIN EN Insulation Characteristics Table, if applicable. 7. Use of a. μf bypass capacitor connected between pins 4 and is recommended

8 Figure Typical Logic Low Output Voltage vs. Temperature VOL - LOW LEVEL OUTPUT VOLTAGE - V V CC = 4.5/2V V F = V I O =.4 ma V CC = 4.5V V CC = 2V T A - TEMPERATURE - C Figure 2 Typical Logic High Output Current vs. Temperature IOH - HIGH LEVEL OUTPUT CURRENT - ma Vcc = 4.5V I F = ma Vo = 2.7V Vo = 2.4V T A - TEMPERATURE - C Figure 3 Typical Output Voltage vs. Forward Input Current Figure 4 Typical Input Diode Forward Characteristic Vo - OUTPUT VOLTAGE - V I O =.4 ma I O = -2. ma T A = 25C V CC = 4.5V I F - INPUT CURRENT - ma IF - FORWARD CURRENT - ma..... V F + - I F T A = 25 C V F - FORWARD VOLTAGE - V Figure 5 Test Circuit for t PLH, t PHL, t r, and t f INPUT MONITORING NODE PULSE GEN. t r = t f = 5 ns f = khz % DUTY CYCLE V O = 5V Z O = 5Ω R 2 3 C = 2 pf SHIELD 5 4 V CC OUTPUT V MONITORING NODE * D O C 2 = 5 pf 5 kω 5V 9 Ω D 2 D 3 D 4 THE PROBE AND JIG CAPACITANCES ARE INCLUDED IN C AND C 2. I R INPUT I F F(ON) ALL DIODES ARE N9 OR N34. OUTPUT V O 58Ω ma 33Ω ma I F (ON) 5% I F (ON) ma t PLH t PHL V OH.3V VOL *. μf BYPASS - SEE NOTE 9-8 -

9 Figure Typical Propagation Delays vs. Temperature Tp - PROPAGATION DELAY - ns t PLH t PHL Vcc = 2V I F = ma T A - TEMPERATURE - C Figure 7 Typical Logic High Output Voltage vs. Supply Voltage Vo - OUTPUT VOLTAGE - V TA = 25 C IO = -2. ma VCC - SUPPLY VOLTAGE - V Figure 8 Typical Propagation Delay vs. Supply Voltage Tp - PROPAGTION DELAY - ns T A = 25 C t PLH t PHL I F (ma) I F (ma) Vcc - SUPPLY VOLTAGE - V Figure 9 V OH vs. I OH Across Temperatures Voh - HIGH OUTPUT VOLTAGE -V Vcc = 4.5V IF = ma C 25 C -4 C Ioh - HIGH OUTPUT CURRENT - ma Figure V OL vs. I OL Across Temperatures Vol - LOW OUTPUT VOLTAGE - V C 25 C -4 C Iol - LOW OUTPUT CURRENT - ma - 9 -

10 Figure Test Circuit for Common Mode Transient Immunity and Typical Waveforms V FF + - R IN B A 2 3 SHIELD V CM 5 4 V CC. μf OUTPUT V O MONITORING NODE V CM V V OH OUTPUT V O V OL V CM (PEAK) SWITCH AT A: I F = ma V O (MIN.) SWITCH AT B: V F = V V O (MAX.)

11 For product information and a complete list of distributors, please go to our web site: the pulse logo, Connecting everything, Avago Technologies, Avago, and the A logo are among the trademarks of and/or its affiliates in the United States, certain other countries and/or the EU. Copyright 27 by. All Rights Reserved. The term "" refers to Limited and/or its subsidiaries. For more information, please visit reserves the right to make changes without further notice to any products or data herein to improve reliability, function, or design. Information furnished by is believed to be accurate and reliable. However, does not assume any liability arising out of the application or use of this information, nor the application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others. AV2-35EN August 24, 27

High CMR Intelligent Power Module and Gate Drive Interface Optocoupler. Features. Specifications. Applications

ACPL-P80 and ACPL-W80 High CMR Intelligent Power Module and Gate Drive Interface Optocoupler Data Sheet Lead (Pb) Free RoHS fully compliant RoHS fully compliant options available; -xxxe denotes a lead-free