Data Sheet HCPL-3020/HCPL Amp Output Current IGBT Gate Drive Optocoupler. Features. Description. Functional Diagram.

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1 HCPL-/HCPL-. Amp Output Current IGBT Gate Drive Optocoupler Data Sheet Description The HCPL- and HCPL- consist of a GaAsP LED optically coupled to an integrated circuit with a power output stage. These optocouplers are ideally suited for driving power IGBTs and MOSFETs used in motor control inverter applications. The high operating voltage range of the output stage provides the drive voltages required by gate-controlled devices. The voltage and current supplied by this optocoupler makes it ideally suited for directly driving small or medium power IGBTs. For IGBTs with higher ratings, the HCPL-/ (. A), HCPL (. A) or HCPL- (. A) gate drive opto-couplers can be used. Functional Diagram N/C ANODE V CC N/C Features. A maximum peak output current. A minimum peak output current High speed response:. µs maximum propagation delay over temperature range Ultra high CMR: minimum kv/µs at VCM = V Bootstrappable supply current: maximum ma Wide operating temperature range: C to C Wide VCC operating range: V to V over temperature range Available in DIP and SO- packages Safety approvals: UL approval, VRMS for minute CSA approval IEC/EN/DIN EN -- approval VIORM = VPEAK (HCPL-), VIORM = VPEAK (HCPL-) CATHODE V O Applications Isolated IGBT/power MOSFET gate drive N/C SHIELD V EE AC and brushless DC motor drives Industrial inverters Air conditioner Truth Table Washing machine LED OFF V O LOW Induction heater for cooker Switching power supplies (SPS) ON HIGH Note: A. uf bypass capacitor must be connected between pins V CC and V EE. CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and /or degradation which may be induced by ESD.

2 Ordering Information Specify part number followed by option number (if desired). Example: HCPL--XXXX HCPL--XXXX No option = Standard DIP package, per tube = Gull Wing Surface Mount Option, per tube = Tape and Reel Packaging Option = IEC/EN/DIN EN --, VIORM = VPEAK XXXE = Lead Free Option No option = Standard SO- package, per tube = Tape and Reel Packaging Option = IEC/EN/DIN EN --, VIORM = VPEAK XXXE = Lead Free Option Package Outline Drawings HCPL- Standard DIP Package 9. ±. (. ±.). ±. (. ±.) TYPE NUMBER OPTION CODE*. ±. (. ±.) A XXXXZ DATE CODE YYWW.9 (.) MAX.. (.) MAX.. ±. (. ±.). (.) MAX. TYP (. +.) -.). ±. (. ±.).9 (.) MIN.. (.) MAX.. ±. (. ±.). (.) MIN. DIMENSIONS IN MILLIMETERS AND (INCHES). * MARKING CODE LETTER FOR OPTION NUMBERS. "V" = OPTION OPTION NUMBERS AND NOT MARKED. NOTE: FLOATING LEAD PROTUSION IS. mm ( mils) MAX.

3 HCPL- Gull Wing Surface Mount Option 9. ±. (. ±.) Land Pattern Recommendation. (.). ±. (. ±.).9 (.). (.). (.).9 (.) MAX.. (.) MAX.. ±. (. ±.) 9. ±. (. ±.). ±. (. ±.). (.). (.). ±. (. ±.). (.) BSC. ±. (. ±.). ±. (. ±.) NOM. DIMENSIONS IN MILLIMETERS (INCHES). LEAD COPLANARITY =. mm (. INCHES). HCPL- Small Outline SO- Package.9 ±. (. ±.) PIN ONE XXX YWW.99 ±. (. ±.) TYPE NUMBER (LAST DIGITS) DATE CODE NOTE: FLOATING LEAD PROTUSION IS. mm ( mils) MAX. Land Pattern Recommendation.9 (.9).9 (.). ±. (. ±.). (.) BSC. (.) *. ±. (. ±.) X. (.). ±. (. ±.). (.) ~. ±. (.9 ±.) * TOTAL PACKAGE LENGTH (INCLUSIVE OF MOLD FLASH). ±. (. ±.) DIMENSIONS IN MILLIMETERS (INCHES). LEAD COPLANARITY =. mm (. INCHES) MAX.. (.) MIN.. ±. (. ±.) NOTE: FLOATING LEAD PROTUSION IS. mm ( mils) MAX.

4 Solder Reflow Temperature Profile TEMPERATURE ( C) PREHEATING RATE C + C/. C/SEC. REFLOW HEATING RATE. C ±. C/SEC. C C C C + C/. C. C ±. C/SEC. PREHEATING TIME C, 9 + SEC. PEAK TEMP. C SEC. SEC. SEC. PEAK TEMP. C SOLDERING TIME C PEAK TEMP. C TIGHT TYPICAL LOOSE ROOM TEMPERATURE Note: Use of non-chlorine-activated fluxes is highly recommended TIME (SECONDS) Recommended Solder Reflow Temperature Profile (Lead free) TEMPERATURE ( C) Tp TL Tsmax Tsmin +/- C C RAMP-UP C/SEC. MAX. - C ts PREHEAT to SEC. t C to PEAK tp tl TIME WITHIN C of ACTUAL PEAK TEMPERATURE - SEC. RAMP-DOWN C/SEC. MAX. to SEC. TIME (SECONDS) NOTES: THE TIME FROM C to PEAK TEMPERATURE = MINUTES MAX. Tsmax = C, Tsmin = C Note: Use of non-chlorine-activated fluxes is highly recommended

5 Regulatory Information The HCPL-/ has been approved by the following organizations: IEC/EN/DIN EN -- Approved under: IEC --:99 + A: EN --: + A: DIN EN -- (VDE Teil ):-. (Option only) UL Approval under UL, component recognition program up to VISO = VRMS. File E. CSA Approval under CSA Component Acceptance Notice #, File CA. IEC/EN/DIN EN -- Insulation Characteristics (HCPL- and HCPL- Option ) Description Symbol HCPL- HCPL- Unit Installation Classification per DIN VDE /.9, Table for Rated Mains Voltage Vrms I IV I IV for Rated Mains Voltage Vrms I III I III for Rated Mains Voltage Vrms I II Climatic Classification // // Pollution Degree (DIN VDE /.9) Maximum Working Insulation Voltage VIORM Vpeak Input to Output Test Voltage, Method b [] VIORM x. = VPR, % Production Test with tm = sec, Partial Discharge < pc VPR Vpeak Input to Output Test Voltage, Method a [] VIORM x. = VPR, Type and Sample Test, tm = sec, Partial Discharge < pc VPR 9 Vpeak Highest Allowable Overvoltage (Transient Overvoltage tini = sec) VIOTM Vpeak Safety-Limiting Values Maximum Values Allowed in the Event of a Failure. Case Temperature TS C Input Current [] IS, INPUT ma Output Power [] PS, OUTPUT mw Insulation Resistance at TS, VIO = V RS > 9 > 9 Ω. Refer to the optocoupler section of the Isolation and Control Components Designer s Catalog, under Product Safety Regulations section, (IEC/EN/DIN EN --), for a detailed description of Method a and Method b partial discharge test profiles.. Refer to the following figure for dependence of P S and I S on ambient temperature. OUTPUT POWER P S, INPUT CURRENT I S P S (mw) I S (ma) T S CASE TEMPERATURE C

6 Insulation and Safety Related Specifications Parameter Absolute Maximum Ratings Parameter Symbol Min. Max. Units Note Storage Temperature TS C Operating Temperature TA C Average Input Current IF(AVG) ma Peak Transient Input Current (< µs pulse width, pps) IF(TRAN). A Reverse Input Voltage VR V High Peak Output Current IOH(PEAK). A Low Peak Output Current IOL(PEAK). A Supply Voltage VCC VEE. V Output Voltage VO(PEAK). VCC V Output Power Dissipation PO mw Input Power Dissipation PI mw Lead Solder Temperature Solder Reflow Temperature Profile Symbol HCPL- HCPL- Units Conditions Minimum External Air Gap L()..9 mm Measured from input terminals to output (Clearance) terminals, shortest distance through air. Minimum External Tracking L().. mm Measured from input terminals to output (Creepage) terminals, shortest distance path along body. Minimum Internal Plastic Gap.. mm Through insulation distance conductor to (Internal Clearance) conductor, usually the straight line distance thickness between the emitter and detector. Tracking Resistance CTI > > V DIN IEC /VDE Part (Comparative Tracking Index) Isolation Group IIIa IIIa Material Group (DIN VDE, /9, Table ) C for sec.,. mm below seating plane See Package Outline Drawings section Recommended Operating Conditions Parameter Symbol Min. Max. Units Note Power Supply VCC - VEE V Input Current (ON) IF(ON) ma Input Voltage (OFF) VF(OFF).. V Operating Temperature TA C

7 Electrical Specifications (DC) Over recommended operating conditions unless otherwise specified. Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note High Level Output Current IOH. A VO = VCC.. A VO = VCC Low Level Output Current IOL. A VO = VEE +... A VO = VEE + High Level Output Voltage VOH VCC VCC. V IO = ma, Low Level Output Voltage VOL. V IO = ma High Level Supply Current ICCH. ma IO = ma, Low Level Supply Current ICCL. ma IO = ma Threshold Input Current Low to High IFLH ma IO = ma,, VO > V Threshold Input Voltage High to Low VFHL. V Input Forward Voltage VF... V IF = ma Temperature Coefficient of Input DVF/DTA. mv/ C Forward Voltage Input Reverse Breakdown Voltage BVR V IR = µa Input Capacitance CIN pf f = MHz, VF = V Switching Specifications (AC) Over recommended operating conditions unless otherwise specified. Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note Propagation Delay Time to High tplh... µs Rg=Ω, Cg =. nf,, 9 Output Level f = khz, Duty Cycle = %,, IF = ma, VCC = V, Propagation Delay Time to Low tphl... µs Output Level Propagation Delay Difference PDD.. µs Between Any Two Parts or Channels Rise Time tr ns Fall Time tf ns Output High Level Common Mode CMH kv/µs TA = C, VCM = V Transient Immunity Output Low Level Common Mode CML kv/µs Transient Immunity

8 Package Characteristics Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note Input-Output Momentary VISO Vrms TA = C, RH < %, 9 Withstand Voltage Input-Output Resistance RI-O Ω VI-O = V 9 Input-Output Capacitance CI-O. pf Freq = MHz Notes:. Derate linearly above C free air temperature at a rate of. ma/ C.. Maximum pulse width = µs, maximum duty cycle =.%. This value is intended to allow for component tolerances for designs with IO peak minimum =. A. See Application section for additional details on limiting IOL peak.. Derate linearly above C, free air temperature at the rate of. mw/ C.. Input power dissipation does not require derating.. Maximum pulse width = µs, maximum duty cycle =.%.. In this test, VOH is measured with a DC load current. When driving capacitive load VOH will approach VCC as IOH approaches zero amps.. Maximum pulse width = ms, maximum duty cycle = %.. In accordance with UL, each optocoupler is proof tested by applying an insulation test voltage > Vrms for second (leakage detection current limit II-O < µa). This test is performed before % production test for partial discharge (method B) shown in the IEC/EN/DIN EN -- Insulation Characteristics Table, if applicable. 9. Device considered a two-terminal device: pins on input side shorted together and pins on output side shorted together.. PDD is the difference between t PHL and t PLH between any two parts or channels under the same test conditions.. Common mode transient immunity in the high state is the maximum tolerable dv CM/dt of the common mode pulse V CM to assure that the output will remain in the high state (i.e. V O >. V).. Common mode transient immunity in a low state is the maximum tolerable dv CM/dt of the common mode pulse, V CM, to assure that the output will remain in a low state (i.e. V O <. V).. This load condition approximates the gate load of a V/ A IGBT.. The power supply current increases when operating frequency and C g of the driven IGBT increases. (V OH -V CC ) HIGH OUTPUT VOLTAGE DROP V T A TEMPERATURE C (V OH -V CC ) OUTPUT HIGH VOLTAGE DROP V V OL OUTPUT LOW VOLTAGE V I OH OUTPUT HIGH CURRENT A T A TEMPERATURE C Figure. V OH vs. temperature. Figure. V OH vs. I OH. Figure. VOL vs. temperature.

9 .. V OL OUTPUT LOW VOLTAGE DROP V.... I CC SUPPLY CURRENT ma I CC L I CC H I CC SUPPLY CURRENT ma..... I CC L I CC H I OL OUTPUT LOW CURRENT A T A TEMPERATURE C V CC SUPPLY VOLTAGE V Figure. VOL vs. IOL. Figure. ICC vs. temperature. Figure. ICC vs. VCC. I FLH LOW TO HIGH CURRENT THRESHOLD ma T P PROPAGATION DELAY ns T PLH T PHL T P PROPAGATION DELAY ns 9 T A TEMPERATURE C V CC SUPPLY VOLTAGE V I F FORWARD LED CURRENT ma Figure. I FLH vs. temperature. Figure. Propagation delay vs. V CC. Figure 9. Propagation delay vs. I F. T P PROPAGATION DELAY ns - - T PLH T PHL T P PROPAGATION DELAY ns T PLH T PHL T P PROPAGATION DELAY ns T PLH T PHL T A TEMPERATURE C Rg SERIES LOAD RESISTANCE Ω Cg LOAD CAPACITANCE nf Figure. Propagation delay vs. tempera- Figure. Propagation delay vs. R g. Figure. Propagation delay vs. C g. 9

10 V O OUTPUT VOLTAGE V I F FORWARD CURRENT ma - I F FORWARD LED CURRENT ma Figure. Transfer characteristics.... V F FORWARD VOLTAGE V Figure. Input current vs. forward voltage.. I F = to ma + KHz % DUTY CYCLE Ω. µf V O Ω. nf + V CC = to V I F V OUT t r t f 9% % % t PLH t PHL Figure. Propagation delay test circuits and waveforms. V CM V + I F A B. µf V + O V CC = V V V O t δv V CM δt = t V OH SWITCH AT A: I F = ma V O V OL + V CM = V SWITCH AT B: I F = ma Figure. CMR test circuits and waveforms.

11 Applications Information Eliminating Negative IGBT Gate Drive To keep the IGBT firmly off, the HCPL- and HCPL- have a very low maximum VOL specification of. V. Minimizing Rg and the lead inductance from the HCPL- or HCPL- to the IGBT gate and emitter (possibly by mounting the HCPL- or HCPL- on a small PC board directly above the IGBT) can eliminate the need for negative IGBT gate drive in many applications as shown in Figure. Care should be taken with such a PC board design to avoid routing the IGBT collector or emitter traces close to the HCPL- or HCPL- input as this can result in unwanted coupling of transient signals into the input of HCPL- or HCPL- and degrade performance. (If the IGBT drain must be routed near the HCPL- or HCPL- input, then the LED should be reverse biased when in the off state, to prevent the transient signals coupled from the IGBT drain from turning on the HCPL- or HCPL-. + V Ω HCPL-/. µf V CC = V + Rg + HVDC CONTROL INPUT Q -PHASE AC XXX OPEN COLLECTOR Q - HVDC Figure. Recommended LED drive and application circuit for HCPL- and HCPL-.

12 Selecting the Gate Resistor (Rg) for HCPL- Step : Calculate Rg minimum from the IOL peak specification. The IGBT and Rg in Figure can be analyzed as a simple RC circuit with a voltage supplied by the HCPL-. Rg VCC VOL IOLPEAK = -. =. Ω The VOL value of V in the previous equation is the VOL at the peak current of. A. (See Figure ). Step : Check the HCPL- power dissipation and increase Rg if necessary. The HCPL- total power dissipation (PT) is equal to the sum of the emitter power (PE) and the output power (PO). PT = PE + PO PE = IF VF Duty Cycle PO = PO(BIAS) + PO(SWITCHING) = ICC VCC + ESW (Rg;Qg) f = (ICCBIAS + KICC Qg f) VCC + ESW (Rg;Qg) f where KICC Qg f is the increase in ICC due to switching and KICC is a constant of. ma/(nc*khz). For the circuit in Figure with IF (worst case) = ma, Rg =. Ω, Max Duty Cycle = %, Qg = nc, f = khz and TAMAX = C: PE = ma. V. = mw PO = [ ma + (. ma/nc khz) khz nc] V +.mj khz = mw < mw C The value of ma for ICC in the previous equation is the max. ICC over entire operating temperature range. Since PO for this case is less than PO(MAX), Rg =. Ω is alright for the power dissipation. Esw ENERGY PER SWITCHING CYCLE µj Qg = nc Qg = nc Qg = nc Qg = nc Rg GATE RESISTANCE Ω Figure. Energy dissipated in the HCPL- and HCPL- and for each IGBT switching cycle.

13 LED Drive Circuit Considerations for Ultra High CMR Performance Without a detector shield, the dominant cause of optocoupler CMR failure is capacitive coupling from the input side of the optocoupler, through the package, to the detector IC as shown in Figure 9. The HCPL- and HCPL- improve CMR performance by using a detector IC with an optically transparent Faraday shield, which diverts the capacitively coupled current away from the sensitive IC circuitry. However, this shield does not eliminate the capacitive coupling between the LED and optocoupler pins - as shown in Figure. This capacitive coupling causes perturbations in the LED current during common mode transients and becomes the major source of CMR failures for a shielded optocoupler. The main design objective of a high CMR LED drive circuit becomes keeping the LED in the proper state (on or off) during common mode transients. For example, the recommended application circuit (Figure ), can achieve kv/µs CMR while minimizing component complexity. Techniques to keep the LED in the proper state are discussed in the next two sections. C LEDO C LEDP C LEDP C LEDO C LEDN C LEDN SHIELD Figure 9. Optocoupler input to output capacitance model for unshielded optocouplers. Figure. Optocoupler Input to output capacitance model for shielded optocouplers. + V + V SAT C LEDP I LEDP C LEDN. µf + Rg V CC = V + V Q C LEDP C LEDN SHIELD I LEDN SHIELD * THE ARROWS INDICATE THE DIRECTION OF CURRENT FLOW DURING dv CM/dt. + Figure. Not recommended open collector drive circuit. V CM Figure. Equivalent circuit for figure during common mode transient. + V C LEDP C LEDN SHIELD Figure. Recommended LED drive circuit for ultra-high CMR IPM dead time and propagation delay specifications.

14 CMR with the LED On (CMRH) A high CMR LED drive circuit must keep the LED on during common mode transients. This is achieved by overdriving the LED current beyond the input threshold so that it is not pulled below the threshold during a transient. A minimum LED current of ma provides adequate margin over the maximum IFLH of ma to achieve kv/µs CMR. CMR with the LED Off (CMRL) A high CMR LED drive circuit must keep the LED off (VF VF(OFF)) during common mode transients. For example, during a -dvcm/dt transient in Figure, the current flowing through CLEDP also flows through the RSAT and VSAT of the logic gate. As long as the low state voltage developed across the logic gate is less than VF(OFF) the LED will remain off and no common mode failure will occur. The open collector drive circuit, shown in Figure, cannot keep the LED off during a +dvcm/dt transient, since all the current flowing through CLEDN must be supplied by the LED, and it is not recommended for applications requiring ultra high CMR performance. The alternative drive circuit, which likes the recommended application circuit (Figure ), does achieve ultra high CMR performance by shunting the LED in the off state. Dead Time and Propagation Delay Specifications The HCPL- and HCPL- include a Propagation Delay Difference (PDD) specification intended to help designers minimize dead time in their power inverter designs. Dead time is the time high and low side power transistors are off. Any overlap in Ql and Q conduction will result in large currents flowing through the power devices from the high voltage to the low-voltage motor rails. To minimize dead time in a given design, the turn on of LED should be delayed (relative to the turn off of LED) so that under worst-case conditions, transistor Q has just turned off when transistor Q turns on, as shown in Figure. The amount of delay necessary to achieve this condition is equal to the maximum value of the propagation delay difference specification, PDD max, which is specified to be ns over the operating temperature range of to C. Delaying the LED signal by the maximum propagation delay difference ensures that the minimum dead time is zero, but it does not tell a designer what the maximum dead time will be. The maximum dead time is equivalent to the difference between the maximum and minimum propagation delay difference specification as shown in Figure. The maximum dead time for the HCPL- and HCPL- is ms (=. µs (. µs)) over the operating temperature range of C to C. Note that the propagation delays used to calculate PDD and dead time are taken at equal temperatures and test conditions since the optocouplers under consideration are typically mounted in close proximity to each other and are switching identical IGBTs.

15 I LED I LED V OUT Q ON Q OFF V OUT Q ON Q OFF V OUT Q OFF Q ON V OUT Q OFF Q ON I LED I LED t PHL MIN t PHL MAX t PHL MAX tplh MIN PDD* MAX = (t PHL - t PLH ) MAX = t PHL MAX - t PLH MIN *PDD = PROPAGATION DELAY DIFFERENCE NOTE: FOR PDD CALCULATIONS THE PROPAGATION DELAYS ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS. Figure. Minimum LED skew for zero dead time. (t PHL- t PLH ) MAX PDD* MAX t PLH MIN t PLH MAX MAXIMUM DEAD TIME (DUE TO OPTOCOUPLER) = (t PHL MAX - t PHL MIN ) + (t PLH MAX - t PLH MIN ) = (t PHL MAX - t PLH MIN ) (t PHL MIN - t PLH MAX ) = PDD* MAX PDD* MIN *PDD = PROPAGATION DELAY DIFFERENCE NOTE: FOR DEAD TIME AND PDD CALCULATIONS ALL PROPAGATION DELAYS ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS. Figure. Waveforms for dead time. For product information and a complete list of distributors, please go to our web site: Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies, Pte. in the United States and other countries. Data subject to change. Copyright Avago Technologies Pte. All rights reserved. Obsoletes 99-9EN AV-EN - August,

0.4 Amp Output Current IGBT Gate Drive Optocoupler. Features. Applications

0.4 Amp Output Current IGBT Gate Drive Optocoupler. Features. Applications HCPL-1J. Amp Output Current IGBT Gate Drive Optocoupler Data Sheet Lead (Pb) Free RoHS fully compliant RoHS fully compliant options available; -xxxe denotes a lead-free product Description The HCPL-1J