ACSL-6xx0 Multi-Channel and Bi-Directional, 15 MBd Digital Logic Gate Optocoupler

Transcription

1 ACSL-xx Multi-Channel and Bi-Directional, MBd Digital Logic Gate Optocoupler Data Sheet Description ACSL-xx are truly isolated, multi-channel and bi-directional, high-speed optocouplers. Integration of multiple optocouplers in monolithic form is achieved through patented process technology. These devices provide full duplex and bi-directional isolated data transfer and communication capability in compact surface mount packages. Available in Mbd speed option and wide supply voltage range. These high channel density make them ideally suited to isolating data conversion devices, parallel buses and peripheral interfaces. They are available in -pin and pin narrow-body SOIC package and are specified over the temperature range of - C to + C. Applications Full duplex communication Isolated line receiver Computer-peripheral interfaces Microprocessor system interfaces Digital isolation for A/D and D/A conversion Switching power supply Instrument input/output isolation Ground loop elimination Pulse transformer replacement Features Available in dual, triple and quad channel configurations Bi-directional Wide supply voltage range.v to.v High-speed: MBd typical, MBd minimum kv/µs minimum Common Mode Rejection (CMR) at Vcm = V LSTTL/TTL compatible Safety and regulatory approvals (Pending) Vrms for min per UL77 CSA Component Acceptance IEC/EN/DIN EN 77-- Pin narrow-body SOIC package for triple and quad channel - to C temperature range CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation, which may be induced by ESD.

2 Device Selection Guide Device Number Channel Configuration Package ACSL- Dual, Bi-Directional` -pin Small Outline ACSL-* Triple, All-in-One -pin Small Outline ACSL-* Triple, Bi-Directional, / -pin Small Outline ACSL- Quad, All-in-One -pin Small Outline ACSL-* Quad, Bi-Directional, / -pin Small Outline ACSL-* Quad, Bi-Directional, / -pin Small Outline * Advanced Information Ordering Information A C S L - X X - X Y Z E Lead Free Option Channel Configuration (Refer to the Device Selection Guide) R = SO- Package, units per tube T = SO- Package, units per tube = IEC/EN/DIN EN 77--, VIORM = V peak Option = Tape and Reel Packaging Option, units per reel for SO- Package and units per reel for SO- Package Pin Description Symbol Description Symbol Description V DD Power Supply GND Power Supply Ground V DD Power Supply GND Power Supply Ground ANODE x LED Anode NC Not Connected CATHODE x LED Cathode V OX Output Signal Truth Table (Positive Logic) LED ON OFF OUTPUT L H

3 Functional Diagrams ACSL- - Dual-Ch, Bi-Dir ACSL- - Triple-Ch, All-in-One* ACSL- - Triple-Ch, Bi-Dir (/)* ACSL- - Quad-Ch, All-in-One ACSL- - Quad-Ch, Bi-Dir (/)* ACSL- - Quad-Ch, Bi-Dir (/)* * Advanced Information

4 Schematic Diagrams The ACSL-xx series optocouplers feature the GaAsP LEDs with proprietary back emission design. They offer the designer a broad range of input drive current, from 7 ma to ma, thus providing greater flexibility in designing the drive circuit. The output detector integrated circuit (IC) in the optocoupler consists of a photodiode at the input of a two-stage amplifier that provides both high gain and high bandwidth. The secondary amplifier stage of the detector IC feeds into an open collector Schottky-clamped transistor. The entire output circuit is electrically shielded so that any commonmode transient capacitively coupled from the LED side of the optocoupler is diverted from the photodiode to ground. With this electric shield, the optocoupler can withstand transients that slopes up to,v/µs, and amplitudes up to,v. ACSL- - Dual-Ch, Bi-Dir GND CATHODE ANODE ACSL- - Triple-Ch, All-in-One* ANODE GND VDD Vo Vo VDD CATHODE 7 VDD Vo ANODE ANODE Vo GND CATHODE CATHODE ANODE Vo CATHODE 9 VDD GND ACSL- - Triple-Ch, Bi-Dir (/)* GND ANODE Vo VDD CATHODE ANODE VDD Vo CATHODE ANODE 7 Vo CATHODE 9 GND * Advanced Information

5 Schematic Diagrams, continued ACSL- - Quad-Ch, All-in-One ACSL- - Quad-Ch, Bi-Dir (/)* ANODE GND VDD Vo GND CATHODE CATHODE CATHODE Vo VDD ANODE GND ANODE Vo Vo CATHODE ANODE ANODE Vo CATHODE Vo CATHODE ANODE ANODE 7 Vo CATHODE 7 Vo CATHODE 9 VDD GND ANODE 9 VDD GND ACSL- - Quad-Ch, Bi-Dir (/)* GND ANODE Vo CATHODE ANODE Vo VDD CATHODE ANODE VDD Vo CATHODE ANODE 7 Vo CATHODE 9 GND * Advanced Information

6 Package Outline Drawings ACSL- Small Outline SO- Package.9 (.).97 (.) 7. (.). (.). (.).7 (.). (.). (.). (.7).9 (.7). (.). (.). (.). (.). (.). (.) x. (.). (.7). (.9). (.) DIMENSIONS: INCHES (MILLIMETERS) MIN MAX ACSL-*, ACSL-*, ACSL-, ACSL-* and ACSL-* Small Outline SO- Package. (9.).9 (9.999). (.79). (.97). (.).7 (.9). (.). (.). (.7). (.77). (.9). (.9). (.). (.) x ß. (.7). (.) TYP. (.). (.). (.). (.9). (.). (.7) DIMENSIONS: INCHES (MILLIMETERS) MIN MAX

7 Solder Reflow Temperature Profile TEMPERATURE ( C) PREHEATING RATE C + C/. C/SEC. REFLOW HEATING RATE. C ±. C/SEC. C C C C + C/. C. C ±. C/SEC. PREHEATING TIME C, 9 ± SEC. PEAK TEMP. C SEC. SEC. SOLDERING TIME C SEC. PEAK TEMP. C PEAK TEMP. C ROOM TEMPERATURE TIME (SECONDS) TIGHT TYPICAL LOOSE Recommended Pb-free IR Profile SEC. 7

8 Regulatory Information Insulation and Safety Related Specifications Parameter Symbol Value Units Conditions Minimum External Air Gap (Clearance) L(I).9 mm Measured from input terminals to output terminals, shortest distance through air Minimum Externa l Tracking(Creepage) L(I). mm Measured from input terminals to output terminals, shortest distance path through body Minimum Internal Plastic Gap (Internal Clearance). mm Insulation thickness between emitter and detector; also known as distance through insulation Tracking Resistance (Comparative Tracking Index) CTI 7 Volts DIN IEC /VDE Part Isolation Group IIIa Material Group (DIN VDE, /9, Table ) IEC/EN/DIN EN 77-- Insulation Related Characteristics (Option XX Only) Description Symbol ACSL-XX-XX Units Installation Classification per DIN VDE /.9, Table for rated mains voltage V rms for rated mains voltage V rms I-IV I-III Climatic Classification // Pollution Degree (DIN VDE /.9) Maximum Working Insulation Voltage V IORM V peak Input to Output Test Voltage, Method b * V PR V peak V IORM x.7 = V PR, % Production Test with t m = sec, Partial Discharge < pc Input to Output Test Voltage, Method a * V PR V peak V IORM x. = V PR, Type and Sample Test, T m = sec, Partial Discharge < pc Highest Allowable Overvoltage * V IOTM V peak (Transient Overvoltage, t ini = sec) Safety Limiting Values (Maximum values allowed in the event of a failure) Case Temperature T S 7 C Input Current I S,INPUT ma Output Power P S,OUTPUT mw Insulation Resistance at T S, V IO = V R IO 9 Ω *Refer to the front of the optocoupler section of the current catalog, under Product Safety Regulations section, IEC/EN/DIN EN 77--, for a detailed description. Note: Isolation characteristics are guaranteed only within the safety maximum ratings, which must be ensured by protective circuits in application.

9 Absolute Maximum Ratings Parameter Symbol Min. Max. Units Storage Temperature T s - C Operating Temperature T A - C Supply Voltage ( Minute Maximum) V DD, V DD 7 V Reverse Input Voltage (Per Channel) V R V Output Voltage (Per Channel) V O 7 V Average Forward Input Current [] (Per Channel) I F ma Output Current (Per Channel) I O ma Input Power Dissipation [] (Per Channel) P mw Output Power Dissipation [] (Per Channel) P O SO package mw SO package mw Recommended Operating Conditions Parameter Symbol Min. Max. Units Operating Temperature T A - C Input Current, Low Level [] I FL µa Input Current, High Level [] I FH 7 ma Supply Voltage V DD, V DD.. V Fan Out (at R L = kω) N TTL Loads Output Pull-up Resistor R L k Ω Notes:. Peaking circuits may produce transient input currents up to ma, ns max. pulse width, provided average current does not exceed its max. values.. Derate total package power dissipation, PT linearly above + C free-air temperature at a rate of. mw/ C for the SO package mounted on low conductivity board per JESD -. Derate total package power dissipation, PT linearly above +7 C free-air temperature at a rate of 7.9 mw/ C for the SO package mounted on low conductivity board per JESD -. PT= number of channels multiplied by (PI+PO).. The off condition can be guaranteed by ensuring that V FL.V.. The initial switching threshold is 7 ma or less. It is recommended that minimum ma be used for best performance and to permit guardband for LED degradation. 7 Is (ma) Ps (mw) Output Power-Ps Input Power-lp 7 7 Ts-Case Temperature, C 9

10 Electrical Specifications Over recommended operating range (.V V DD.V,.V V DD.V, T A = - C to + C) unless otherwise specified. All typical specifications are at T A = + C, V DD = V DD = +.V. Parameter Symbol Min. Typ. Max. Units Test Conditions Input Threshold Current I TH.7 7. ma I OL(Sinking) = ma, V O =.V High Level Output Current I OH.7. µa I F = µa, V O =.V Low Level Output Voltage V OL.. V I OL(Sinking) = ma, I F = 7mA High Level Supply Current (per channel) I DDH.. ma I F = ma Low Level Supply Current (per channel) I DDL. 7. ma I F = ma Input Forward Voltage V F... V I F = ma, T A = C Input Reverse Breakdown Voltage BV R. V I R = µa Input Diode Temperature Coefficient V F / T A -. mv/ C I F = ma Input Capacitance C IN pf f = MHz, V F = V Switching Specifications Over recommended operating range (.V V DD.V,.V V DD.V, I F =. ma, T A = - C to + C) unless otherwise specified. All typical specifications are at T A = + C, V DD = V DD = +.V. Parameter Symbol Min. Typ. Max. Units Test Conditions Maximum Data Rate MBd R L = Ω, C L = pf Pulse Width t PW ns R L = Ω, C L = pf Propagation Delay Time to Logic High Output Level [] t PLH ns R L = Ω, C L = pf Propagation Delay Time to Logic Low Output Level [] t PHL ns R L = Ω, C L = pf Pulse Width Distortion t PHL t PLH PWD ns R L = Ω, C L = pf Propagation Delay Skew [7] t PSK ns R L = Ω, C L = pf Output Rise Time ( 9%) t R ns R L = Ω, C L = pf Output Fall Time ( 9%) t F ns R L = Ω, C L = pf Logic High Common Mode Transient Immunity [] CM H kv/µs V cm = V, I F = ma, V O =.V, R L = Ω, T A = C Logic Low Common Mode Transient Immunity [] CM L kv/µs V cm = V, I F = ma, V O =.V, R L = Ω, T A = C Notes:. t PLH is measured from the. ma level on the falling edge of the input pulse to the.v level on the rising edge of the output pulse.. t PHL is measured from the. ma level on the rising edge of the input pulse to the.v level on the falling edge of the output pulse. 7. t PSK is equal to the worst case difference in t PHL and/or t PLH that will be seen between units at any given temperature and specified test conditions.. CM H is the maximum common mode voltage slew rate that can be sustained while maintaining V O >.V. CM L is the maximum common mode voltage slew rate that can be sustained while maintaining V O <.V. The common mode voltage slew rates apply to both rising and falling common mode voltage edges.

11 Electrical Specifications Over recommended operating range (.V V DD.V,.V V DD.V, T A = - C to + C) unless otherwise specified. All typical specifications are at T A = + C, V DD = V DD = +.V. Parameter Symbol Min. Typ. Max. Units Test Conditions Input Threshold Current I TH.7 7. ma I OL(Sinking) = ma, V O =.V High Level Output Current I OH.. µa I F = µa, V O =.V Low Level Output Voltage V OL.. V I OL(Sinking) = ma, I F =7 ma High Level Supply Current (per channel) I DDH. 7. ma I F = ma Low Level Supply Current (per channel) I DDL.. ma I F = ma Input Forward Voltage V F... V I F = ma, T A = C Input Reverse Breakdown Voltage BV R. V I R = µa Input Diode Temperature Coefficient V F / T A -. mv/ C I F = ma Input Capacitance C IN pf f = MHz, V F = V Switching Specifications Over recommended operating range (.V V DD.V,.V V DD.V, I F =. ma, T A = - C to + C) unless otherwise specified. All typical specifications are at T A =+ C, V DD = V DD = +.V. Parameter Symbol Min. Typ. Max. Units Test Conditions Maximum Data Rate MBd R L = Ω, C L = pf Pulse Width t PW ns R L = Ω, C L = pf Propagation Delay Time to Logic High Output Level [] t PLH ns R L = Ω, C L = pf Propagation Delay Time to Logic Low Output Level [] t PHL ns R L = Ω, C L = pf Pulse Width Distortion t PHL t PLH PWD ns R L = Ω, C L = pf Propagation Delay Skew [7] t PSK ns R L = Ω, C L = pf Output Rise Time ( 9%) t R ns R L = Ω, C L = pf Output Fall Time ( 9%) t F ns R L = Ω, C L = pf Logic High Common Mode Transient Immunity [] CM H kv/µs V cm = V, I F = ma, V O =.V, R L =Ω, T A = C Logic Low Common Mode Transient Immunity [] CM L kv/µs V cm = V, I F = ma, V O =.V, R L = Ω, T A = C Notes:. t PLH is measured from the. ma level on the falling edge of the input pulse to the.v level on the rising edge of the output pulse.. t PHL is measured from the. ma level on the rising edge of the input pulse to the.v level on the falling edge of the output pulse. 7. t PSK is equal to the worst case difference in t PHL and/or t PLH that will be seen between units at any given temperature and specified test conditions.. CM H is the maximum common mode voltage slew rate that can be sustained while maintaining V O >.V. CM L is the maximum common mode voltage slew rate that can be sustained while maintaining V O <.V. The common mode voltage slew rates apply to both rising and falling common mode voltage edges.

12 Package Characteristics All specifications are at T A =+ C. Parameter Symbol Min. Typ. Max. Units Test Conditions Input-Output Momentary SO V ISO V RMS RH %, t = min Withstand Voltage [9] SO V ISO RH %, t = min Input-Output Insulation [] [] SO I I-O µa % RH, t= sec, V I-O = kv DC SO I I-O % RH, t= sec, V I-O =kv DC Input-Output Resistance [] SO R I-O 9 Ω V I-O = V DC SO R I-O 9 V I-O = V DC Input-Output Capacitance [] SO C I-O.7 pf f = MHz SO C I-O.7 f = MHz Input-Input Insulation SO I I-I. µa RH %, t = sec, V I-I = V Leakage Current [] SO I I-I. RH %, t = sec, V I-I = V Input-Input Resistance [] SO R I-I Ω RH %, t= sec, V I-I = V SO R I-I RH %, t = sec, V I-I =V Input-Input Capacitance [] SO C I-I. pf f = MHz SO C I-I. f = MHz Electrostatic Discharge Sensitivity This product has been tested for electrostatic sensitivity to the limits stated in the specifications. However, Avago recommends that all integrated circuits be handled with appropriate care to avoid damage. Damage caused by inappropriate handling or storage could range from performance degradation to complete failure. Notes: 9. V ISO is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. For continuous voltage rating, refer to the IEC/EN/DIN EN 77-- Insulation Characteristics Table (if applicable), the equipment level safety specification or Avago Application Note 7 entitled Optocoupler Input-Output Endurance Voltage.. Measured between each input pair shorted together and all output connections for that channel shorted together.. In accordance to UL77, each optocoupler is proof tested by applying an insulation test voltage Vrms for sec (leakage detection current limit, I I-O µa). This test is performed before the % production test for partial discharge (Method b) shown in the IEC/EN/DIN EN 77-- Insulation Characteristics Table, if applicable.. Measured between inputs with the LED anode and cathode shorted together.

13 Typical Performance ITH - INPUT THRESHOLD CURRENT - ma RL = KΩ RL = Ω V DD =.V V O =.V RL = KΩ ITH - INPUT THRESHOLD CURRENT - ma RL = KΩ RL = Ω V DD =.V V O =.V RL = KΩ IOL - LOW LEVEL OUTPUT CURRENT - ma 7 IF = 7. ma VDD =.V VOL =.V T A - TEMPERATURE - C Figure. Typical input threshold current vs. temperature for.v operation TA - TEMPERATURE - C Figure. Typical input threshold current vs. temperature for V operation T A - TEMPERATURE - C Figure. Typical low level output current vs. temperature for.v operation. IOL- LOW LEVEL OUTPUT CURRENT - ma 7 IF = 7. ma V DD =.V V OL =.V IF = ma IOH- HIGH LEVEL OUTPUT CURRENT -µa V DD =.V V O =.V IF = µa IOH- HIGH LEVEL OUTPUT CURRENT -µa V DD =.V V O =.V IF = µa T A - TEMPERATURE - C Figure. Typical low level output current vs. temperature for V operation TA - TEMPERATURE - C Figure. Typical high level output current vs. temperature for.v operation T A - TEMPERATURE - C Figure. Typical high level output current vs. temperature for V operation. VOL- LOW LEVEL OUTPUT VOLTAGE - V IO = ma V DD =.V IF = 7 ma TA - TEMPERATURE - C VOL - LOW LEVEL OUTPUT VOLTAGE - V IO = ma V DD =.V IF = 7 ma TA - TEMPERATURE - C IDD- SUPPLY CURRENT PER CHANNEL - ma 9 7 IDDH IF = ma V DD =.V IDDL IF = ma TA - TEMPERATURE - C Figure 7. Typical low level output voltage vs. temperature for.v operation. Figure. Typical low level output voltage vs. temperature for V operation. Figure 9. Typical supply current per channel vs. temperature for.v operation.

14 Typical Performance, continued IDD- SUPPLY CURRENT PER CHANNEL - ma 9 7 IDDH IF = ma V DD =.V IDDL IF = ma TA - TEMPERATURE - C Figure. Typical supply current per channel vs. temperature for V operation. IF - FORWARD CURRENT - ma.. I F + V F V F - FORWARD VOLTAGE - V Figure. Typical input diode forward characteristics. T A = C tp - PROPAGATION DELAY - ns 9 t PLH, R L = Ω t PHL, R L = Ω V DD =.V IF =. ma TA - TEMPERATURE - C Figure. Typical propagation delay vs. temperature for.v operation. tp - PROPAGATION DELAY - ns 9 t PLH, R L = Ω t PHL, R L = Ω V DD =.V I F =. ma T A - TEMPERATURE - C Figure. Typical propagation delay vs. temperature for V operation. PWD - PULSE WIDTH DISTORTION - ns R L = Ω V DD =.V I F =. ma T A - TEMPERATURE - C Figure. Typical pulse width distortion vs. temperature for.v operation. PWD - PULSE WIDTH DISTORTION - ns R L = Ω V DD =.V I F =. ma T A - TEMPERATURE - C Figure. Typical pulse width distortion vs. temperature for V operation.

15 Test Circuits ACSL-.V or V INPUT MONITORING NODE PULSE GEN. Zo = Ω tf = tr = ns IF 7.µF BYPASS RL C L* OUTPUT Vo MONITORING NODE *C L IS APPROXIMATELY pf WHICH INCLUDES PROBE AND STRAY WIRING CAPACITANCE I F =. ma INPUT I F I F =. ma t PHL t PLH 9% 9% OUTPUT Vo.V % % t F t R Figure. Test circuit for t PHL. t PLH, t F, and t R. IF ACSL- B.V or V A.µF BYPASS R L OUTPUT Vo MONITORING NODE V FF 9 + _ PULSE GEN. Zo = Vcm (peak) Vcm V SWITCH AT POSITION "A": IF = ma V Vo Vo (min.) SWITCH AT POSITION "B": IF = ma Vo. V CM H Vo (max.) CM L Figure 7. Test circuit for common mode transient immunity and typical waveforms.

16 Application Information ON and OFF Conditions The ACSL-xx series has the ON condition defined by current, and the OFF condition defined by voltage. In order to guarantee that the optocoupler is OFF, the forward voltage across the LED must be less than or equal to. volt for the entire operating temperature range. This has direct implications for the input drive circuit. If the design uses a TTL gate to drive the input LED, then one has to ensure that the gate output voltage is sufficient to cause the forward voltage to be less than. volt. The typical threshold current for the ACSL-xx series optocouplers is.7 ma; however, this threshold could increase over time due to the aging effects of the LED. Drive circuit arrangements must provide for the ON state LED forward current of at least 7 ma, or more if faster operation is desired. Maximum Input Current and Reverse Voltage The average forward input current should not exceed the ma Absolute Maximum Rating as stated; however, peaking circuits with transient input currents up to ma are allowed provided the average current does not exceed ma. If the input current maximum rating is exceeded, the local temperature of the LED can rise, which in turn may affect the longterm reliability of the device. When designing the input circuit, one must also ensure that the input reverse voltage does not exceed V. If the optocoupler is subjected to reverse voltage transients or accidental situations that may cause a reverse voltage to be applied, thus an anti-parallel diode across the LED is recommended. Suggested Input Circuits for Driving the LED Figures, 9, and show some of the several techniques for driving the ACSL-xx LED. Figure shows the recommended circuit when using any type of TTL gate. The buffer PNP transistor allows the circuit to be used with TTL or CMOS gates that have low sinking current capability. One advantage of this circuit is that there is very little variation in power supply current due to the switching of the optocoupler LED. This can be important in high-resolution analog-to-digital (A/D) systems where ground loop currents due to the switching of the LEDs can cause distortion in the A/D output. Ω Figure. TTL interface circuit for the ACSL-xx.

17 With a CMOS gate to drive the optocoupler, the circuit shown in Figure 9 can be used. The diode in parallel to the current limiting resistor speeds the turn-off of the optocoupler LED. Any HC or HCT series CMOS gate can be used in this circuit. Ω Figure 9. CMOS drive circuit for the ACSL-xx. For high common-mode rejection applications, the drive circuit shown in Figure is recommended. In this circuit, only an open-collector TTL, or an open drain CMOS gate can be used. This circuit drives the optocoupler LED with a ohm current-limiting resistor to ensure that an I F of 7 ma is applied under worst case conditions and thus guarantee the, V/µs optocoupler common mode rejection rating. The designer can obtain even higher common-mode rejection performance than, V/µs by driving the LED harder than 7 ma. Phase Relationship to Input The output of the optocoupler is inverted when compared to the input. The input is defined to be logic HIGH when the LED is ON. If there is a design that requires the optocoupler to behave as a non-inverting gate, then the series input drive circuit shown in Figure 9 can be used. This input drive circuit has an inverting function, and since the optocoupler also behaves as an inverter, the total circuit is noninverting. The shunt drive circuits shown in Figures and will cause the optocoupler to function as an inverter. Figure. High voltage switching with ACSL-xx. Current and Voltage Limitations The absolute maximum voltage allowable at the output supply voltage pin and the output voltage pin of the optocoupler is 7 volts. However, the recommended maximum voltage at these two pins is. volts. The output sinking current should not exceed ma in order to make the Low Level Output Voltage be less than. volt. If the output voltage is not a consideration, then the absolute maximum current allowed through the ACSL-xx is ma. If the output requires switching either higher currents or voltages, output buffer stages as shown in Figures and are suggested. Ω Figure. High CMR drive circuit for the ACSL-xx. Figure. High voltage and high current switching with ACSL-xx. 7

18 Propagation Delay, Pulse-Width Distortion and Propagation Delay Skew Propagation delay is a figure of merit which describes how quickly a logic signal propagates through a system. The propagation delay from low to high (t PLH ) is the amount of time required for an input signal to propagate to the output,causing the output to change from low to high. Similarly,the propagation delay from high to low (t PHL ) is the amount of time required for the input signal to propagate to the output causing the output to change from high to low (see Figure ). Pulse-width distortion (PWD) results when t PLH and t PHL differ in value. PWD is defined as the difference between t PLH and t PHL and often determines the maximum data rate capability of a transmission system. PWD can be expressed in percent by dividing the PWD (in ns) by the minimum pulse width (in ns) being transmitted. Typically, PWD on the order of -% of the minimum pulse width is tolerable; the exact figure depends on the particular application (RS, RS, T-l, etc.). Propagation delay skew,t PSK, is an important parameter to consider in parallel data applications where synchronization of signals on parallel data lines is a concern. If the parallel data is being sent through a group of optocouplers, differences in propagation delays will cause the data to arrive at the outputs of the optocouplers at different times. If this difference in propagation delays is large enough, it will determine the maximum rate at which parallel data can be sent through the optocouplers. Propagation delay skew is defined as the difference between the minimum and maximum propagation delays,either t PLH or t PHL, for any given group of optocouplers which are operating under the same conditions (i.e., the same drive current, supply voltage, output load, and operating temperature). As illustrated in Figure, if the inputs of a group of optocouplers are switched either ON or OFF at the same time, t PSK is the difference between the shortest propagation delay,either t PLH or tphl, and the longest propagation delay,either t PLH or t PHL. As mentioned earlier,t PSK can determine the maximum parallel data transmission rate. Figure is the timing diagram of a typical parallel data application with both the clock and the data lines being sent through optocouplers. The figure shows data and clock signals at the inputs and outputs of the optocouplers. To obtain the maximum data transmission rate, both edges of the clock signal are being used to clock the data;if only one edge were used, the clock signal would need to be twice as fast. Propagation delay skew represents the uncertainty of where an edge might be after being sent through an optocoupler. Figure shows that there will be uncertainty in both the data and the clock lines. It is important that these two areas of uncertainty not overlap, otherwise the clock signal might arrive before all of the data outputs have settled,or some of the data outputs may start to change before the clock signal has arrived. From these considerations, the absolute minimum pulse width that can be sent through optocouplers in a parallel application is twice t PSK. A cautious design should use a slightly longer pulse width to ensure that any additional uncertainty in the rest of the circuit does not cause a problem. The t PSK specified optocouplers offer the advantages of guaranteed specifications for propagation delays, pulsewidth distortion and propagation delay skew over the recommended temperature, input current, and power supply ranges. Figure. Propagation delay skew t PSK. Figure. Parallel data transmission example.

19 For product information and a complete list of distributors, please go to our web site: Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies, Pte. in the United States and other countries. Data subject to change. Copyright Avago Technologies Pte. All rights reserved. Obsoletes 99-EN 99-9EN January,