HCPL-0720, HCPL-7720, HCPL-0721, and HCPL-7721

Transcription

1 Data Sheet HCPL-7, HCPL-77, HCPL-7, and HCPL-77 Description Available in either an 8-pin DIP or SO-8 package style respectively, the HCPL-77X or HCPL-7X optocouplers utilize the latest CMOS IC technology to achieve outstanding performance with very low power consumption. The HCPL-77X/7X require only two bypass capacitors for complete CMOS compatability. Basic building blocks of the HCPL-77X/7X are a CMOS LED driver IC, a high-speed LED, and a CMOS detector IC. A CMOS logic input signal controls the LED driver IC, which supplies current to the LED. The detector IC incorporates an integrated photodiode, a high-speed transimpedance amplifier, and a voltage comparator with an output driver. Features +V CMOS compatibility -ns max propagation delay skew High speed: MBd -ns max propagation delay -kv/μs minimum common mode rejection to +8 C temperature range Safety and regulatory approvals: UL recognized 7 V rms for min. per UL 77 V rms for min. per UL 77 (for HCPL-77X option ) CSA component acceptance notice # IEC/EN/DIN EN 77-- V IORM = V peak for HCPL-77X option V IORM = 7 V peak for HCPL-7X option CAUTION! It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD. The components featured in this data sheet are not to be used in military or aerospace applications or environments. Applications Digital fieldbus isolation: CC-Link, DeviceNet, PROFIBUS, SDS AC plasma display panel level shifting Multiplexed data transmission Computer peripheral interface Microprocessor system interface October, 7

2 Functional Diagram Truth Table V I Input LED V O Output **V DD 8 V DD ** H OFF H L ON L V I 7 NC* I O * V O LED GND SHIELD GND * Pin is the anode of the internal LED and must be left unconnected for guaranteed data sheet performance. Pin 7 is not connected internally. ** A.-μF to.-μf bypass capacitor must be connected as close as possible between pins and, and and 8. Selection Guide 8-Pin DIP ( Mil) Small Outline SO-8 Data Rate PWD HCPL-77 HCPL-7 MB ns HCPL-77 HCPL-7 MB 8 ns Ordering Information HCPL-7, HCPL-7, HCPL-77, and HCPL-77 are UL Recognized with 7 V rms for minute per UL77. Option Part Number RoHS Compliant Non RoHS Compliant Package Surface Mount Gull Wing Tape & Reel UL Vrms/ Minute rating IEC/EN/DIN EN 77-- Quantity HCPL-77 HCPL-77 HCPL-7 HCPL-7 -E no option mil per tube -E # DIP-8 X X per tube -E # X X X per reel -E - X per tube -E - X X X per tube -E - X X X X per reel -E # X per tube -E # X X X per tube -E # X X X X per reel -E no option SO-8 X X per tube -E # X X X per reel -E # X X X per tube -E # X X X X per reel

3 To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. Example : HCPL-77-E to order product of Gull Wing Surface Mount package in Tape and Reel packaging with IEC/EN/DIN EN 77-- Safety Approval and RoHS compliant. Example : HCPL-7 to order product of Small Outline SO-8 package in Tube packaging and non RoHS compliant. Option data sheets are available. Contact your sales representative or authorized distributor for information. NOTE: The notation #XXX is used for existing products, while (new) products launched since July, and RoHS compliant will use -XXXE. Package Outline Drawing HCPL-77X 8-Pin DIP Package 9. ±. (.8 ±.) 7. ±. (. ±.) AVAGO LEAD-FREE DATE CODE PIN 8 7 A NNNN YYWW EEE Z P DEVICE PART NUMBER TEST RATING CODE UL LOGO SPECIAL PROGRAM CODE LOT ID. ±. (. ±.).9 (.7) MAX..78 (.7) MAX.. ±. (. ±.).7 (.8) MAX. TYP (. +.) -.).8 ±. (. ±.). (.) MIN..9 (.) MIN.. (.) MAX.. ±. (. ±.) DIMENSIONS IN MILLIMETERS (INCHES). *MARKING CODE LETTER FOR OPTION NUMBERS "L" = OPTION "V" = OPTION OPTION NUMBERS AND NOT MARKED. NOTE: FLOATING LEAD PROTRUSION IS. mm ( mils) MAX.

4 HCPL-77X Package with Gull Wing Surface Mount Option 9. ±. (.8 ±.) LAND PATTERN RECOMMENDATION. (.) 8 7. ±. (. ±.).9 (.).7 (.). (.8).9 (.7) MAX..78 (.7) MAX.. ±. (. ±.) 9. ±. (.8 ±.) 7. ±. (. ±.) (. +.) -.).8 ±. (. ±.). (.) BSC DIMENSIONS IN MILLIMETERS (INCHES). LEAD COPLANARITY =. mm (. INCHES).. ±. (. ±.) NOTE: FLOATING LEAD PROTRUSION IS. mm ( mils) MAX.. ±. (. ±.) NOM. HCPL-7X Outline Drawing (Small Outline SO-8 Package) LAND PATTERN RECOMMENDATION.9 (.7). (.).97.7 (. ±.) 8 7 DEVICE PART NUMBER NNNN Z LEAD-FREE PIN EEE YYWW TEST RATING CODE DATE CODE LOT ID.99 ±. (. ±.8).9 (.) 7.9 (.9). ±.7 (. ±.).7 (.) BSC.7 (.) *.8 ±.7 (. ±.) 7 X. (.7).7 ±.7 (. ±.). (.) ~ 7.8 ±. (.9 ±.) * Total package length (inclusive of mold flash).7 ±. (. ±.) Dimensions in Millimeters (Inches). Note: Floating lead protrusion is. mm ( mils) max. Lead coplanarity =. mm (. inches) max. Option number not marked.. ±. (.8 ±.). (.) MIN.

5 Reflow Soldering Profile Recommended reflow condition as per JEDEC Standard, J-STD- (latest revision). Non-Halide Flux should be used. Regulatory Information The HCPL-77X/7X have been approved by the following organizations: UL Recognized under UL77, component recognition program, File E. CSA Approval under CSA Component Acceptance Notice #, File CA88. IEC/EN/DIN EN 77-- Insulation and Safety Related Specifications Value Parameter Symbol 77X 7X Unit Conditions Minimum External Air Gap L(I) 7..9 mm Measured from input terminals to output terminals, (Clearance) shortest distance through air. Minimum External Tracking L(I) 7..8 mm Measured from input terminals to output terminals, (Creepage) shortest distance path along body. Minimum Internal Plastic Gap.8.8 mm Insulation thickness between emitter and detector; (Internal Clearance) also known as distance through insulation. Tracking Resistance CTI 7 7 V DIN IEC /VDE Part. (Comparative Tracking Index) Isolation Group IIIa IIIa Material Group (DIN VDE, /89, Table ). All data sheets report the creepage and clearance inherent to the optocoupler component itself. These dimensions are needed as a starting point for the equipment designer when determining the circuit insulation requirements. However, once mounted on a printed circuit board, minimum creepage and clearance requirements must be met as specified for individual equipment standards. For creepage, the shortest distance path along the surface of a printed circuit board between the solder fillets of the input and output leads must be considered. There are recommended techniques such as grooves and ribs, which may be used on a printed circuit board to achieve desired creepage and clearances. Creepage and clearance distances will also change depending on factors such as pollution degree and insulation level.

6 IEC/EN/DIN EN 77-- Insulation Characteristics (Option ) Characteristic HCPL-77 HCPL-7 Description Symbol HCPL-77 HCPL-7 Installation Classification per DIN VDE /9, Table For Rated Mains Voltage V rms I IV I IV For Rated Mains Voltage V rms I IV I III For Rated Mains Voltage V rms I IV I III Climatic Classification /8/ /8/ Pollution Degree (DIN VDE /9) Unit Maximum Working Insulation Voltage V IORM 7 V peak Input-to-Output Test Voltage, Method b a V IORM x.87 = V PR, % Production Test with t m = s, Partial Discharge < pc Input-to-Output Test Voltage, Method a a V IORM x. = V PR, Type and Sample Test, t m = s, Partial Discharge < pc V PR 8 V peak V PR 8 97 V peak Highest Allowable Overvoltage (Transient Overvoltage, t ini = s) V IOTM 8 V peak Safety-Limiting Values Maximum Values Allowed in the Event of a Failure Case Temperature Input Current Output Power Insulation Resistance at T S, V IO = V R IO 9 9 Ω a. Refer to the optocoupler section of the Isolation and Control Component Designer s Catalog, under Product Safety Regulations section IEC/ EN/DIN EN 77--, for a detailed description of Method a and Method b partial discharge test profiles. T S I S, INPUT P S, OUTPUT 7 C ma mw NOTE: These optocouplers are suitable for safe electrical isolation only within the safety limit data. Maintenance of the safety data shall be ensured by means of protective circuits. Absolute Maximum Ratings Parameter Symbol Min. Max. Unit Storage Temperature T S C Ambient Operating Temperature a T A 8 C Supply Voltages V DD, V DD. V Input Voltage V I. V DD +. V Output Voltage V O. V DD +. V Average Output Current I O ma Lead Solder Temperature C for sec.,. mm below seating plane. Solder Reflow Temperature Profile See Reflow Soldering Profile section. a. Absolute maximum ambient operating temperature means the device will not be damaged if operated under these conditions. It does not guarantee functionality

7 Recommended Operating Conditions Parameter Symbol Min. Max. Unit Figure Ambient Operating Temperature T A 8 C Supply Voltages V DD, V DD.. V Logic High Input Voltage V IH. V DD V, Logic Low Input Voltage V IL..8 V Input Signal Rise and Fall Times t ir, t if. ms Electrical Specifications (DC) Test conditions that are not specified can be anywhere within the recommended operating range. All typical specifications are at T A = + C, V DD = V DD = +V. Parameter Symbol Min. Typ. Max. Unit Test Conditions Fig Note Logic Low Input Supply Current I DDL.. ma V I = V a Logic High Input Supply Current I DDH.. ma V I = V DD a Output Supply Current I DDL ma I DDH.8 9. ma Input Current I I μa Logic High Output Voltage V OH.. V I O = μa, V I = V IH,..8 V I O = ma, V I = V IH Logic Low Output Voltage V OL. V I O = μa, V I = V IL. V I O = μa, V I = V IL.. V I O = ma, V I = V IL a. The LED is ON when V I is low and OFF when V I is high. Switching Specifications (AC) Parameter Symbol Min. Typ. Max. Unit Test Conditions Fig. Note Propagation Delay Time to Logic t PHL ns C L = pf, a Low Output CMOS Signal Levels Propagation Delay Time to Logic t PLH 9 ns High Output Pulse Width PW ns Data Rate MBd Pulse Width Distortion t PHL - t PLH PWD 77/7 ns 7 b 77/7 8 ns Propagation Delay Skew t PSK c Output Rise Time (% to 9%) t R 9 ns Output Fall Time (9% to %) t F 8 ns 7

8 Parameter Symbol Min. Typ. Max. Unit Test Conditions Fig. Note Common Mode CM H kv/μs V I = V DD, V O >.8 V DD, Transient Immunity at Logic High Output Common Mode Transient Immunity at Logic Low Output Input Dynamic Power Dissipation Capacitance Output Dynamic Power Dissipation Capacitance Package Characteristics CM L V CM = V V I = V, V O >.8V, V CM = V C PD pf e C PD a. t PHL propagation delay is measured from the % level on the falling edge of the V I signal to the % level of the falling edge of the V O signal. t PLH propagation delay is measured from the % level on the rising edge of the V I signal to the % level of the rising edge of the V O signal. b. PWD is defined as t PHL t PLH. %PWD (percent pulse width distortion) is equal to the PWD divided by pulse width. c. t PSK is equal to the magnitude of the worst-case difference in t PHL and/or t PLH that will be seen between units at any given temperature within the recommended operating conditions. d. CM H is the maximum common mode voltage slew rate that can be sustained while maintaining V O >.8V DD. CM L is the maximum common mode voltage slew rate that can be sustained while maintaining V O <.8V. The common mode voltage slew rates apply to both rising and falling common mode voltage edges. e. Unloaded dynamic power dissipation is calculated as follows: C PD V DD f + I DD V DD, where f is switching frequency in MHz. d Parameter Symbol Min. Typ. Max. Unit Test Conditions Fig. Note Input-Output Momentary 7X V ISO 7 V rms RH %, a, b, c Withstand Voltage t = min, 77X 7 T A = C Option Input-Output Resistance R I-O Ω V I-O = Vdc a Input-Output Capacitance C I-O. pf f = MHz Input Capacitance C I. d Input IC Junction-to-Case 77X θ jci C/W Thermocouple Thermal Resistance 7X located at center underside of Output IC Junction-to-Case 77X θ jco C/W package Thermal Resistance 7X Package Power Dissipation P PD mw a. Device considered a two-terminal device: pins,,, and shorted together and pins,, 7, and 8 shorted together. b. In accordance with UL77, each HCPL-7X is proof tested by applying an insulation test voltage V rms for second (leakage detection current limit, I I-O μa). Each HCPL-77X is proof tested by applying an insulation test voltage V rms for second (leakage detection current limit. I I-O μa). c. The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. d. C I is the capacitance measured at pin (V I ). 8

9 Figure : Typical Output Voltage vs. Input Voltage Figure : Typical Input Voltage Switching Threshold vs. Input Supply Voltage C C 8 C... C C 8 C VO (V) VITH (V) VI (V) VDD (V) Figure : Typical Propagation Delays vs. Temperature 9 Figure : Typical Pulse Width Distortion vs. Temperature 7 TPLH, TPHL (ns) 9 TPHL TPLH PWD (ns) T A (C) 8 Figure : Typical Rise Time vs. Temperature Figure : Typical Fall Time vs. Temperature 7 T R (ns) 9 T F (ns) T A (C) T A (C) 9

10 Figure 7: Typical Propagation Delays vs. Output Load Capacitance 9 7 Figure 8: Typical Pulse Width Distortion vs. Output Load Capacitance T PLH, T PHL (ns) 9 T PHL T PLH PWD (ns) 7 C I (pf) C I (pf) Figure 9: Thermal Derating Curve, Dependence of Safety Limiting Value with Case Temperature per IEC/EN/DIN EN 77-- OUTPUT POWER P S, INPUT CURRENT I S 8 7 () STANDARD 8 PIN DIP PRODUCT P S (mw) I S (ma) 7 7 T A CASE TEMPERATURE C OUTPUT POWER P S, INPUT CURRENT I S 8 7 () SURFACE MOUNT SO8 PRODUCT P S (mw) I S (ma) 7 7 T A CASE TEMPERATURE C

11 Application Information Bypassing and PC Board Layout The HCPL-77X/7X optocouplers are extremely easy to use. No external interface circuitry is required because the HCPL- 77X/7X use high-speed CMOS IC technology allowing CMOS logic to be connected directly to the inputs and outputs. As shown in Figure, the only external components required for proper operation are two bypass capacitors. Capacitor values should be between. μf and. μf. Each capacitor should be placed as close as possible to the input and output power-supply pins of the optocoupler. Figure : Functional Diagram V DD 8 V DD C C V I 7 NC NC V O GND GND C, C =. μf TO. μf

12 Digital Field Bus Communication Networks To date, despite its many drawbacks, the ma to ma analog current loop has been the most widely accepted standard for implementing process control systems. In today s manufacturing environment, however, automated systems are expected to help manage the process, not merely monitor it. With the advent of digital field bus communication networks such as CC-Link, DeviceNet, PROFIBUS, and Smart Distributed Systems (SDS), gone are the days of constrained information. Controllers can now receive multiple readings from field devices (sensors, actuators, etc.) in addition to diagnostic information. The physical model for each of these digital field bus communication networks is very similar as shown in Figure. Each includes one or more buses, an interface unit, optical isolation, transceiver, and sensing and/or actuating devices. Figure : Typical Field Bus Communication Physical Model CONTROLLER BUS INTERFACE OPTICAL TRANSCEIVER FIELD BUS TRANSCEIVER TRANSCEIVER TRANSCEIVER TRANSCEIVER OPTICAL OPTICAL OPTICAL OPTICAL BUS INTERFACE BUS INTERFACE BUS INTERFACE BUS INTERFACE XXXXXX SENSOR DEVICE CONFIGURATION MOTOR STARTER YYY MOTOR CONTROLLER

13 Optical Isolation for Field Bus Networks To recognize the full benefits of these networks, optocouplers are recommended to provide galvanic isolation. As network communication is bidirectional (involving receiving data from and transmitting data onto the network), two optocouplers are needed. By providing galvanic isolation, data integrity is retained via noise reduction and the elimination of false signals. In addition, the network receives maximum protection from power system faults and ground loops. Within an isolated node, such as the DeviceNet Node shown in Figure, some of the node's components are referenced to a ground other than V of the network. These components could include such things as devices with serial ports, parallel ports, RS- and RS-8 type ports. As shown in Figure, power from the network is used only for the transceiver and input (network) side of the optocouplers. Isolation of nodes connected to any of the three types of digital field bus networks is best achieved by using the HCPL-77X/ 7X optocouplers. For each network, the HCPL-77X/7X satisify the critical propagation delay and pulse width distortion requirements over the temperature range of C to +8 C, and power supply voltage range of.v to.v. Figure : Typical DeviceNet Node AC LINE NODE/APP SPECIFIC μp/can LOCAL NODE SUPPLY HCPL 77x/7x TRANSCEIVER HCPL 77x/7x V REG. GALVANIC BOUNDARY DRAIN/SHIELD SIGNAL POWER V+ (SIGNAL) V (SIGNAL) V+ (POWER) V (POWER) NETWORK POWER SUPPLY

14 Implementing CC-Link with the HCPL-77X/7X CC-Link (Control and Communication Link) is developed to merge control and information in the low-level network (field network) by PCs, thereby making the multivendor environment a reality. It has data control and message-exchange function, as well as bit control function, and operates at the speed up to Mb/s. The recommended CC-Link circuit is shown in Figure. Since the HCPL-77X/7X are fully compatible with CMOS logic level signals, the optocoupler is connected directly to the transceiver. Two bypass capacitors (with values between. μf and. μf) are required and should be located as close as possible to the input and output power supply pins of the HCPL- 77X/7X. The bypass capacitors are required because of the high-speed digital nature of the signals inside the optocoupler. Figure : Recommended CC-Link Application Circuit DA DB DG SLD FIL SN7ALS8NS VCC VCC A R B RE Y Z DE D GND GND. μ VDD ( V) GND HCPL-77# VDD VDD VI VO GND GND HCPL-77# VDD VDD VDD ( V). μ GND K RD. μ VO GND VI GND. μ SD FG HCPL-# K K HC. μ VOE VDD VO GND NC + NC 9 HC MPU BOARD OUTPUT K HCPL-# VOE NC K VDD + VO. μ SDGATEON HC 9 GND NC HC

15 Implementing DeviceNet and SDS with the HCPL-77X/7X With transmission rates up to Mb/s, both DeviceNet and SDS are based upon the same broadcast-oriented, communications protocol: the Controller Area Network (CAN). Three types of isolated nodes are recommended for use on these networks: Isolated Node Powered by the Network (Figure ), Isolated Node with Transceiver Powered by the Network (Figure 9), and Isolated Node Providing Power to the Network (Figure ). Isolated Node Powered by the Network This type of node is very flexible and as can be seen in Figure, is regarded as isolated because not all of its components have the same ground reference. Yet, all components are still powered by the network. This node contains two regulators: one is isolated and powers the CAN controller, node-specific application and isolated (node) side of the two optocouplers while the other is non-isolated. The non-isolated regulator supplies the transceiver and the non-isolated (network) half of the two optocouplers. Figure : Isolated Node Powered by the Network NODE/APP SPECIFIC μp/can HCPL 77x/7x TRANSCEIVER HCPL 77x/7x REG. ISOLATED SWITCHING POWER SUPPLY GALVANIC BOUNDARY DRAIN/SHIELD SIGNAL POWER V+ (SIGNAL) V (SIGNAL) V+ (POWER) V (POWER) NETWORK POWER SUPPLY

16 Isolated Node with Transceiver Powered by the Network Figure shows a node powered by both the network and another source. In this case, the transceiver and isolated (network) side of the two optocouplers are powered by the network. The rest of the node is powered by the AC line which is very beneficial when an application requires a significant amount of power. This method is also desirable as it does not heavily load the network. More importantly, the unique dual-inverting design of the HCPL-77X/7X ensure the network will not lock- up if either AC line power to the node is lost or the node powered-off. Specifically, when input power (V DD ) to the HCPL-77X/7X located in the transmit path is eliminated, a RECESSIVE bus state is ensured as the HCPL-77X/ 7X output voltage (V O ) go HIGH. Bus V+ Sensing* It is suggested that the Bus V+ sense block shown in Figure be implemented. A locally powered node with an unpowered isolated Physical Layer will accumulate errors and become bus-off if it attempts to transmit. The Bus V+ sense signal would be used to change the BOI attribute of the DeviceNet Object to the auto-reset () value. Refer to Volume, Section... This would cause the node to continually reset until bus power was detected. Once power was detected, the BOI attribute would be returned to the hold in bus-off () value. The BOI attribute should not be left in the auto-reset () value since this defeats the jabber protection capability of the CAN error confinement. Any inexpensive low-frequency optical isolator can be used to implement this feature. Figure : Isolated Node with Transceiver Powered by the Network AC LINE NODE/APP SPECIFIC NON ISO V μp/can HCPL 77x/7x HCPL 77x/7x *HCPL 77x/7x GALVANIC BOUNDARY TRANSCEIVER REG. DRAIN/SHIELD SIGNAL POWER V+ (SIGNAL) V (SIGNAL) V+ (POWER) V (POWER) NETWORK POWER SUPPLY * OPTIONAL FOR BUS V + SENSE

17 Isolated Node Providing Power to the Network Figure shows a node providing power to the network. The AC line powers a regulator which provides V locally. The AC line also powers a V isolated supply, which powers the network, and another V regulator, which, in turn, powers the transceiver and isolated (network) side of the two optocouplers. This method is recommended when there is a limited number of devices on the network, which do not require much power, thus eliminating the need for separate power supplies. More importantly, the unique dual-inverting design of the HCPL-77X/7X ensure the network will not lock- up if either AC line power to the node is lost or the node powered-off. Specifically, when input power (V DD ) to the HCPL-77X/7X located in the transmit path is eliminated, a RECESSIVE bus state is ensured as the HCPL-77X/ 7X output voltage (V O ) go HIGH. Figure : Isolated Node Providing Power to the Network AC LINE DeviceNet Node NODE/APP SPECIFIC V REG. μp/can HCPL 77x/7x TRANSCEIVER HCPL 77x/7x V REG. ISOLATED SWITCHING POWER SUPPLY GALVANIC BOUNDARY DRAIN/SHIELD SIGNAL POWER V+ (SIGNAL) V (SIGNAL) V+ (POWER) V (POWER) The recommended DeviceNet application circuit is shown in Figure 7. Since the HCPL-77X/7X are fully compatible with CMOS logic level signals, the optocoupler is connected directly to the CAN transceiver. Two bypass capacitors (with values between. µf and. µf) are required and should be located as close as possible to the input and output power-supply pins of the HCPL-77X/7X. The bypass capacitors are required because of the high-speed digital nature of the signals inside the optocoupler. 7

18 Figure 7: Recommended DeviceNet Application Circuit ISO V GALVANIC BOUNDARY V VDD VDD 8 TX. VIN 7 μf. μf HCPL-77x HCPL-7x VO TxD VCC CANH LINEAR OR SWITCHING REGULATOR + + V+ CAN+ RX. μf GND 7 GND GND VO HCPL-77x HCPL-7x GND GND VIN. μf + C. μf Rs 8C GND CANL REF RXD VREF D V C. μf V SHIELD CAN V R M 8 VDD VDD ISO V V 8

19 Implementing PROFIBUS with the HCPL-77X/7X An acronym for Process Fieldbus, PROFIBUS is essentially a twisted-pair serial link very similar to RS-8 capable of achieving high-speed communication up to MBd. As shown in Figure 8, a PROFIBUS Controller (PBC) establishes the connection of a field automation unit (control or central processing station) or a field device to the transmission medium. The PBC consists of the line transceiver, optical isolation, frame character transmitter/receiver (UART), and the FDL/APP processor with the interface to the PROFIBUS user. Figure 8: PROFIBUS Controller (PBC) PROFIBUS USER: CONTROL STATION (CENTRAL PROCESSING) OR FIELD DEVICE USER INTERFACE FDL/APP PROCESSOR PBC UART OPTICAL TRANSCEIVER MEDIUM The recommended PROFIBUS application circuit is shown in Figure 9. Since the HCPL-77X/7X are fully compatible with CMOS logic level signals, the optocoupler is connected directly to the transceiver. Two bypass capacitors (with values between. μf and. μf) are required and should be located as close as possible to the input and output power-supply pins of the HCPL-77X/7X. The bypass capacitors are required because of the high-speed digital nature of the signals inside the optocoupler. Being very similar to multistation RS8 systems, the HCPL-N optocoupler provides a transmit disable function which is necessary to make the bus free after each master/slave transmission cycle. Specifically, the HCPL-N disables the transmitter of the line driver by putting it into a high state mode. In addition, the HCPL-N switches the RX/TX driver IC into the listen mode. The HCPL-N offers HCMOS compatibility and the high CMR performance ( kv/μs at V CM = V) essential in industrial communication interfaces. 9

20 Figure 9: Recommended PROFIBUS Application Circuit GALVANIC BOUNDARY V ISO V 8 VDD VDD ISO V Rx Tx. μf. μf V 7 VO GND VDD VIN HCPL-77x HCPL-7x HCPL-77x HCPL-7x VIN GND VDD VO 8 7 ISO V. μf. μf. μf R D DE RE 8 VCC SN77B GND A B 7 RT. μf + SHIELD M GND GND ISO V Tx ENABLE V, kω VCC ANODE VE HCPL-N CATHODE VO 8 7. μf 8 Ω GND

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