Ultra-Low Bias Current Difet OPERATIONAL AMPLIFIER

Transcription

1 OPA9 Ultra-Low Bias Current Difet OPERATIONAL AMPLIFIER FEATURES ULTRA-LOW BIAS CURRENT: fa max LOW OFFSET: mv max LOW DRIFT: µv/ C max HIGH OPEN-LOOP GAIN: 9dB min LOW NOISE: nv/ Hz at khz PLASTIC DIP and SOIC PACKAGE APPLICATIONS PHOTODETECTOR PREAMP CHROMATOGRAPHY ELECTROMETER AMPLIFIERS MASS SPECTROMETER ph PROBE AMPLIFIER ION GAGE MEASUREMENT DESCRIPTION The OPA9 is an ultra-low bias current monolithic operational amplifier offered in an -pin PDIP and SO- package. Using advanced geometry dielectrically-isolated FET (Difet ) inputs, this monolithic amplifier achieves a high performance level. Difet fabrication eliminates isolation-junction leakage current the main contributor to input bias current with conventional monolithic FETs. This reduces input bias current by a factor of to. Very low input bias current can be achieved without resorting to small-geometry FETs or CMOS designs which can suffer from much larger offset voltage, voltage noise, drift, and poor power supply rejection. The OPA9's special pinout eliminates leakage current that occurs with other op amps. Pins and have no internal connection, allowing circuit board guard traces even with the surface-mount package version. In +In Noise-Free Cascode kω kω Substrate OPA9 is available in -pin DIP and SO- packages, specified for operation from C to + C. Simplified Circuit Difet Burr-Brown Corp. International Airport Industrial Park Mailing Address: PO Box Tucson, AZ Street Address: S. Tucson Blvd. Tucson, AZ Tel: () - Twx: 9-9- Cable: BBRCORP Telex: -9 FAX: () 9- Immediate Product Info: () - 99 Burr-Brown Corporation PDS-9A Printed in U.S.A. July, 99

2 SPECIFICATIONS ELECTRICAL At V S = ±V and T A = + C unless otherwise noted. Pin connected to ground. OPA9PB, UB OPA9P, U PARAMETER CONDITION MIN TYP MAX MIN TYP MAX UNITS INPUT BIAS CURRENT () V CM = V ± ± * ± fa vs Temperature Doubles every C * INPUT OFFSET CURRENT V CM = V ± * fa OFFSET VOLTAGE Input Offset Voltage V CM = V ±. ± ± ± mv vs Temperature ± ± ± µv/ C Supply Rejection V S = ±V to ±V ± ± * * µv/v NOISE Voltage f = Hz * nv/ Hz f = Hz * nv/ Hz f = khz * nv/ Hz f = khz * nv/ Hz f B =.Hz to Hz * µvp-p Current f = khz. * fa/ Hz INPUT IMPEDANCE Differential * Ω pf Common-Mode * Ω pf VOLTAGE RANGE Common-Mode Input Range ± ± * * V Common-Mode Rejection V IN = ±V * * db OPEN-LOOP GAIN, DC Open-Loop Voltage Gain R L kω 9 * * db FREQUENCY RESPONSE Unity Gain, Small Signal * MHz Full Power Response Vp-p, R L = kω * khz Slew Rate V O = ±V, R L = kω. * * V/µs Settling Time: G =, R L = kω, V Step.% * µs.% * µs Overload Recovery, % Overdrive () G = * µs RATED OUTPUT Voltage R L = kω ± ± * * V Current V O = ±V ± ± * * ma Load Capacitance Stability Gain = + * pf Short-Circuit Current ± ± * * ma POWER SUPPLY Rated Voltage ± * V Voltage Range, Derated Performance ± ± * * V Current, Quiescent I O = ma.. * * ma TEMPERATURE Specification Ambient Temperature + * * C Operating Ambient Temperature + * * C Storage + * * C Thermal Resistance θ JA, Junction-to-Ambient PDIP "P" 9 * C/W SOIC "U" * C/W NOTES: () High-speed automated test. () Overload recovery is defined as the time required for the output to return from saturation to linear operation following the removal of a % input overdrive. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. OPA9

3 ABSOLUTE MAXIMUM RATINGS Power Supply Voltage... ±V Differential Input Voltage... to Input Voltage Range... to Storage Temperature Range... C to + C Operating Temperature Range... C to + C Lead Temperature (soldering, s; SOIC s)... + C Short Circuit Duration ()... Continuous Junction Temperature (T J )... + C NOTE: () Short circuit may be to power supply common at + C ambient. PACKAGE INFORMATION PACKAGE DRAWING MODEL PACKAGE NUMBER () OPA9P -pin Plastic DIP OPA9PB -pin Plastic DIP OPA9U -pin SOIC OPA9UB -pin SOIC NOTE: () For detailed drawing and dimension table, please see end of data sheet, or Appendix D of Burr-Brown IC Data Book. ELECTROSTATIC DISCHARGE SENSITIVITY Any integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet published specifications. CONNECTION DIAGRAM Top View NC In OPA +In NC NC: No internal connection. DIP/SOIC Substrate TYPICAL PERFORMANCE CURVES T A = + C, +VDC, unless otherwise noted. OPEN-LOOP FREQUENCY RESPONSE POWER SUPPLY REJECTION vs FREQUENCY Voltage Gain (db) Gain Phase Margin 9 θ 9 Pulse Shift (degrees) Power Supply Rejection (db) PSRR +PSRR k k k M M k k k M M OPA9

4 TYPICAL PERFORMANCE CURVES (CONT) T A = + C, +VDC, unless otherwise noted. COMMON-MODE REJECTION vs INPUT COMMON-MODE VOLTAGE COMMON-MODE REJECTION vs FREQUENCY Common-Mode Rejection (db) 9 Common-Mode Rejection (db) Common-Mode Voltage (V) k k k M M pa BIAS AND OFFSET CURRENT vs TEMPERATURE BIAS AND OFFSET CURRENT vs INPUT COMMON-MODE VOLTAGE Bias and Offset Current (fa) pa pa I B and I OS Normalized Bias and Offset Current.. Ambient Temperature ( C) Common-Mode Voltage (V) k INPUT VOLTAGE NOISE SPECTRAL DENSITY FULL-POWER OUTPUT vs FREQUENCY Voltage Density (nv/ Hz) Voltage (Vp-p) k k k k k k M OPA9

5 TYPICAL PERFORMANCE CURVES (CONT) T A = + C, +VDC, unless otherwise noted. GAIN BANDWIDTH AND SLEW RATE vs TEMPERATURE GAIN BANDWIDTH AND SLEW RATE vs SUPPLY VOLTAGE Gain Bandwidth (MHz) Slew Rate (V/µs) Gain Bandwidth (MHz) +Slew Slew GBW Slew Rate (v/µs) Ambient Temperature ( C) Supply Voltage (±V CC ) SUPPLY CURRENT vs TEMPERATURE OPEN-LOOP GAIN, PSR AND CMR vs TEMPERATURE Supply Current (ma).. PSR, CMR, Voltage Gain (db) CMR PSR A OL Ambient Temperature ( C) 9 Ambient Temperature ( C) LARGE SIGNAL TRANSIENT RESPONSE SMALL SIGNAL TRANSIENT RESPONSE Voltage (V) Voltage (mv) Time (µs) Time (µs) OPA9

6 TYPICAL PERFORMANCE CURVES (CONT) T A = + C, +VDC, unless otherwise noted. COMMON-MODE INPUT RANGE vs SUPPLY VOLTAGE pa BIAS CURRENT vs ADDITIONAL POWER DISSIPATION Common-Mode Voltage (+V) Bias Current (fa) pa pa Supply Voltage (±V CC ) Additional Power Dissipation (mw) APPLICATIONS INFORMATION NON-STANDARD PINOUT The OPA9 uses a non-standard pinout to achieve lowest possible input bias current. The negative power supply is connected to pin see Figure. This is done to reduce the leakage current from the V- supply (pin on conventional op amps) to the op amp input terminals. With this new pinout, sensitive inputs are separated from both power supply pins. V IN R IN OPA9 Ω R F FIGURE. Offset Adjust Circuit. kω kω.µf V OUT OFFSET VOLTAGE TRIM The OPA9 has no conventional offset trim connections. Pin, next to the critical inverting input, has no internal connection. This eliminates a source of leakage current and allows guarding of the input terminals. Pin and pin, next to the two input pins, have no internal connection. This allows an optimized circuit board layout with guarding see circuit board layout. Due to its laser-trimmed input stage, most applications do not require external offset voltage trimming. If trimming is required, the circuit shown in Figure can be used. Power supply voltages are divided down, filtered and applied to the non-inverting input. The circuit shown is sensitive to variation in the supply voltages. Regulation can be added, if needed. GUARDING AND SHIELDING Ultra-low input bias current op amps require precautions to achieve best performance. Leakage current on the surface of circuit board can exceed the input bias current of the amplifier. For example, a circuit board resistance of Ω from a power supply pin to an input pin produces a current of pa more than one-hundred times the input bias current of the op amp. To minimize surface leakage, a guard trace should completely surround the input terminals and other circuitry connecting to the inputs of the op amp. The DIP package should have a guard trace on both sides of the circuit board. The guard ring should be driven by a circuit node equal in potential to the op amp inputs see Figure. The substrate, pin, should also be connected to the circuit board guard to assure that the amplifier is fully surrounded by the guard potential. This minimizes leakage current and noise pick-up. Careful shielding is required to reduce noise pickup. Shielding near feedback components may also help reduce noise pick-up. Triboelectric effects (friction-generated charge) can be a troublesome source of errors. Vibration of the circuit board, input connectors and input cables can cause noise and drift. Make the assembly as rigid as possible. Attach cables to avoid motion and vibration. Special low noise or low leakage cables may help reduce noise and leakage current. Keep all input connections as short possible. Surface-mount components may reduce circuit board size and allow a more rigid assembly. OPA9

7 CIRCUIT BOARD LAYOUT MΩ The OPA9 uses a new pinout for ultra low input bias current. Pin and pin have no internal connection. This allows ample circuit board space for a guard ring surrounding the op amp input pins even with the tiny SO- surfacemount package. Figure shows suggested circuit board layouts. The guard ring should be connected to pin (substrate) as shown. It should be driven by a circuit node equal in potential to the input terminals of the op amp see Figure for common circuit configurations. I IN Current Input R F OPA9 kω V O = I IN R F V O = V/nA kω TESTING Accurately testing the OPA9 is extremely difficult due to its high performance. Ordinary test equipment may not be able to resolve the amplifier s extremely low bias current. Inaccurate bias current measurements can be due to:. Test socket leakage,. Unclean package,. Humidity or dew point condensations,. Circuit contamination from fingerprints or anti-static treatment chemicals,. Test ambient temperature,. Load power dissipation,. Mechanical stress,. Electrostatic and electromagnetic interference. FIGURE. Current-to-Voltage Converter. Ω Guard OPA9 ph Probe R S MΩ mv Out 9.kΩ FIGURE. High Impedance ( Ω) Amplifier. VDC (A) Non-Inverting (B) Buffer C F pf In Out In (C) Inverting Out Q R F Ω OPA9 V OUT In Out Low frequency cutoff = /(πr F C F ) =.Hz V OUT = Q/C F (A) DIP package (B) SOIC package Guard top and bottom of board. FIGURE. Connection of Input Guard. V V Connect to proper circuit node, depending on circuit configuration (see Figure ). Connect to proper circuit node, depending on circuit configuration (see Figure ). FIGURE. Suggested Board Layout for Input Guard. FIGURE. Piezoelectric Transducer Charge Amplifier. Pin photodiode HP - Guard Ω +V.µF OPA9.µF V FIGURE. Sensitive Photodiode Amplifier. ~pf to prevent gain peaking x 9 V/W Circuit must be well shielded. OPA9

8 PACKAGE DRAWINGS OPA9