Microprocessor-Compatible 12-BIT DIGITAL-TO-ANALOG CONVERTER

Transcription

1 Microprocessor-Compatible 1-BIT DIGITAL-TO-ANALOG CONVERTER FEATURES ±1/LSB NONLINEARITY OVER TEMPERATURE GUARANTEED MONOTONIC OVER TEMPERATURE LOW POWER: 7mW typ DIGITAL INTERFACE DOUBLE BUFFERED: 1 AND 8 + BITS SPECIFIED AT ±1V AND ±1V POWER SUPPLIES RESET FUNCTION TO BIPOLAR ZERO." WIDE DIP AND SO PACKAGES DESCRIPTION The is a complete monolithic 1-bit digitalto-analog converter with a flexible digital interface. It includes a precision +1V reference, interface control logic, double-buffered latch and a 1-bit D/A con- verter with voltage output operational amplifier. Fast current switches and laser-trimmed thin-film resistors provide a highly accurate, fast D/A converter. Digital interfacing is facilitated by a double buffered latch. The input latch consists of one 8-bit byte and one -bit nibble to allow interfacing to 8-bit (right justified format) or 1-bit data buses. Input gating logic is designed so that the last nibble or byte to be loaded can be loaded simultaneously with the transfer of data to the D/A latch saving computer instructions. A reset control allows the D/A latch to asynchronously reset the D/A output to bipolar zero, a feature useful for power-up reset, recalibration, or for system re-initialization upon system failure. The is specified to ±1/LSB maximum linearity error (J, A grades) and ±1/LSB (K, B grades). It is packaged in a 8-pin." wide ceramic DIP ( C to +8 C specification temperature range), 8-pin." wide plastic DIP and 8-lead plastic SO ( C to +7 C). Reset MSBs 8 LSBs Input Latch Input Latch 8 D/A Latch 1.kΩ BPO V Span V Span 1V Reference.kΩ 1-Bit D/A Converter V REF OUT V REF IN International Airport Industrial Park Mailing Address: PO Box 11 Tucson, AZ 87 Street Address: 7 S. Tucson Blvd. Tucson, AZ 87 Tel: () Twx: Cable: BBRCORP Telex: -1 FAX: () Immediate Product Info: (8) Burr-Brown Corporation PDS-177E Printed in U.S.A. January, 1

2 SPECIFICATIONS ELECTRICAL T A = + C, ±V CC = ±1V or ±1V and load on = kω pf to common unless otherwise noted. AH, JP, JU, AU BH, KP, KU PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS DIGITAL INPUTS Resolution 1 * Bits Codes (1) USB, BOB * Digital Inputs Over Temperature Range () V () IH + +. * * VDC V IL +.8 * * VDC DATA Bits,, Reset,,, ±1 * µa I IH V IN = +.7V ±1 * µa I IL V IN = +.V ACCURACY Linearity Error ±1/ ±1/ ±1/8 ±1/ LSB Differential Linearity Error ±1/ ±/ ±1/ ±1/ LSB Gain Error () ±. ±. * * % Unipolar Offset Error () ±.1 ±. * * % of FSR (7) Bipolar Zero Error () ±. ±. * * % of FSR Monotonicity Guaranteed * Power Supply Sensitivity: +V CC V Range 1 * * ppm of FSR/% V CC 1 1 * * ppm of FSR/% DRIFT Over Specification Gain Temperature Range ± ± * ±1 ppm/ C Unipolar Offset ±1 ± * ± ppm of FSR/ C Bipolar Zero ± ±1 * ± ppm of FSR/ C Linearity Error Over Temperature Range ±1/ ±/ ±1/ ±1/ LSB Monotonicity Over Temperature Range Guaranteed * SETTLING TIME (8) (To Within ±.1% of FSR of Final Value; kω pf load) For Full Scale Range Change V Range. * * µs 1V Range. * * µs For 1LSB Change at Major Carry () * µs Slew Rate 1 * V/µs ANALOG OUTPUT Voltage Range: Unipolar ±V CC > ±11.V to +1 * V Bipolar ±V CC > ±11.V ±, ±1 * V Output Current ± * ma Output Impedance At DC. * Ω Short Circuit to Common Duration Indefinite * REFERENCE VOLTAGE Voltage * * * V Source Current Available for External Loads * ma Impedance * Ω Temperature Coefficient ± ± * * ppm/ C Short Circuit to Common Duration Indefinite * POWER SUPPLY REQUIREMENTS Voltage: +V CC * * * VDC V CC * * * VDC Current: +V CC + V L No Load 1 1 * * ma V CC No Load 7 * * ma Potential at DCOM with Respect to ACOM (1) + * * V Power Dissipation 7 * * mw TEMPERATURE RANGE Specification: J, K +7 * * C A, B +8 * * C Operating: J, K +8 * * C A, B +1 * * C Storage: J, K +1 * * C A, B +1 * * C *Same as specification for AH, JP, JU. NOTES: (1) USB = Unipolar Straight Binary; BOB = Bipolar Offset Binary. () TTL and V CMOS compatible. () Open DATA input lines will be pulled above +.V. See discussion under LOGIC INPUT COMPATIBILITY in the OPERATION section. () Specified with Ω Pin to 7. Adjustable to zero with external trim potentiometer. () Error at input code HEX for unipolar mode, FSR = 1V. () Error at input code 8 HEX for bipolar range. Specified with 1Ω Pin to and with Ω pin to 7. See page for zero adjustment procedure. (7) FSR means Full Scale Range and is V for the ±1V range. (8) Maximum represents the σ limit. Not 1% tested for this parameter. () At the major carry, 7FF HEX to 8 HEX and 8 HEX to 7FF HEX. (1) The maximum voltage at which ACOM and DCOM may be separated without affecting accuracy specifications.

3 MINIMUM TIMING DIAGRAMS ITE CYCLE #1 (Load first rank from Data Bus: = 1), DB11 DB ITE CYCLE # (Load second rank from first rank:, = 1) RESET COMMAND (Bipolar Mode) Reset +1V 1V > ns > ns > ns > ns > ns,,, = Don t Care > ns t SETTLING t SETTLING ±1/LSB ±1/LSB +V CC to ACOM... to +18V V CC to ACOM... to 18V +V CC to V CC... to +V DCOM with respect to ACOM... ±V Digital Inputs (Pins 11 1, 17 8) to DCOM....V to +V CC External Voltage Applied to BPO Span Resistor... ±V CC V REF OUT... Indefinite Short to ACOM... Indefinite Short to ACOM Power Dissipation... 7mW Lead Temperature (soldering, 1s)... + C Max Junction Temperature C Thermal Resistance, θ J-A :Plastic DIP and SOIC... 1 C/W Ceramic DIP... 8 C/W NOTE: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. V ABSOLUTE MAXIMUM RATINGS >ns PIN DESCRIPTIONS PIN NAME DESCRIPTION 1 +V L Positive supply pin for logic circuits. Connect to +V CC., V Range Connect Pin or Pin to Pin ( ) for a V FSR. Connect both to Pin for a 1V FSR. BPO Bipolar offset. Connect to Pin (V REF OUT ) through 1Ω resistor or Ω potentiometer for bipolar operation. ACOM Analog common, ±V CC supply return. V REF OUT +1V reference output referred to ACOM. 7 V REF IN Connected to V REF OUT through a 1kΩ gain adjustment potentiometer or a Ω resistor. 8 +V CC Analog supply input, nominally +1V to +1V referred to ACOM. D/A converter voltage output. 1 V CC Analog supply input, nominally 1V or 1V referred to ACOM. 11 Master enable for,, and. Must be low for data transfer to any latch. 1 Load DAC. Must be low with for data transfer to the D/A latch and simultaneous update of the D/A converter. 1 Reset When low, resets the D/A latch such that a Bipolar Zero output is produced. This control overrides all other data input operations. 1 Enable for -bit input latch of D 8 -D 11 data inputs. NOTE: This logic path is slower than the path. 1 Enable for 8-bit input latch of D -D 7 data inputs. NOTE: This logic path is slower than the path. 1 DCOM Digital common. 17 D Data Bit 1, LSB. 18 D1 Data Bit. 1 D Data Bit. D Data Bit. 1 D Data Bit. D Data Bit. D Data Bit 7. D7 Data Bit 8. D8 Data Bit. D Data Bit 1. 7 D1 Data Bit D11 Data Bit 1, MSB, positive true. ELECTROSTATIC DISCHARGE SENSITIVITY Electrostatic discharge can cause damage ranging from performance degradation to complete device failure. Burr- Brown Corporation recommends that all integrated circuits be handled and stored using appropriate ESD protection methods. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet published specifications. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.

4 DICE INFORMATION NC NC NC DIE TOPOGRAPHY 1 1 PAD FUNCTION 1 +V L V Range V Range BPO ACOM V REF OUT 7 V REF IN 8 +V CC 1 V CC Reset 1 Substrate Bias: V CC NC: No Connection. MECHANICAL INFORMATION PAD FUNCTION 1 1 DCOM 17 DB (LSB) 18 DB1 1 DB DB 1 DB DB DB DB7 DB8 DB 7 DB1 8 DB11 (MSB) MILS (.1") MILLIMETERS Die Size x 1 ±.18 x. ±.1 Die Thickness ±.1 ±.8 Min. Pad Size x.1 x.1 Metalization Aluminum ORDERING INFORMATION LINEARITY GAIN TEMPERATURE ERROR, MAX DRIFT USA OEM PRICE MODEL PACKAGE RANGE AT + C (ppm/ C) 1 1+ AU Plastic SOIC C to +8 C ±1/LSB ± $1.7 $1. $11. JP Plastic DIP C to +7 C ±1/LSB ± JU Plastic SOIC C to +7 C ±1/LSB ± KP Plastic DIP C to +7 C ±1/LSB ± KU Plastic SOIC C to +7 C ±1/LSB ± AH Ceramic DIP C to +8 C ±1/LSB ± BH Ceramic DIP C to +8 C ±1/LSB ±1 PACKAGE INFORMATION PACKAGE DRAWING MODEL PACKAGE NUMBER (1) AH 8-Pin Hermetic 7 Side-Brazed DIP BH 8-Pin Hermetic 7 Side-Brazed DIP AP 8-Pin Plastic DIP KP 8-Pin Plastic DIP AU 8-Pin Plastic SOIC 17 JU 8-Pin Plastic SOIC 17 KU 8-Pin Plastic SOIC 17 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix D of Burr-Brown IC Data Book. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.

5 TYPICAL PERFORMANCE CURVES T A = + C, V CC = ±1V unless otherwise noted. [Change in FSR]/[Change in Supply Voltage] (ppm of FSR/ %) 1k POWER SUPPLY REJECTION vs POWER SUPPLY RIPPLE FREQUENCY Frequency (Hz) +V CC V CC k 1k 1k 1M Input Current (µa) DIGITAL INPUT CURRENT vs INPUT VOLTAGE,, Reset Data 8 Input Voltage (V) 1 CHANGE OF GAIN AND OFFSET ERROR vs TEMPERATURE.8. INTEGRAL LINEARITY ERROR Gain Error (%).. Bipolar Offset Gain Error Unipolar Offset.. Bipolar/Unipolar Offset (%) (For 1V FSR; Double for V FSR) Linearity Error (LSB) Temperature ( C).8. 8 C FFF Input Code (Hexidecimal) 1 ± FULL SCALE OUTPUT SWING MAJOR CARRY GLITCH (V) 1 + (V) (mv) 1 1 Data = Data = 8 H Data = 7FF H 7FF H +1 (V) Time (µs) Time (µs)

6 TYPICAL PERFORMANCE CURVES (CONT) T A = + C, V CC = ±1V unless otherwise noted. SETTLING TIME, +1V TO 1V 1LSB =.88mV 1 SETTLING TIME, 1V TO +1V 1LSB =.88mV Around 1V (mv) (V) Around +1V (mv) 1 + (V) Time (µs) Time (µs) DISCUSSION OF SPECIFICATIONS INPUT CODES The accepts positive-true binary input codes. may be connected by the user for any one of the following codes: USB (Unipolar Straight Binary), BOB (Bipolar Offset Binary) or, using an external inverter on the MSB line, BTC (Binary Two s Complement). See Table I. DIGITAL ANALOG OUTPUT INPUT USB BOB BTC* Unipolar Bipolar Binary Straight Offset Two s MSB to LSB Binary Binary Complement FFF HEX + Full Scale + Full Scale Zero 1LSB 8 HEX + 1/ Full Scale Zero Full Scale 7FF HEX + 1/ Full Scale 1LSB Zero 1LSB + Full Scale HEX Zero Full Scale Zero * Invert MSB of BOB code with external inverter to obtain BTC code. TABLE I. Digital Input Codes. LINEARITY ERROR Linearity error as used in D/A converter specifications by Burr-Brown is the deviation of the analog output from a straight line drawn between the end points (inputs all 1s and all s ). The linearity error is specified at ±1/LSB (max) at + C for B and K grades, and ±1/LSB (max) for A and J grades. DIFFERENTIAL LINEARITY ERROR Differential linearity error (DLE) is the deviation from a 1LSB output change from one adjacent state to the next. A DLE specification of 1/LSB means that the output step size can range from 1/LSB to /LSB when the input changes from one state to the next. Monotonicity requires that DLE be less than 1LSB over the temperature range of interest. MONOTONICITY A D/A converter is monotonic if the output either increases or remains the same for increasing digital inputs. All grades of are monotonic over their specification temperature range. DRIFT Gain Drift is a measure of the change in the Full Scale Range (FSR) output over the specification temperature range. Gain Drift is expressed in parts per million per degree Celsius (ppm/ C). Unipolar Offset Drift is measured with a data input of HEX. The D/A is configured for unipolar output. Unipolar Offset Drift is expressed in parts per million of Full Scale Range per degree Celsius (ppm of FSR/ C). Bipolar Zero Drift is measured with a data input of 8 HEX. The D/A is configured for bipolar output. Bipolar Zero Drift is expressed in parts per million of Full Scale Range per degree Celsius (ppm of FSR/ C). SETTLING TIME Settling Time is the total time (including slew time) for the output to settle within an error band around its final value after a change in input. Three settling times are specified to ±.1% of Full Scale Range (FSR): two for maximum full scale range changes of V and 1V, and one for a 1LSB change. The 1LSB change is measured at the major carry (7FF HEX to 8 HEX and 8 HEX to 7FF HEX ), the input transition at which worst-case settling time occurs. REFERENCE SUPPLY contains an on-chip +1V reference. This voltage (pin ) has a tolerance of ±mv. V REF OUT must be connected to V REF IN through a gain adjust resistor with a nominal value of Ω. The connection can be made through an optional 1kΩ trim resistor to provide adjustment to zero

7 gain error. The reference output may be used to drive external loads, sourcing at least ma. This current should be constant, otherwise the gain of the converter will vary. POWER SUPPLY SENSITIVITY Power supply sensitivity is a measure of the effect of a power supply change on the D/A converter output. It is defined as a ppm of FSR output change per percent of change in either +V CC or V CC about the nominal voltages expressed in ppm of FSR/%. The first performance curve on page shows typical power supply rejection versus power supply ripple frequency. OPERATION is a complete single IC chip 1-bit D/A converter. The chip contains a 1-bit D/A converter, voltage reference, output amplifier, and microcomputer-compatible input logic as shown in Figure 1. INTERFACE LOGIC Input latches hold data temporarily while a complete 1-bit word is assembled before loading into the D/A latch. This double-buffered organization prevents the generation of spurious analog output values. Each latch is independently addressable. All latches are level-triggered. Data present when the control signals are logic will enter the latch. When any one of the control signals returns to logic 1, the data is latched. A truth table for the control signals is presented in Table II. RESET OPERATION 1 X X X 1 No operation X X X X D/A latch set to 8 HEX Enables MSBs input latch Enables 8 LSBs input latch Loads D/A latch from input latches 1 Makes all latches transparent X = Don t Care TABLE II. Interface Logic Truth Table. CAUTION: was designed to use as the fast strobe. has a much faster logic path than EN X (or ). Therefore, if one permanently wires to DCOM and uses only EN X to strobe data into the latches, the DATA HOLD time will be long, approximately 1ns to ns, and this time will vary considerably in this range from unit to unit. DATA HOLD time using is ns max. LOGIC INPUT COMPATIBILITY The digital inputs are TTL, V CMOS compatible over the operating range of +V CC. The input switching threshold remains at the TTL threshold over the supply range. An equivalent circuit of a digital input is shown in Figure. The logic input current over temperature is low enough to permit driving the directly from the outputs of V CMOS devices. Open DATA input lines will float to 7V or more. Although this will not harm the, current spikes will occur in the input lines when a logic is asserted and, in addition, MSB LSB D11 D8 D7 D V (1) L DCOM Reset Bit Latch.kΩ 1-Bit D/A Latch 1-Bit D/A Converter 8-Bit Latch 8µA.kΩ BPO V Range V Range +1V Reference NOTE: (1) V L must be connected to +V CC. V REF IN V REF OUT ACOM +V CC V CC FIGURE 1. Block Diagram. 7

8 Digital Input 1kΩ*.8V pf See page for I I I I BTC) configurations, apply the digital input code that should produce the maximum negative output voltage and adjust the offset potentiometer for minus full scale voltage. Example: If the full scale range is connected for V, the maximum negative output voltage is 1V. See Table III for corresponding codes. DCOM * R = Ω for. FIGURE. Equivalent Input Circuit for Digital Inputs. the speed of the interface will be slower. A digital output driving a DATA input line of the must not drive, or let the DATA input float, above +.V. Unused DATA inputs should be connected to DCOM. RESET FUNCTION When asserted low (<.8V), RESET (Pin 1) forces the D/A latch to 8 HEX regardless of any other input logic condition. If the analog output is connected for bipolar operation (either ±1V or ±V), the output will be reset to Bipolar Zero (V). If the analog output is connected for unipolar operation ( to +1V), the output will be reset to half-scale (+V). If RESET is not used, it should be connected to a voltage greater than +V but not greater than +.V. If this voltage is not available Reset can be connected to +V CC through a 1kΩ to 1MΩ resistor to limit the input current. GAIN AND OFFSET ADJUSTMENTS Figures and illustrate the relationship of offset and gain adjustments to unipolar and bipolar D/A converter output. OFFSET ADJUSTMENT For unipolar (USB) configurations, apply the digital input code that should produce zero voltage output and adjust the offset potentiometer for zero output. For bipolar (BOB, GAIN ADJUSTMENT For either unipolar or bipolar configurations, apply the digital input that should give the maximum positive voltage output. Adjust the gain potentiometer for this positive full scale voltage. See Table III for positive full scale voltages. DIGITAL INPUT ANALOG OUTPUT MSB to LSB to +1V ±V ±1V FFF HEX +.7V +.7V +.1V 8 HEX +.V.V.V 7FF HEX +.7V.V.V HEX.V.V 1.V 1LSB.mV.mV.88mV TABLE III. Digital Input/Analog Output. INSTALLATION POWER SUPPLY CONNECTIONS Note that the lid of the ceramic packaged is connected to V CC. Take care to avoid accidental short circuits in tightly spaced installations. Power supply decoupling capacitors should be added as shown in Figure. Optimum settling performance occurs using a 1 to 1µF tantalum capacitor at V CC and at least a.1µf ceramic capacitor at +V CC. Applications with less critical settling time may be able to use.1µf at V CC as well. The.1µF capacitors should be located close to the. Pin 1 supplies internal logic and must be connected to +V CC. Analog Output 1LSB Full Scale Range Range of Offset Adj. ±.% + Full Scale All Bits Logic Offset Adjust Translates the Line Digital Input Gain Adjust Rotates the Line All Bits Logic 1 Range of Gain Adjust ±1% FIGURE. Relationship of Offset and Gain Adjustments for a Unipolar D/A Converter. Analog Output All Bits Logic Range of Offset Adjust Offset Adj. Translates the Line ±.% + Full Scale Bipolar Offset 1LSB Full Scale Range Digital Input MSB on All Others Off Full Scale Gain Adjust Rotates the Line Range of Gain Adjust ±1% All Bits Logic 1 FIGURE. Relationship of Offset and Gain Adjustments for a Bipolar D/A Converter. 8

9 Ω 1kΩ 1 7 V L D11 V Range D1 V Range D BPO D8 ACOM D7 VREF OUT D VREF IN D 8 7 +V CC 1k Ω to 1k Ω V CC () MΩ.1µF 1kΩ 1 7 V L D11 V Range D1 V Range D BPO D8 ACOM D7 VREF OUT D VREF IN D 8 7 (1) 1µF tantalum for optimum settling performance. () Unipolar offset is not necessary in most applications and can lead to noise pickup. () Note that for the ceramic package the lid is connected to VCC. +V CC 8 +V CC D 1 +V CC 8 +V CC D 1.1µF VOUT D.1µF VOUT D V CC () 1 V CC D 1 V () CC D1 18.1µF (1).1µF (1) 1 D V CC D D1 D Reset DCOM 1 1 Reset DCOM BIPOLAR UNIPOLAR FIGURE. Power Supply, Gain, and Offset Connections. features separate digital and analog power supply returns to permit optimum connections for low noise and high speed performance. It is recommended that both Analog Common (ACOM, Pin ) and Digital Common (DCOM, Pin 1) be connected directly to a ground plane under the package. If a ground plane is not used, connect the ACOM and DCOM pins together close to the package. Since the reference point for and V REF OUT is the ACOM pin, it is also important to connect the load directly to the ACOM pin. Refer to Figure. The change in current in the Analog Common pin (ACOM, Pin ) due to an input data word change from HEX to FFF HEX is only 8µA. OUTPUT RANGE CONNECTIONS Internal scaling resistors provided in the may be connected to produce bipolar output voltage ranges of ±1V and ±V or unipolar output voltage range of to +1V. Refer to Figure. The internal feedback resistors () and the bipolar offset resistor (.kω) are trimmed to an absolute tolerance of less than ±%. Therefore, one can change the range by adding a series resistor in various feedback circuit configurations. For example, a Ω resistor in series with the V range terminal can be used to obtain a.8v (±1.V) range (mv LSB). A 7.8kΩ resistor in series with the 1V range connection (V ranges in parallel) gives a 1.8V (±8.1V) bipolar range (mv LSB). Gain drift will be affected by the mismatch of the temperature coefficient of the external resistor with the internal D/A resistors. APPLICATIONS MICROCOMPUTER BUS INTERFACING The interface logic allows easy interface to microcomputer bus structures. The control signal is derived from external device select logic and the I/O Write or Memory Write (depending upon the system design) signals from the microcomputer. The latch enable lines,, and determine which of the latches are selected. It is permissible to enable two or more latches simultaneously, as shown in some of the following examples. The double-buffered latch permits data to be loaded into the input latches of several s and later strobed into the D/A latch of all D/As, simultaneously updating all analog outputs. All the interface schemes shown below use a base address decoder. If blocks of memory are used, the base address decoder can be simplified or eliminated altogether. 8-BIT INTERFACE The control logic of permits interfacing to rightjustified data formats, illustrated in Figure 7. When a 1-bit D/A converter is loaded from an 8-bit bus, two bytes of data are required. Figure 8 illustrates an addressing scheme for right-justified data. The base address is decoded from the high-order address bits. A and A1 address the appropriate latches. Note that adjacent addresses are used. X1 HEX loads the 8 LSBs and X1 HEX loads the MSBs and simultaneously transfers input latch data to the D/A latch. Addresses X HEX and X11 HEX are not used.

10 INTERFACING MULTIPLE s IN 8-BIT SYSTEMS Many applications, such as automatic test systems, require that the outputs of several D/A converters be updated simultaneously. The interface shown in Figure uses a 7LSB18 decoder to decode a set of eight adjacent addresses to load the input latches of four s. The example uses a right-justified data format. A ninth address using A causes all s to be updated simultaneously. If a certain is always loaded last (for instance, D/A #), A is not needed, saving 8 address spaces for other uses. Incorporate A into the base address decoder, remove the inverter, connect the common line to of D/A #, and connect D1 of the 7LS18 to +V. 1- AND 1-BIT MICROCOMPUTER INTERFACE For this application the input latch enable lines, and, are tied low, causing the latches to be transparent. The D/A latch, and therefore, is selected by the address decoder and strobed by. Be sure and read the CAUTION statement in the LOGIC INPUT COMPATIBILITY section..kω NC BPO V V TO +1V RANGE X X X X D11 D1 D D8 D7 D D D D D D1 D Right-Justified FIGURE 7. 1-Bit Data Format for 8-Bit Systems. I DAC.kΩ V to +1V ACOM V REF OUT BPO V NC Ω pot or 1 Ω fixed ±1V RANGE Microcomputer DB DB1 DB DB DB DB DB DB D D8 D1 D D D1 D D11 D D D D7 I DAC.kΩ BPO ±1V ACOM V REF OUT V V Ω pot or 1 Ω fixed ±V RANGE A1 A A1 A Base Address Decoder Reset Circuitry FIGURE 8. Right-Justified Data Bus Interface Reset I DAC ±V ACOM FIGURE. Output Amplifier Voltage Range Scaling Circuit. 1

11 A1 A Base Address Decoder CS (1) A Microcomputer 7LS18 GA Y Y1 GB Y G1 Y Y () A A1 A 1 C B A Y Y Y7 1 7 () ADDRESS BUS A A A1 A OPERATION Load 8 LSB D/A #1 1 Load MSB D/A #1 1 Load 8 LSB D/A # 1 1 Load MSB D/A # 1 Load 8 LSB D/A # 1 1 Load MSB D/A # 1 1 Load 8 LSB D/A # Load MSB D/A # 1 X X X Load D/A Latch All D/A FIGURE. Interfacing Multiple s to an 8-Bit Bus. 11

12 PACKAGE DRAWINGS 1