6-Bit A/D converter (parallel outputs)

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1 DESCRIPTION The is a low cost, complete successive-approximation analog-to-digital (A/D) converter, fabricated using Bipolar/I L technology. With an external reference voltage, the will accept input voltages between V and V REF. An external START pulse of at least ns in duration will provide the -bit result of the conversion in parallel format. Full conversion with no missing codes occurs in 9µs. PIN CONFIGURATION N Package V REF V IN B (MSB) B B ANALOG GND B FEATURES TTL-compatible inputs and outputs -State output buffer Easy interface to CMOS microprocessors Fast conversion 9µs Guaranteed no missing codes over full temp range Single-supply operation, +V Positive true binary outputs High-impedance analog inputs APPLICATIONS Temperature control DIGITAL GND START CS µp-based appliances Light level monitors Head position sensing Electronic toys Joystick interface 8 9 TOP VIEW B B EO ORDERING INFORMATION DESCRIPTION TEMPERATURE RANGE ORDER CODE DWG # -Pin Plastic Dual In-Line Package (DIP) to + C N C BLOCK DIAGRAM V REF V IN A GND D GND V/I V/I I IN CONTROL LOGIC / LSB BIT DAC SAR I O COM DB DB DB DB O 8 9 START CS August,

2 ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER RATING UNIT Power supply voltage V V REF Reference voltage V V IN(Analog) Analog input voltage V V IN(Digital) Digital input voltage (CS, OE, START, ) V D OUT Data outputs (DB to DB) -state mode V Enabled mode (each output) ma End of conversion GND Analog GND to digital GND ± V T A Operating temperature range to C T STG Storage temperature range - to C T SOLD Lead soldering temperature ( seconds) C P D Maximum power dissipation, T A = C (still-air) NOTES:. Derate above C at the following rates: N package=.mw/ C N package mw DC ELECTRICAL CHARACTERISTICS =.V; V REF =.V; Clock=MHz; C T A C unless otherwise specified. Typical values are specified at C SYMBOL PARAMETER TEST CONDITIONS LIMITS Min Typ Max Resolution Bits Relative accuracy, / / LSB Positive supply voltage V ε FS Full-scale gain error,, V REF =.V, T A = C ± ± LSB ε ZS Zero-scale offset error V REF =.V, T A = C ±/ -/, + LSB PSR Power supply rejection, Max change in full-scale V REF =.V,.V.V ±/ ± LSB I IN Analog input bias current V IN.V µa I REF Reference bias current V REF.V µa R IN Analog input resistance MΩ V IH Logic input voltage. V V IL Logic input voltage.8 V I IH Logic input current µa I IL Logic input current µa I OH Logic output current.v V OH µa I OL Logic output current V OL.V. ma I OZ -State leakage current ±. ± µa I CC Positive supply current 8 ma P D Power dissipation mw NOTES:. Relative accuracy is defined as the deviation of the code transition points from the ideal code transition points on a straight line drawn from zero-scale to full-scale of the device.. Specifications given in LSBs refer to the weight of the least significant bit at the -bit level which is.% of the full-scale voltage.. Full-scale gain error is the deviation of the full-scale code transition point ( to ) from its ideal value.. The analog input voltage (V IN ) range is V to V REF nominally, with the output remaining at even though the input may increase from V REF to. (For optimum performance, V REF can be any value from.v to.v.). The data outputs have active pull-ups. The line is open-collector with a nominal kω internal pull-up resistor. UNIT August, 99 8

3 AC ELECTRICAL CHARACTERISTICS =.V; V REF =.V; Clock=MHz; C T A C unless otherwise specified. Typical values are specified at C (Refer to AC test figures.) SYMBOL PARAMETER TO FROM TEST CONDITIONS LIMITS Min Typ Max f MAX Maximum clock frequency MHz t W Start pulse width ns Minimum positive/negative clock pulse width UNIT ns t CONV Conversion time 9 Clock cycles t P (OUT DATA) Propagation delay Data out OE T A = C t R =t F ns ns t P (OUT ) Propagation delay Clock T A = C t R =t F ns 8 ns t P (-STATE) Propagation delay, -State -State Data OE T A = C t R =t F ns ns NOTES:. Propagation delay of data outputs is defined as the delay in the data outputs reading their final value after the low going edge of OE.. Propagation delay of is defined as the delay in going low, following the low going edge of the 9th clock pulse after the start pulse. CIRCUIT DESCRIPTION is a complete -bit, parallel output, microprocessor compatible, A/D converter which incorporates the successive-approximation method. The chip includes the internal control logic, the successive-approximation register (SAR), -bit DAC, comparator and output buffers. An externally-generated clock source (max frequency=mhz) must be provided to Pin. An external reference voltage supplied to Pin sets the full-scale range of the A/D converter. The CS pin must be at a low level prior to the start of the conversion process. Upon receipt of a START pulse, the internal control logic resets the SAR. On the first low-going edge of the clock pulse, successive approximation conversion commences. Successive bits beginning with the MSB (D) are supplied to the input of the internal -bit current output DAC by the I L successive approximation register. CS START The comparator determines whether the output current of the DAC is greater or less than the input current, which is converted from the unknown analog input voltage through the V/I converter. If the DAC output is greater, that bit of the DAC is set to and the corresponding output buffer goes to simultaneously. If it is less, it stays at and the output buffer also stays at. On successive clock pulses, successive bits of the DAC are tried and the corresponding output buffer represents the bits of the DAC. On the eighth low-going edge of the clock pulse (after the receipt of the start pulse), the pin goes low, thereby indicating that the conversion is complete. The output data is now valid. In order to access the result of the conversion, the OE pin must be set to a low level. is reset to a high state when OE is low. When OE is in a state, the output buffers are in a high impedance state. Refer to Figure for the timing diagram. ÉÉÉÉÉÉÉÉÉÉÉÉ DON T CARE ÉÉÉ ÉÉ OE DATA OUTPUTS IMPEDANCE IMPEDANCE IMPEDANCE DATA READY Figure. Timing Diagram AVAILABLE AVAILABLE August, 99 8

4 TRANSFER CHARACTERISTICS The ideal transfer characteristic of the is shown in Figure. The is designed to have a nominal LSB offset so that the code transition points are located LSB on either side of the exact analog inputs for a given code. Thus the first transition ( to ) will occur at an input of LSB (.mv with a V REF of.v). Subsequent transitions will occur at nominal increments of LSB. The last transition (to full-scale ) will occur at. LSB (.9V at V REF of.v). LAYOUT PRECAUTIONS Analog ground (Pin ) and digital ground (Pin ) are not connected internally and should be connected together as close to the device as possible for optimum performance. The circuit will operate with as much as ±mv between the two grounds but some degradation will occur. The leads to the analog inputs should be kept as short as possible to minimize noise pick-up. Input bypass capacitors from the analog inputs to ground will eliminate noise pick-up. Power supplies should be decoupled with at least µf located close to the device to minimize the effects of noise spikes. The reference input and the analog voltage input must both remain stable during conversion to insure accuracy and proper operation. This can be done by adequately bypassing these inputs and/or keeping the impedance of these inputs at or below kω. DIGITAL OUTPUT CODE / LSB / LSB / LSB / LSB 9/ LSB ANALOG INPUT / LSB LSB / LSB / LSB V REF FOR OUTPUT V IN = V REF LSB / LSB BUILT IN OFFSET.LSB. V REF Figure. Ideal Transfer Characteristics August, 99 8

5 TYPICAL PERFORMANCE CHARACTERISTICS Zero Scale Offset Error vs Temp Zero Scale Offset Error vs v cc Zero Scale Offset Error vs v REF Z F OFFSET ERROR (LSB s) +/ +/ +/ =.V V REF =.V Z F OFFSET ERROR (LSB s) +/ +/ +/ V REF =.V T A = o C Z F OFFSET ERROR (LSB s) +/ +/ +/ =.V T A = o C (VOLTS DC) V REF (VOLTS DC) Z F GAIN ERROR (LSB s) Full Scale GAIN Error vs Temp Full Scale Gain Error vs v cc Full Scale Gain Error vs v REF =.V T A = o C + / + +/ =.V V REF =.V Z F GAIN ERROR (LSB s) + / + +/ V REF =.V T A = o C Z F GAIN ERROR (LSB s) + / + +/.... (VOLTS DC)... V REF (VOLTS DC) I OL vs Temp (Data Output) I OL vs Temp (). I OH vs Temp (Data Output) =.V =.V 9. =.V =.V I OL (ma) =.V I OL (ma) I OH (ma) 8. =.V I V OL =.V DC I V OL =.V DC. I V OL =.V DC. I CC vs Temp (). I OH vs Temp () V REF =.V. =.V I CC (ma) =.V =.V I OH (ma). =.V. I V OH =.V DC. August, 99 8

6 AC TEST CIRCUITS AND WAVEFORMS = V V REF = V V IN =.V MHz (TTL) pf DATA OUTPUT kω tp (DATA) OE 9% % % R = t F = ns 9% % % START PULSE (TTL LEVEL) EO (TTL LEVEL) t F t R % DB ( TO ) % tp (DATA) tp ( STATE) Propagation Delay Time t P (DATA) and T P (-state) R = t F = ns = V V REF = V V IN =.V MHz (TTL) START PULSE (TTL LEVEL) = +V K pf EO (TTL LEVEL) DATA OUTPUT OE DB ( TO ) % t F % GND GND 9% % % % t R tp (DATA) tp ( STATE) Data Output High = +V V REF = +V MHz TTL (CLOCK) START PULSE (TTL LEVEL) EO = kω START 9% 9% % % t R t F t W % 9 % tp () Propagation Delay Time t P() August, 99 8

7 +V LM.µF.µF RANGE.K (F). K (C) pf K.µF A/D STRT 8 CS 9 OE CONTROLLER K BIAS ADJ. K 8 + / NE + / NE BIT DATA BUS 8.µF 9 DISPLAY READING o F o C VOLTAGE TP.89.8 TP* V TP TP +V a. Temperature Sensor.µF LM K BIAS ADJ. K.µF RANGE.K (F). K (C) µF / NE pf 9 K + / NE.µF.µF A/D NLS BIT LATCH 9 8 N8S PROM (DECODER/ DRIVER) OPEN DIS s Q N9 DIS s TP* V TP TP DISPLAY READING o F o C U PIN 8 GND VOLTAGE TP.89.8 Q N98 b. Digital Thermometer Figure. August, 99 88

8 APPLICATION to C Temperature Sensor CIRCUIT DESCRIPTION The temperature sensor of Figure provides an input to Pin of the of mv/ C. This mv is the value of one LSB for the. The LM is a three-terminal temperature sensor and provides a current of µa for each Kelvin. The first section of the dual op amp is connected as a trans-impedance amplifier to convert the current from the LM to a voltage, which is amplified and inverted by the section amplifier. Note that the first amplifier requires different values of feedback resistance for C and F. The NE was chosen for its low temperature coefficient of input bias current as excessive I OS tempco would degrade temperature tracking. To read temperature, conversion is started by sending a momentary low signal to Pin of the. When Pin of the goes low, conversion is complete and a low is applied to Pin 9 of the to read data on Pins through. Note that this temperature data is in straight binary format. The controller can be a microprocessor in a temperature control application, or discrete circuitry in a simple temperature reporting application. A temperature reporting (digital thermometer) circuit is shown in Figure b. The A/D converter is connected in a continuous conversion mode by connecting together Pins, 9, and. Should this pin be momentarily shorted to any relatively low impedance point, conversion will stop. Conversion will resume upon interruption and restoration of the power. These pins are also connected to the latch enable of a -bit latch because the data at the converter output is available for only a short time when the converter is in the continuous conversion mode. The (P)ROM) must have the correct code for converting the data from the (used as address for the (P)ROMs) to the appropriate segment drive codes. Note that the circuit of Figure b shows a circuit which can be used to display either Fahrenheit or Centigrade temperatures. The displayed output could easily be converted to degrees Fahrenheit ( F) by the controller of Figure a or through the (P)ROMs of Figure b. When doing this, a third (hundreds) digit (P)ROM and display will be needed for displaying temperatures above 99 F. An inexpensive clock can be made from NAND gates or inverters, as shown in Figure c. CIRCUIT ADJUSTMENT The circuit should be at a known ambient temperature for a few minutes before making adjustments..adjust bias adjust potentiometer for the voltage indicated in the chart in Figure b..with the circuit (or sensor U, if it is remotely located) at a known temperature for to minutes, adjust range control for a correct reading on the displays. This should provide an accuracy of ± counts ( F or C). Higher accuracy may require reference voltage regulation. August, 99 89

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