Octal Sample-and-Hold with Multiplexed Input SMP18

Transcription

1 a FEATURES High Speed Version of SMP Internal Hold Capacitors Low Droop Rate TTL/CMOS Compatible Logic Inputs Single or Dual Supply Operation Break-Before-Make Channel Addressing Compatible With CD Pinout Low Cost APPLICATIONS Multiple Path Timing Deskew for A.T.E. Memory Programmers Mass Flow/Process Control Systems Multichannel Data Acquisition Systems Robotics and Control Systems Medical and Analytical Instrumentation Event Analysis Stage Lighting Control GENERAL DESCRIPTION The SMP is a monolithic octal sample-and-hold; it has eight internal buffer amplifiers, input multiplexer, and internal hold capacitors. It is manufactured in an advanced oxide isolated CMOS technology to obtain high accuracy, low droop rate, and fast acquisition time. The SMP has a typical linearity error of only.% and can accurately acquire a -bit input signal to ±/ LSB in less than. microseconds. The SMP s output swing includes the negative supply in both single and dual supply operation. The SMP was specifically designed for systems that use a calibration cycle to adjust a multiple of system parameters. The low cost and high level of integration make the SMP ideal for calibration requirements that have previously required an ASIC, or high cost multiple D/A converters. The SMP is also ideally suited for a wide variety of sampleand-hold applications including amplifier offset or VCA gain adjustments. One or more SMPs can be used with single or multiple DACs to provide multiple set points within a system. INPUT Octal Sample-and-Hold with Multiplexed Input SMP FUNCTIONAL BLOCK DIAGRAM HOLD CAPS (INTERNAL) SMP (LSB) A B OF DECODER (MSB) C INH CH OUT CH OUT CH OUT CH OUT DGND V DD CH OUT CH OUT CH OUT CH OUT The SMP offers significant cost and size reduction over discrete designs. It is available in a -pin plastic DIP, a narrow body SO- surface-mount SOIC package or the thin TSSOP- package. The SMP is a higher speed direct replacement for the SMP. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box, Norwood, MA -, U.S.A. Tel: /- World Wide Web Site: Fax: /- Analog Devices, Inc.,

2 SMP SPECIFICATIONS ELECTRICAL CHARACTERISTICS Parameter Symbol Conditions Min Typ Max Units Linearity Error V V IN + V. % Buffer Offset Voltage V OS T A = + C, V IN = V. mv C T A + C, V IN = V. mv Hold Step V HS V IN = V, T A = + C to + C mv V IN = V, T A = C mv Droop Rate V CH / t T A = + C, V IN = V mv/s Output Source Current I SOURCE V IN = V. ma Output Sink Current I SINK V IN = V. ma Output Voltage Range R L = kω. +. V LOGIC CHARACTERISTICS Logic Input High Voltage V INH. V Logic Input Low Voltage V INL. V Logic Input Current I IN V IN =. V. µa DYNAMIC PERFORMANCE Acquisition Time t AQ T A = + C, V to + V to.%. µs Hold Mode Settling Time t H To ± mv of Final Value µs Channel Select Time t CH ns Channel Deselect Time t DCS ns Inhibit Recovery Time t IR ns Slew Rate SR V/µs Capacitive Load Stability <% Overshoot pf Analog Crosstalk V to + V Step db SUPPLY CHARACTERISTICS Power Supply Rejection Ratio PSRR = ± V to ± V db Supply Current I DD T A = + C.. ma C T A + C.. ma ELECTRICAL CHARACTERISTICS (@ V DD = + V, = V, DGND = V, R L = No Load, T A = C to + C for SMPF, unless otherwise noted) (@ V DD = + V, = V, DGND = V, R L = No Load, T A = C to + C for SMPF, unless otherwise noted) Parameter Symbol Conditions Min Typ Max Limits Linearity Error mv V IN V. % Buffer Offset Voltage V OS T A = + C, V IN = V. mv C T A + C, V IN = V. mv Hold Step V HS V IN = V, T A = + C to + C mv V IN = V, T A = C mv Droop Rate V CH / t T A = + C, V IN = V mv/s Output Source Current I SOURCE V IN = V. ma Output Sink Current I SINK V IN = V. ma Output Voltage Range R L = kω.. V R L = kω.. V LOGIC CHARACTERISTICS Logic Input High Voltage V INH. V Logic Input Low Voltage V INL. V Logic Input Current I IN V IN =. V. µa DYNAMIC PERFORMANCE Acquisition Time t AQ T A = + C, to V to.%.. µs Hold Mode Settling Time t H To ± mv of Final Value µs Channel Select Time t CH ns Channel Deselect Time t DCS ns Inhibit Recovery Time t IR ns Slew Rate SR V/µs Capacitive Load Stability <% Overshoot pf Analog Crosstalk V to V Step db SUPPLY CHARACTERISTICS Power Supply Rejection Ratio PSRR. V V DD. V db Supply Current I DD T A = + C.. ma C T A + C.. ma NOTES Outputs are capable of sinking and sourcing over ma but offset is guaranteed at specified load levels. All input control signals are specified with t r = t f = ns (% to % of + V) and timed from a voltage level of. V. This parameter is guaranteed without test. Slew rate is measured in the sample mode with a to V step from % to %. Specifications subject to change without notice.

3 SMP ABSOLUTE MAXIMUM RATINGS V DD to DGND V, V V DD to V, V V LOGIC to DGND V, V DD V IN to DGND , V DD V OUT to DGND , V DD Analog Output Current ± ma (Not short-circuit protected) Operating Temperature Range FP, FS C to + C Junction Temperature C Storage Temperature C to + C Lead Temperature (Soldering, sec) C PIN CONNECTIONS CH OUT CH OUT INPUT CH OUT CH OUT INH DGND SMP TOP VIEW (Not to Scale) V DD CH OUT CH OUT CH OUT CH OUT A CONTROL B CONTROL C CONTROL Package Type JA * JC Units -Pin Plastic DIP (P) C/W -Pin SOIC (S) C/W -Lead TSSOP (RU) C/W NOTES *θ JA is specified for worst case mounting conditions, i.e., θ JA is specified for device in socket for plastic DIP packages; θ JA is specified for device soldered to printed circuit board for SOIC and TSSOP packages. ORDERING GUIDE Temperature Package Package Model Range Description Option SMPFP C to + C Plastic DIP N- SMPFRU C to + C TSSOP- RU- SMPFS C to + C SO- R-A CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as V readily accumulate on the human body and test equipment and can discharge without detection. Although the SMP features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE

4 SMP Typical Performance Characteristics DROOP RATE mv/s. V DD = +V = V V IN = +V R L = kω. TEMPERATURE C DROOP RATE mv/s V DD = +V = V T A = + C DROOP RATE mv/s V DD = +V = V T A = + C Droop Rate vs. Temperature Droop Rate vs. Input Voltage Droop Rate vs. Input Voltage HOLD STEP mv V DD = +V = V T A = + C HOLD STEP mv V DD = +V = V V IN = V SLEW RATE V/µs V DD = +V = V T A = + C +SR SR TEMPERATURE C V DD Volts Hold Step vs. Input Voltage Hold Step vs. Temperature Slew Rate vs. V DD OFFSET VOLTAGE mv R L = R L = kω R L = kω V DD = +V = V T A = + C OFFSET VOLTAGE mv V DD = +V = V T A = + C R L = R L = kω R L = kω OFFSET VOLTAGE mv R L = R L = kω V DD = +V = V T A = C R L = kω Offset Voltage vs. Input Voltage Offset Voltage vs. Input Voltage Offset Voltage vs. Input Voltage

5 Typical Performance Characteristics SMP OFFSET VOLTAGE mv V DD = +V = V V IN = +V R L = kω SUPPLY CURRENT ma = V + C + C C REJECTION RATIO db PSRR +PSRR V DD = +V = V V IN = +V T A = + C TEMPERATURE C V DD Volts k k k M Offset Voltage vs. Temperature Supply Current vs. V DD Sample Mode Power Supply Rejection GAIN db V DD = +V = V T A = + C PHASE GAIN PHASE SHIFT Degrees OUTPUT IMPEDANCE Ω V DD = +V = V T A = + C k k k M M k k k M Gain, Phase Shift vs. Frequency Output Impedance vs. Frequency PEAK-TO-PEAK OUTPUT Volts V DD = +V = V T A = + C k k M M REJECTION RATIO db V DD = +V = V T A = + C +PSRR HOLD CAPACITORS REFERENCED TO PSRR k k k M Maximum Output Voltage vs. Frequency Hold Mode Power Supply Rejection

6 SMP R kω R kω V CC +V D R Ω C µf + C µf SMP R kω R kω R kω R kω R kω R kω R kω R kω Burn-in Circuit APPLICATIONS INFORMATION The SMP, a multiplexed octal S/H, minimizes board space in systems requiring cycled calibration or an array of control voltages. When used in conjunction with a low cost -bit D/A, the SMP can easily be integrated into microprocessor based systems. Since the SMP features break-before-make switching and an internal decoder, no external logic is required. The SMP has an internally regulated TTL supply so that TTL/CMOS compatibility is maintained over the full supply range. See Figure for channel decode address information. POWER SUPPLIES The SMP is capable of operating with either single or dual supplies over a voltage range of to volts. Based on the supply voltages chosen, V DD and establish the output voltage range, which is: ( +. V ) V OUT (V DD V) Note that several specifications, including acquisition time, offset and output voltage compliance, will degrade for supply voltages of less than V. If split supplies are used, the negative supply should be bypassed with a. µf capacitor in parallel with a µf to ground. The internal hold capacitors are connected to this supply pin, and any noise will appear at the outputs. In single supply applications, it is extremely important that the (negative supply) pin is connected to a clean ground. The hold capacitors are internally tied to the (negative) rail. Any ground noise or disturbance will directly couple to the output of the sample-and-hold degrading the signal-to-noise performance. The analog and digital ground traces on the circuit board should be physically separated to reduce digital switching noise from entering the analog circuitry. POWER SUPPLY SEQUENCING V DD should be applied to the SMP before the logic input signals. The SMP has been designed to be immune to latchup, but standard precautions should still be taken. OUTPUT BUFFERS (Pins,,,,,,, ) The buffer offset specification is mv; this is less than / LSB of an -bit DAC with V full scale. The hold step (magnitude of step caused in the output voltage when switching from sample-to-hold mode, also referred to as the pedestal error or sample-to-hold offset) is about mv with little variation over the full output voltage range. The droop rate of a held channel is mv/s typical and mv/s maximum. The buffers are designed to drive loads connected to ground. The outputs can source more than ma over the full voltage range but have limited current sinking capability near. In split supply operation, symmetrical output swings can be obtained by restricting the output range to V from either supply. On-chip SMP buffers eliminate potential stability problems associated with external buffers; outputs are stable with capacitive loads up to pf. However, since the SMP s buffer outputs are not short circuit protected, care should be taken to avoid shorting any output to the supplies or ground. SIGNAL INPUT (Pin ) The signal input should be driven from a low impedance voltage source such as the output of an op amp. The op amp should have a high slew rate and fast settling time if the SMP s acquisition time characteristics are to be maintained. As with all CMOS devices, all input voltages should be kept within range of the supply rails ( V IN V DD ) to avoid the possibility of latchup. If single supply operation is desired, op amps such as the OP or AD that have input and output voltage compliances including ground, can be used to drive the inputs. Split supplies, such as ±. V, can be used with the SMP.

7 SMP APPLICATION TIPS All unused digital inputs should be connected to logic LOW. For analog inputs that may become temporarily disconnected, a resistor to V DD, or analog ground should be used with a value ranging from kω to MΩ. Do not apply signals to the SMP with power off unless the input current is limited to less than ma. TYPICAL APPLICATIONS An -Channel Multiplexed D/A Converter Figure illustrates a typical demultiplexing function of the SMP. It is used to sample-and-hold eight different output voltages corresponding to eight different digital codes from a D/A converter. The SMP s droop rate of mv/s requires a refresh once every ms before the voltage drifts beyond / LSB accuracy ( LSB of an -bit DAC is equivalent to. mv out of a full-scale voltage of V). For a -bit DAC the refresh rate must be less than ms, and for a -bit system, ms. This implementation is very cost effective compared to using multiple DACs as the number of output channels increases. +V SMP REF +V CH DIGITAL INPUTS +V V REF A V DD CH DAC V OA WR CS V Z GND CH WR ADDRESS BUS ADDRESS DECODE A B C DGND CH CH CH CH PIN C X PIN B X CHANNEL DECODING PIN A X PIN INH CH PIN NONE INH CH +V.µF Figure. -Channel Multiplexed D/A Converter

8 SMP OUTLINE DIMENSIONS Dimensions shown in inches and (mm). -Pin Plastic DIP (N-). (.). (.). (.). (.) PIN. (.). (.). (.) MAX.. (.). (.) (.) MIN. (.). (.). (.) BSC. (.). (.) SEATING PLANE. (.). (.). (.). (.). (.). (.) Ca / -Pin (Narrow Body) (SO-). (.). (.). (.). (.). (.). (.). (.). (.) PIN. (.). (.). (.). (.) x SEATING PLANE. (.) BSC. (.). (.). (.). (.). (.). (.) -Lead TSSOP (RU-). (.). (.). (.). (.). (.). (.). (.). (.) SEATING PLANE PIN. (.) BSC. (.). (.). (.) MAX. (.). (.). (.). (.) PRINTED IN U.S.A.