PART MAX5166NECM MAX5166MCCM MAX5166LECM MAX5166MECM OUT31 MAX5166 TQFP. Maxim Integrated Products 1

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1 9-456; Rev ; 8/99 32-Channel Sample/Hold Amplifier General Description The MAX566 contains four -to-8 multiplexers and 32 sample/hold amplifiers. The sample/hold amplifiers are organized into four octal sample/holds with separate inputs and independent TTL/CMOS-compatible hold enables for each octal set. Additional 3-bit TTL/CMOScompatible address logic selects the -to-8 multiplexer channel. The MAX566 is available with an output impedance of 5Ω, 5Ω, or kω, allowing output filtering. The MAX566 operates with +V and -5V supplies, and a separate +5V digital logic supply. Manufactured with a proprietary BiCMOS process, it provides high accuracy, fast acquisition time, low droop rate, and a low hold step. The device acquires 8V step input signals to.% accuracy in 2.5µs. Transitions from sample mode to hold mode result in only.5mv of error. While in hold mode, the output voltage slowly droops at a rate of mv/sec. The MAX566 is available in a 48-pin TQFP package. Automatic Test Systems (ATE) Industrial Process Controls Arbitrary Function Generators Avionics Equipment Applications Quad, 8-Channel Sample/Hold.% Accuracy of Acquired Signal.% Linearity Error Fast Acquisition Time: 2.5µs Low Droop Rate: mv/sec Low Hold Step:.25mV Wide Output Voltage Range: +7V to -4V PART MAX566LCCM MAX566MCCM MAX566NCCM MAX566LECM MAX566MECM MAX566NECM Features Ordering Information TEMP. RANGE C to +7 C C to +7 C C to +7 C -4 C to +85 C -4 C to +85 C -4 C to +85 C PIN- PACKAGE 48 TQFP 48 TQFP 48 TQFP 48 TQFP 48 TQFP 48 TQFP R OUT (Ω) 5 5 k 5 5 k MAX566 Pin Configuration TOP VIEW A2 M M M2 M3 V L DGND V SS IN3 IN2 IN OUT2 OUT2 OUT9 OUT8 OUT7 OUT6 V DD OUT5 OUT4 OUT3 OUT2 OUT A A OUT3 OUT3 OUT29 OUT28 OUT27 OUT26 OUT25 OUT24 OUT23 OUT22 MAX IN OUT OUT OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8 OUT9 OUT TQFP Maxim Integrated Products For free samples & the latest literature: or phone For small orders, phone

2 MAX566 ABSOLUTE MAXIMUM RATINGS V DD to...-.3v to +.V V SS to...-6.v to +.3V V DD to V SS V V L to DGND...-.3V to +6.V V L to...-.3v to +6.V DGND to...-.3v to +2.V IN_ to...v SS to V DD A_, M_ to DGND...-.3V to +6.V Maximum Current into Output Pin...±mA Maximum Current into A_, M_...±2mA Continuous Power Dissipation (T A = +7 C) 48-Pin TQFP (derate 2.5mW/ C above +7 C)...W Operating Temperature Ranges MAX566_CCM... C to +7 C MAX566_ECM...-4 C to +85 C Storage Temperature Range C to +5 C Lead Temperature (soldering, sec)...+3 C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (V DD = +V, V SS = -5V, V L = +5V ±5%, = DGND, R L = 5kΩ, C L = 5pF, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +25 C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS ANALOG SECTION Linearity Error -4V < V IN < +7V, R L =..8 % Hold Step V HS IN_ =.25. mv Droop Rate V OUT IN_ =, T A = +25 C 4 mv/sec Offset Voltage V OS IN_ =, T A = +25 C mv +5 C T A +65 C (Note ) 2 4 µv/ C Output Voltage Range Analog Crosstalk Input Capacitance DC Output Impedance Output Source Current Output Sink Current TIMING PERFORMANCE Acquisition Time Hold-Mode Settling Time Aperture Delay Inhibit Pulse Width Data Hold Time Data Setup Time V OUT_ C IN_ R OUT_ I SOURCE I SINK (Note ) R L =, C L = 25pF 8V step to.8%, R L =, Figure 2 (Note 2) t AQ T A = +25 C, mv step to ±mv, R L =, Figure 2 (Note 2) t H t AP t PW t DH t DS R L = 8V step with 5ns rising edge (Note ) MAX565L, C L = 25pF MAX565M, C L = nf MAX565N, C L = nf MAX566L MAX566M MAX566N To ±mv of final value, Figure 2 (Note ) Figure 2 (Note ) Figure 2 (Note ) Figure 2 (Note ) Figure 2 (Note ) V SS + V DD V db pf Ω ma ma µs µs ns ns ns ns 2

3 ELECTRICAL CHARACTERISTICS (continued) (V DD = +V, V SS = -5V, V L = +5V ±5%, = DGND, R L = 5kΩ, C L = 5pF, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +25 C.) Input Voltage High Input Voltage Low Input Current PARAMETER DIGITAL INPUTS POWER SUPPLIES Positive Analog Supply Voltage Negative Analog Supply Voltage Digital Logic Supply Voltage Positive Analog Supply Current Negative Analog Supply Current Digital Logic Supply Current SYMBOL V IH V IL I I V DD V SS V L I DD I SS I L A_ = DGND or V L; M_ = DGND or VL (Note 3) (Note 3) R L = R L = A_ = DGND or V L ; M_ = DGND or V L CONDITIONS V A V A3 =.8V or 2V; V M, V M, V M2 =.8V or 2V MIN TYP MAX UNITS V V µa V V V ma ma ma ma MAX566 Power-Supply Rejection Ratio PSRR For both V DD and V SS in sample mode, V IN = db Note : Guaranteed by design. Note 2: Only one M_ input may be asserted low at a time, so only one channel is selected (see Single vs. Simultaneous Sampling). Note 3: Do not exceed the absolute maximum rating for V DD to V SS of +5.75V (see Absolute Maximum Ratings). 3

4 MAX566 Typical Operating Characteristics (V DD = +V, V SS = -5V, V L = +5V, IN_ = +5V, R L =, C L =, = DGND, T A = +25 C, unless otherwise noted.) DROOP RATE (mv/sec) DROOP RATE vs. TEMPERATURE TEMPERATURE ( C) MAX566- DROOP RATE (mv/sec) DROOP RATE vs. INPUT VOLTAGE INPUT VOLTAGE (V) MAX566-6 PSRR (db) POWER-SUPPLY REJECTION RATIO (HOLD MODE) -SUPPLY +SUPPLY, FREQUENCY (khz) MAX566-2 PSRR (db) POWER-SUPPLY REJECTION RATIO (SAMPLE MODE) -SUPPLY +SUPPLY MAX566-3 HOLD STEP (µv) HOLD STEP vs. TEMPERATURE MAX566-4 HOLD STEP (µv) HOLD STEP vs. INPUT VOLTAGE MAX , FREQUENCY (khz) TEMPERATURE ( C) INPUT VOLTAGE (V) OFFSET VOLTAGE vs. TEMPERATURE MAX OFFSET VOLTAGE vs. INPUT VOLTAGE MAX566-8 OFFSET VOLTAGE (mv) OFFSET VOLTAGE (mv) TEMPERATURE ( C) INPUT VOLTAGE (V) 4

5 M3 M2 M M A2 A A 3-TO-8 DECODER 8 8 MAX566 -TO-8 MULTIPLEXER AND MAX566 AND7 EN OUT IN IN OUT7 SAMPLE-AND-HOLD 8 -TO-8 MULTIPLEXER OUT8 EN IN IN OUT5 SAMPLE-AND-HOLD 8 -TO-8 MULTIPLEXER OUT6 EN IN2 IN OUT23 SAMPLE-AND-HOLD 8 -TO-8 MULTIPLEXER OUT24 EN IN3 IN OUT3 SAMPLE-AND-HOLD V SS V DD V L DGND Figure. Functional Diagram 5

6 MAX566 PIN NAME, 47, 48 A2, A, A 2 5 M M3 FUNCTION Pin Description Address Inputs. The input of a 3-to-8 decoder that controls channel selection for all four -to-8 multiplexers. Selects which output channels are connected to the input during sample mode (Tables, 2). Mode-Selection/Multiplexer-Enable Inputs to 3. All four -to-8 multiplexers are independently controlled. A logic low enables sample mode by connecting the selected channel to IN_. A logic high enables hold mode (Tables, 2). 6 V L Positive Digital Logic Power-Supply Input 7 DGND Digital Ground 8 V SS Negative Analog Power-Supply Input 9 Analog Ground 3 IN3 IN Analog Inputs to OUT OUT5 Outputs to 5 3 V DD Positive Analog Power-Supply Input 3 46 OUT6 OUT3 Outputs 6 to 3 Detailed Description The MAX566 connects four separate analog inputs to four internal -to-8 analog multiplexers. Each multiplexer channel connects to a buffered sample/hold circuit and a series output resistor, creating a four-input device with 32 sample/hold output channels. Three multiplexer channel-address inputs and four modeselect inputs (one for each multiplexer) control channel selection and sample/hold functions (Figure and Tables and 2). Digital Interface Three address pins and 3-to-8 address decoder logic select the channel for all four internal analog multiplexers. The mode-select inputs (M3 M) independently control the sample/hold functions for each multiplexer (Tables and 2). Sample/Hold The MAX566 contains 32 buffered sample/hold circuits with internal hold capacitors. Internal hold capacitors minimize leakage current, dielectric absorption, feedthrough, and required board space. The value of the hold capacitor affects acquisition time, hold step, and droop rate. Lower capacitance allows faster acquisition times but increases the droop rate. Higher values increase hold time and acquisition time. The hold capacitor used in the MAX566 provides fast 2.5µs (typ) acquisition time while maintaining a low mv/sec (typ) droop rate, making the sample/hold ideal for highspeed sampling. Sample Mode Driving M3 M low (one at a time) selects sample mode (Tables and 2). During sample mode, the selected multiplexer channel connects to IN_ allowing the hold capacitor to acquire the input signal. To guarantee an accurate sample, maintain sample mode for at least 4µs. Sampling for longer than 4µs results in tracking. Only the addressed channel on the selected multiplexer samples the input; all other channels remain in hold mode. Hold Mode Driving M3 M high selects hold mode. Hold mode disables the multiplexer, which disconnects all eight channels on the -to-8 multiplexer from the input. When a channel is disconnected, the hold capacitor maintains the sampled voltage at the output with a mv/sec droop rate (towards V DD ). 6

7 Table. Output Selection OUTPUT SELECTED A2 A A MUX MUX MUX2 MUX3 OUT OUT OUT8 OUT9 OUT6 OUT7 OUT24 OUT25 OUT2 OUT OUT8 OUT26 OUT3 OUT OUT9 OUT27 OUT4 OUT2 OUT2 OUT28 OUT5 OUT3 OUT2 OUT29 OUT6 OUT4 OUT22 OUT3 OUT7 OUT5 OUT23 OUT3 MAX566 = Logic Low, = Logic High Table 2. Mode Selection MODE-SELECT INPUTS* (M3 M) ACTION Sample mode enabled on selected analog multiplexer and channel (Table ). Hold mode enabled on selected analog multiplexer and channel (Table ). = Logic Low, = Logic High * Only one M_ input asserted low; all others must be logic high to meet the timing specification (see Single vs. Simultaneous Sampling). Hold Step When switching between sample mode and hold mode, the voltage of the hold capacitor changes due to charge injection from stray capacitance. This voltage change, called hold step, is minimized by limiting the amount of stray capacitance seen by the hold capacitor. The MAX566 limits the hold step to.25mv (typ). An output capacitor to ground can be used to filter out this small hold-step error. Output The MAX566 contains an output buffer for each multiplexer channel (32 total), so the hold capacitor sees a high-impedance input, reducing the droop rate. While in hold mode, the hold capacitor discharges at a rate of mv/sec (typ). The buffer also provides a low output impedance; however, the device contains output resistors in series with the buffer output (Figure ) for selected output filtering. To provide greater design flexibility, the MAX566 is available with an RO of 5Ω, 5Ω, or kω. Note: Output loads increase the analog supply current (IDD and ISS). Excessive loading of the output(s) damages the device by consuming more power than the device will dissipate (see Absolute Maximum Ratings). The resistor-divider formed by the output resistor (ROUT_) and load impedance (RL) scales the sampled voltage (VSAMP). Determine the output voltage (VOUT_) as follows: Voltage Gain = AV = RL/(RL + ROUT) VOUT_ = VSAMP AV The maximum output voltage range depends on the analog supply voltages available and the scaling factor used: (VSS +.75V) AV VOUT_ (VDD - 2.4V) AV when RL =, then AV =, and this equation becomes (VSS +.75V) VOUT (VDD - 2.4V). Timing Definitions Acquisition time (taq) is the amount of time the MAX566 must remain in sample mode for the hold capacitor to acquire an accurate sample. The holdmode settling time (th) is the amount of time necessary for the output voltage to settle to its final value. Aperture delay (tap) is the time interval required to disconnect the input from the hold capacitor. The inhibit pulse width (tpw) is the amount of time the MAX566 must remain in hold mode while the address is changed. The data setup time (tds) is the amount of time an address must be maintained before the address becomes valid. The data hold time (tdh) is the amount of time an address must be maintained after mode select has gone from low to high (Figure 2). 7

8 MAX566 MODE SELECT (A A2) t PW t DS t DH OUTPUT t H HOLD STEP INPUT t AQ t AP Figure 2. Timing Performance Applications Information Combining Inputs The MAX566 contains a separate input for each -to-8 multiplexer. Externally connect the input pins to form larger multiplexers. When all four inputs are connected to the same source, the MAX566 is functionally equivalent to the MAX565, except the MAX566 does not contain output clamping diodes. Control-Line Reduction The MAX566 contains four separate -to-8 multiplexers and individual mode selectors for each multiplexer. When sampling one channel at a time, use an external 2-to-4 decoder (with active-low outputs) to reduce the number of digital control lines from seven to five (Figure 3). Single vs. Simultaneous Sampling Individually control the four mode/multiplexer-select pins to simultaneously sample on four channels, the same channel for each multiplexer (Figure 4). Each mode-select pin controls sampling on one of the -to-8 multiplexers, while the 3-bit address selects one of the eight channels on all the multiplexers (Tables and 2). Setting any combination of the mode-select pin low enables sampling on the addressed channels for the selected multiplexers. Simultaneously sampling two or more channels reduces offset voltage but increases acquisition time. Multiply the single-channel acquisition time by the number of channels sampling. Multiplexed DAC Figure 5 shows a typical demultiplexer application. Different digital codes are converted by the digital-toanalog converter (DAC) and then stored on eight different channels, or as many as 32 different channels when all four inputs are active. The mv/sec (max) droop rate requires refreshing the hold capacitors every ms before the voltage drops by /2LSB for an 8-bit DAC with a 5V full-scale voltage. Powering the MAX566 The MAX566 does not require a special power-up sequence to avoid latchup. The device requires three separate supply voltages for operation; however, when one or two of the voltages are not available, DC-DC charge-pump (switched-capacitor) converters provide a simple, efficient solution. The MAX86 provides voltage doubling or inversion, ideal for conversions from +5V to +V or from +5V to -5V. The MAX86 also functions as a voltage divider to provide conversion from +V to +5V. 8

9 CHANNEL 5 3 A A2 3 2 MODE SELECTOR DECODER M M M2 M3 DECODER /6 MAX566 MAX566 IN OUT INPUT SIGNAL IN IN2 IN3 OUT24 Figure 3. Control-Line Reduction CHANNEL 3 A A2 3 DECODER /6 MAX566 MODE/MULTIPLEXER SELECTION M M M2 M3 IN OUT INPUT SIGNAL IN IN2 IN3 OUT24 Figure 4. Simultaneous Sampling 9

10 MAX566 CHANNEL MODE/MULTIPLEXER SELECTION 3 A A2 3 M M M2 M3 DECODER /6 MAX566 OUT DIGITAL INPUTS DAC IN OUT7 IN IN2 IN3 Figure 5. Multiplexing a DAC Chip Information TRANSISTOR COUNT: 577

11 Package Information TQFPPO.EPS MAX566

12 MAX566 NOTES Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 2 Maxim Integrated Products, 2 San Gabriel Drive, Sunnyvale, CA Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.