Dual, Low Power Video Op Amp AD828

Transcription

1 a FEATURES Excellent Video Performance Differential Gain and Phase Error of.% and. High Speed MHz db Bandwidth (G = +) V/ s Slew Rate ns Settling Time to.% Low Power ma Max Power Supply Current High Output Drive Capability ma Minimum Output Current per Amplifier Ideal for Driving Back Terminated Cables Flexible Power Supply Specified for + V, V, and V Operation. V Min Output Swing into a Load (V S = V) Excellent DC Performance. mv Input Offset Voltage Available in -Lead SOIC and -Lead Plastic Mini-DIP GENERAL DESCRIPTION The is a low cost, dual video op amp optimized for use in video applications that require gains of + or greater and high output drive capability, such as cable driving. Due to its low power and single-supply functionality, along with excellent differential gain and phase errors, the is ideal for powersensitive applications such as video cameras and professional video equipment. With video specs like. db flatness to MHz and low differential gain and phase errors of.% and., along with ma of output current per amplifier, the is an excellent choice for any video application. The MHz gain bandwidth and V/µs slew rate make the useful in many high speed applications, including video monitors, CATV, color copiers, image scanners, and fax machines. R T +V / V. F. F R BT Figure. Video Line Driver Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. R T Dual, Low Power Video Op Amp FUNCTIONAL BLOCK DIAGRAM OUT IN +IN V One Technology Way, P.O. Box 9, Norwood, MA -9, U.S.A. Tel: /9- Fax: /- Analog Devices, Inc., V+ OUT The is fully specified for operation with a single V power supply and with dual supplies from ± V to ± V. This power supply flexibility, coupled with a very low supply current of ma and excellent ac characteristics under all power supply conditions, make the the ideal choice for many demanding yet power-sensitive applications. The is a voltage feedback op amp that excels as a gain stage (gains > +) or active filter in high speed and video systems and achieves a settling time of ns to.%, with a low input offset voltage of mv max. The is available in low cost, small -lead plastic mini-dip and SOIC packages. DIFFERENTIAL PHASE Degrees... DIFF PHASE DIFF GAIN. SUPPLY VOLTAGE V IN +IN Figure. Differential Phase vs. Supply Voltage... DIFFERENTIAL GAIN Percent

2 SPECIFICATIONS T A = C, unless otherwise noted.) Parameter Conditions V S Min Typ Max Unit DYNAMIC PERFORMANCE db Bandwidth Gain = + ± V MHz ± V MHz, + V MHz Gain = ± V MHz ± V MHz, + V MHz Bandwidth for. db Flatness Gain = + ± V MHz C C = pf ± V MHz, + V MHz Gain = ± V MHz C C = pf ± V MHz, + V 9 MHz Full Power Bandwidth* V OUT = V p-p R LOAD = Ω ± V. MHz V OUT = V p-p R LOAD = kω ± V. MHz Slew Rate R LOAD = kω ± V V/µs Gain = ± V V/µs, + V V/µs Settling Time to.%. V to +. V ± V ns V V Step, A V = ± V ns Settling Time to.%. V to +. V ± V ns V V Step, A V = ± V ns NOISE/HARMONIC PERFORMANCE Total Harmonic Distortion F C = MHz ± V db Input Voltage Noise f = khz ± V, ± V nv/ Hz Input Current Noise f = khz ± V, ± V. pa/ Hz Differential Gain Error NTSC ± V.. % (R L = Ω) Gain = + ± V.. %, + V. % Differential Phase Error NTSC ± V..9 Degrees (R L = Ω) Gain = + ± V.. Degrees, + V. Degrees DC PERFORMANCE Input Offset Voltage ± V, ± V. mv T MIN to T MAX mv Offset Drift µv/ C Input Bias Current ± V, ± V.. µa T MIN µa T MAX. µa Input Offset Current ± V, ± V na T MIN to T MAX na Offset Current Drift. na/ C Open-Loop Gain V OUT = ±. V ± V R LOAD = Ω V/mV T MIN to T MAX V/mV R LOAD = Ω V/mV V OUT = ± V ± V R LOAD = kω. 9 V/mV T MIN to T MAX. V/mV V OUT = ±. V ± V R LOAD = Ω ( ma Output) V/mV INPUT CHARACTERISTICS Input Resistance kω Input Capacitance. pf Input Common-Mode Voltage Range ± V V.. V ± V + +. V. V, + V V V Common-Mode Rejection Ratio V CM = +. V, T MIN to T MAX ± V db V CM = ± V ± V db T MIN to T MAX ± V db

3 Parameter Conditions V S Min Typ Max Unit OUTPUT CHARACTERISTICS Output Voltage Swing R LOAD = Ω ± V.. ± V R LOAD = Ω ± V.. ± V R LOAD = kω ± V.. ± V R LOAD = Ω ± V.. ± V. R LOAD = Ω, + V. ± V Output Current ± V ma ± V ma, + V ma Short Circuit Current ± V ma Output Resistance Open-Loop Ω MATCHING CHARACTERISTICS Dynamic Crosstalk f = MHz ± V db Gain Flatness Match G = +, f = MHz ± V. db Skew Rate Match G = ± V V/µs DC Input Offset Voltage Match T MIN to T MAX ± V, ± V. mv Input Bias Current Match T MIN to T MAX ± V, ± V.. µa Open-Loop Gain Match V O = ± V, R L = kω, T MIN to T MAX ± V.. mv/v Common-Mode Rejection Ratio Match V CM = ± V, T MIN to T MAX ± V db Power Supply Rejection Ratio Match ± V to ± V, T MIN to T MAX db POWER SUPPLY Operating Range Dual Supply ±. ± V Single Supply + + V Quiescent Current ± V. ma T MIN to T MAX ± V. ma T MIN to T MAX ± V ma Power Supply Rejection Ratio V S = ± V to ± V, T MIN to T MAX db *Full power bandwidth = slew rate/ π V PEAK. Specifications subject to change without notice. ABSOLUTE MAXIMUM RATINGS Supply Voltage ± V Internal Power Dissipation Plastic DIP (N) See Derating Curves Small Outline (R) See Derating Curves Input Voltage (Common Mode) ±V S Differential Input Voltage ± V Output Short Circuit Duration See Derating Curves Storage Temperature Range (N, R) C to + C Operating Temperature Range C to + C Lead Temperature Range (Soldering sec) C NOTES Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Specification is for device in free air: -Lead Plastic DIP Package: θ JA = C/W -Lead SOIC Package: θ JA = C/W MAXIMUM POWER DISSIPATION Watts.... ORDERING GUIDE -LEAD MINI-DIP PACKAGE -LEAD SOIC PACKAGE T J = C AMBIENT TEMPERATURE C Figure. Maximum Power Dissipation vs. Temperature for Different Package Types CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as V readily accumulate on the human body and test equipment and can discharge without detection. Although WARNING! the features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Temperature Package Package Model Range Description Option AN C to + C -Lead Plastic DIP N- AR C to + C -Lead Plastic SOIC SO- AR-REEL C to + C " Tape and Reel SO- AR-REEL C to + C " Tape and Reel SO- ESD SENSITIVE DEVICE

4 Typical Performance Characteristics INPUT COMMON-MODE RANGE V +V CM VCM SUPPLY VOLTAGE V TPC. Common-Mode Voltage Range vs. Supply Voltage QUIESCENT SUPPLY CURRENT PER AMP ma C C + C. SUPPLY VOLTAGE V TPC. Quiescent Supply Current per Amp vs. Supply Voltage for Various Temperatures OUTPUT VOLTAGE SWING V R L = R L = SLEW RATE V/ s SUPPLY VOLTAGE V TPC. Output Voltage Swing vs. Supply Voltage SUPPLY VOLTAGE V TPC. Slew Rate vs. Supply Voltage OUTPUT VOLTAGE SWING V p-p Vs = V Vs = V CLOSED-LOOP OUTPUT IMPEDANCE. k k LOAD RESISTANCE TPC. Output Voltage Swing vs. Load Resistance. k k k M M M TPC. Closed-Loop Output Impedance vs. Frequency

5 PHASE V OR V SUPPLIES INPUT BIAS CURRENT A OPEN-LOOP GAIN db V SUPPLIES V SUPPLIES PHASE MARGIN Degrees R L = TEMPERATURE C TPC. Input Bias Current vs. Temperature k k k M M M TPC. Open-Loop Gain and Phase Margin vs. Frequency G 9 SHORT CIRCUIT CURRENT ma SINK CURRENT SOURCE CURRENT OPEN-LOOP GAIN V/mV V V TEMPERATURE C TPC. Short Circuit Current vs. Temperature k k LOAD RESISTANCE TPC. Open-Loop Gain vs. Load Resistance PHASE MARGIN Degrees GAIN BANDWIDTH PHASE MARGIN db BANDWIDTH MHz PSRR db +SUPPLY SUPPLY TEMPERATURE C TPC 9. db Bandwidth and Phase Margin vs. Temperature, Gain = + k k k M M M TPC. Power Supply Rejection vs. Frequency

6 = V p-p GAIN = + CMR db HARMONIC DISTORTION db ND HARMONIC RD HARMONIC k k k M M TPC. Common-Mode Rejection vs. Frequency k k k M M TPC. Harmonic Distortion vs. Frequency OUTPUT VOLTAGE V p-p R L = R L = INPUT VOLTAGE NOISE nv/ Hz k M M M TPC. Large Signal Frequency Response k k k TPC. Input Voltage Noise Spectral Density vs. Frequency M M OUTPUT SWING FROM TO V %.%.% %.%.% SLEW RATE V/ s SETTLING TIME ns TPC. Output Swing and Error vs. Settling Time TEMPERATURE C TPC. Slew Rate vs. Temperature

7 GAIN db pf V OUT.dB V S FLATNESS V MHz V MHz +V MHz V S = V V S = +V V S = V GAIN db pf V OUT.dB V S FLATNESS V MHz V MHz +V 9MHz V S = V V S = +V V S = V k M M M TPC 9. Closed-Loop Gain vs. Frequency k M M M TPC. Closed-Loop Gain vs. Frequency, G = DIFFERENTIAL PHASE Degrees DIFF GAIN.. DIFF PHASE.. SUPPLY VOLTAGE V TPC. Differential Gain and Phase vs. Supply Voltage... DIFFERENTIAL GAIN Percent GAIN db..... V S = V. V S = V.. V S = V.. k M M M TPC. Gain Flatness Matching vs. Supply, G = + V. F F V OUT CROSSTALK db R L = R L = / R L R L /. F F k k M M M V USE GROUND PLANE PINOUT SHOWN IS FOR MINI-DIP PACKAGE TPC. Crosstalk vs. Frequency TPC. Crosstalk Test Circuit

8 C F V ns +V S. F. F HP PULSE (LS) OR FUNCTION (SS) GENERATOR / V OUT. F TEKTRONIX P FET PROBE TEKTRONIX A PREAMP %. F R L V V S TPC. Inverting Amplifier Connection TPC. Inverter Large Signal Pulse Response V S, C F = pf, R L = kω V ns mv ns % % V mv TPC. Inverter Large Signal Pulse Response V S, C F = pf, R L = kω TPC 9. Inverter Small Signal Pulse Response V S, C F = pf, R L = Ω mv ns mv ns % % mv mv TPC. Inverter Small Signal Pulse Response V S, C F = pf, R L = Ω TPC. Inverter Small Signal Pulse Response V S, C F = pf, R L = Ω

9 +V S C F. F V ns. F HP PULSE (LS) OR FUNCTION (SS) GENERATOR R IN / V OUT. F TEKTRONIX P FET PROBE TEKTRONIX A PREAMP %. F R L V V S TPC. Noninverting Amplifier Connection TPC. Noninverting Large Signal Pulse Response V S, C F = pf, R L = kω V ns mv ns % % V mv TPC. Noninverting Large Signal Pulse Response V S, C F = pf, R L = kω TPC. Noninverting Small Signal Pulse Response V S, C F = pf, R L = Ω mv ns mv ns % % mv TPC. Noninverting Small Signal Pulse Response V S, C F = pf, R L = Ω mv TPC. Noninverting Small Signal Pulse Response V S, C F = pf, R L = Ω 9

10 THEORY OF OPERATION The is a low cost, dual video operational amplifier designed to excel in high performance, high output current video applications. The consists of a degenerated NPN differential pair driving matched PNPs in a folded-cascade gain stage (Figure ). The output buffer stage employs emitter followers in a class AB amplifier that delivers the necessary current to the load while maintaining low levels of distortion. The will drive terminated cables and capacitive loads of pf or less. As the closed-loop gain is increased, the will drive heavier cap loads without oscillating. IN +IN Figure. Simplified Schematic +V S OUTPUT INPUT CONSIDERATIONS An input protection resistor (R IN in TPC ) is required in circuits where the input to the will be subjected to transient or continuous overload voltages exceeding the ± V maximum differential limit. This resistor provides protection for the input transistors by limiting their maximum base current. For high performance circuits, the balancing resistor should be used to reduce the offset errors caused by bias current flowing through the input and feedback resistors. The balancing resistor equals the parallel combination of R IN and R F and thus provides a matched impedance at each input terminal. The offset voltage error will then be reduced by more than an order of magnitude. APPLYING THE The is a breakthrough dual amp that delivers precision and speed at low cost with low power consumption. The offers excellent static and dynamic matching characteristics, combined with the ability to drive heavy resistive loads. As with all high frequency circuits, care should be taken to maintain overall device performance as well as their matching. The following items are presented as general design considerations. V S Circuit Board Layout Input and output runs should be laid out so as to physically isolate them from remaining runs. In addition, the feedback resistor of each amplifier should be placed away from the feedback resistor of the other amplifier, since this greatly reduces interamp coupling. Choosing Feedback and Gain Resistors To prevent the stray capacitance present at each amplifier s summing junction from limiting its performance, the feedback resistors should be kω. Since the summing junction capacitance may cause peaking, a small capacitor ( pf to pf) may be paralleled with R F to neutralize this effect. Finally, sockets should be avoided, because of their tendency to increase interlead capacitance. Power Supply Bypassing Proper power supply decoupling is critical to preserve the integrity of high frequency signals. In carefully laid out designs, decoupling capacitors should be placed in close proximity to the supply pins, while their lead lengths should be kept to a minimum. These measures greatly reduce undesired inductive effects on the amplifier s response. Though two. µf capacitors will typically be effective in decoupling the supplies, several capacitors of different values can be paralleled to cover a wider frequency range. PARALLEL AMPS PROVIDE ma TO LOAD By taking advantage of the superior matching characteristics of the, enhanced performance can easily be achieved by employing the circuit in Figure. Here, two identical cells are paralleled to obtain even higher load driving capability than that of a single amplifier ( ma min guaranteed). R and R are included to limit current flow between amplifier outputs that would arise in the presence of any residual mismatch. +V S / / V S F. F. F F R R Figure. Parallel Amp Configuration V OUT R L

11 A IN R Z R Z / / B IN FT RG9A/U R Z = B OUT / / A OUT Figure. Bidirectional Transmission CKT Full-Duplex Transmission Superior load handling capability ( ma min/amp), high bandwidth, wide supply voltage range, and excellent crosstalk rejection makes the an ideal choice for even the most demanding high speed transmission applications. The schematic below shows a pair of s configured to drive feet of coaxial cable in a full-duplex fashion. Two different NTSC video signals are simultaneously applied at A IN and B IN and are recovered at A OUT and B OUT, respectively. This situation is illustrated in Figures and. These pictures clearly show that each input signal appears undisturbed at its output, while the unwanted signal is eliminated at either receiver. The transmitters operate as followers, while the receivers gain is chosen to take full advantage of the s unparalleled CMRR. In practice, this gain is adjusted slightly from its theoretical value to compensate for cable nonidealities and losses. R Z is chosen to match the characteristic impedance of the cable employed. Finally, although a coaxial cable was used, the same topology applies unmodified to a variety of cables (such as twisted pairs often used in telephony). mv mv A IN B IN B OUT A OUT % % mv µs mv µs Figure. A Transmission/B Reception Figure. B Transmission/A Reception A High Performance Video Line Driver The buffer circuit shown in Figure 9 will drive a back-terminated Ω video line to standard video levels ( V p-p) with. db gain flatness to MHz with only. and.% differential phase and gain at the. MHz NTSC subcarrier frequency. This level of performance, which meets the requirements for high definition video displays and test equipment, is achieved using only ma quiescent current/amplifier. R T +V / V. F. F. F. F R BT R T Figure 9. Video Line Driver

12 LOW DISTORTION LINE DRIVER The can quickly be turned into a powerful, low distortion line driver (see Figure ). In this arrangement, the can comfortably drive a Ω back-terminated cable with a MHz, V p-p input, while achieving the harmonic distortion performance outlined in the following table. Configuration nd Harmonic. No Load. dbm. Ω R L Only. dbm. Ω R L. Ω R C. dbm In this application, one half of the operates at a gain of +. and supplies the current to the load, while the other provides the overall system gain of +. This is important for two reasons: the first is to keep the bandwidth of both amplifiers the same, and the second is to preserve the s ability to operate from low supply voltage. R C varies with the load and must be chosen to satisfy the following equation: RC = MR L where M is defined by [(M + ) G S = G D ] and G D = Driver s Gain, G S = System Gain. +V S / V S V / IN. F. F F. F R C. Figure. Low Distortion Amplifier R L C9 /(C) OUTLINE DIMENSIONS -Lead Plastic Dual-in-Line Package [PDIP] (N-) Dimensions shown in inches and (millimeters) -Lead Standard Small Outline Package [SOIC] (R-) Dimensions shown in millimeters and (inches).99 (.9). (.). (.9). (.).99 (.). (.). (.).9 (.). (.). (.) PIN.9 (.) MAX.9 (.). (.9). (.). (.). (.) BSC.9 (.). (.).9 (.). (.).99 (.) MIN SEATING PLANE. (.). (.).99 (.9). (.9). (.).9 (.) PIN COPLANARITY. (.9). (.) SEATING PLANE. (.) BSC. (.). (.). (.). (.). (.9).9 (.). (.9). (.99). (.). (.) CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN COMPLIANT TO JEDEC STANDARDS MS- AA PRINTED IN U.S.A. Revision History Location Page / Data Sheet changed from REV. B to. Renumbered Figures and TPCs Global Changes to Figure