HA MHz, PRAM Four Channel Programmable Amplifiers. Features. Applications. Pinout. Ordering Information

Transcription

1 HA0 Data Sheet August 00 FN89. 0MHz, PRAM Four Channel Programmable Amplifiers The HA0 comprise a series of fourchannel programmable amplifiers providing a level of versatility unsurpassed by any other monolithic operational amplifier. Versatility is achieved by employing four input amplifier channels, any one (or none) of which may be electronically selected and connected to a single output stage through DTL/TTL compatible address inputs. The device formed by the output and the selected pair of inputs is an op amp which delivers excellent slew rate, gain bandwidth and power bandwidth performance. Other advantageous features for these dielectrically isolated amplifiers include high voltage gain and input impedance coupled with low input offset voltage and offset current. External compensation is not required on this device at closed loop gains greater than. Each channel of the HA0 can be controlled and operated with suitable feedback networks in any of the standard op amp configurations. This specialization makes these amplifiers excellent components for multiplexing signal selection and mathematical function designs. With 0V/µs slew rate, 0MHz gain bandwidth and 0MΩ input impedance these devices are ideal building blocks for signal generators, active filters and data acquisition designs. Programmability, coupled with mv typical offset voltage and na offset current, makes these amplifiers outstanding components for signal conditioning circuits. During Disable Mode V goes to V. For high output impedance during Disable, see HA. For further design ideas, see Application Note AN. Ordering Information PART NUMBER TEMP. RANGE ( o C) PACKAGE PKG. DWG. # HA0 to 8 6 Ld CERDIP F6. TRUTH TABLE Features Programmability High Rate Slew V/µs Wide Gain Bandwidth MHz High Gain kV/V Low Offset Current nA High Input Impedance MΩ Single Capacitor Compensation DTL/TTL Compatible Inputs Applications Thousands of Applications; Program Signal Selection/Multiplexing Operational Amplifier Gain Oscillator Frequency Filter Characteristics AddSubtract Functions Integrator Characteristics Comparator Levels Pinout IN IN IN IN IN IN IN IN HA0 (CERDIP) TOP VIEW DECODE CONTROL PUT AMP 6 9 D0 D ENABLE GND V V D D0 EN SELECTED CHANNEL D L L H L L H H L H L H H H H H H X X L None, V goes to V X CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 888INTERSIL or 77 Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 00. All Rights Reserved All other trademarks mentioned are the property of their respective owners.

2 HA0 Absolute Maximum Ratings (T A = C) Voltage Between V and V Terminals V Differential Input Voltage V SUPPLY Digital Input Voltage V to.0v Output Current Short Circuit Protected, I SC < ±ma) Internal Power Dissipation (Note ) Operating Conditions Temperature Range HA o C to 8 o C Thermal Information Thermal Resistance (Typical, Note ) θ JA ( o C/W) θ JC ( o C/W) CERDIP Package Maximum Junction Temperature (Ceramic Package) o C Maximum Junction Temperature (Plastic Package) o C Maximum Storage Temperature Range o C to 0 o C Maximum Lead Temperature (Soldering s) o C CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES:. Maximum power dissipation including output load, must be designed to maintain the junction temperature below 7 o C for the ceramic package, and below 0 o C for the plastic packages.. θ JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB79 for details. Electrical Specifications Test Conditions: V SUPPLY = ±V, Unless Otherwise Specified. Digital Inputs: V IL = 0.V, V IH =.. Limits apply to each of the four channels, when addressed PARAMETER TEST CONDITIONS TEMP. ( o C) HA0 MIN TYP MAX UNITS INPUT CHARACTERISTICS Offset Voltage 9 mv Full mv Bias Current (Note 8) 0 00 na Full 00 na Offset Current (Note 8) 0 na Full 0 na Input Resistance (Note 8) 0 MΩ Common Mode Range Full ±9.0 V TRANSFER CHARACTERISTICS Large Signal Voltage Gain R L = kω 0 0 kv/v V = 0V PP Full kv/v Common Mode Rejection Ratio V CM = ±V Full 80 0 db Gain Bandwidth (Notes, 9) 0 0 MHz Gain Bandwidth (Notes, 9) 8 MHz Minimum Stable Gain (C = 0) V/V PUT CHARACTERISTICS Output Voltage Swing R L = kω Full ±.0 ±.0 V Output Current 0 ma Full Power Bandwidth (Notes, ) V = 0V PP khz Full Power Bandwidth (Notes, ) V = 0V PP 00 0 khz TRANSIENT RESPONSE (Note ) Rise Time (Note ) V = 00mV PEAK 0 ns Overshoot (Note ) V = 00mV PEAK 0 % Slew Rate (Note ) V = V PP 0 0 V/µs Slew Rate (Notes, 9) V = V PP 6 8 V/µs

3 HA0 Electrical Specifications Test Conditions: V SUPPLY = ±V, Unless Otherwise Specified. Digital Inputs: V IL = 0.V, V IH =.. Limits apply to each of the four channels, when addressed (Continued) PARAMETER TEST CONDITIONS TEMP. ( o C) HA0 MIN TYP MAX UNITS Settling Time (Notes,, 9) V = V PP.. µs CHANNEL SELECT CHARACTERISTICS Digital Input Current V IN = 0V Full. ma Digital Input Current V IN =.0V Full na Output Delay (Notes 6, 9) 0 0 ns Crosstalk (Note 7) 80 db POWER SUPPLY CHARACTERISTICS Supply Current ma Power Supply Rejection Ratio V S = ±V to ±0V Full 7 90 db NOTES:. A V =, C = 0, R L = kω, C L = 0pF.. A V =, C = pf, R L = kω, C L = 0pF.. To 0.% of final value. 6. To % of final value; output then slews at normal rate to final value. 7. Unselected input to output; V IN = ±V DC. 8. Unselected channels have approximately the same input parameters. 9. Guaranteed by design. SR. Full Power Bandwidth based on slew rate measurement using: FPBW = ; V. πv PEAK = V PEAK. See Figure for test circuit.

4 HA0 Schematic Diagram HA0 IN IN V CC R.8K R.9K ENABLE Q GND Q Q Q 6 Q 7 Q 8 R.K Q Q 9 Q R.6K R 8.0K R 6 Q Q 0 R.0K 8 Q 9.6K R 7.6K Q VD Q VE R.6K Q 8 Q7 R K Q 9 R 0.8K Q 6 Q 0 Q Q Q Q Q Q Q Q 8 R 8.0K Q Q Q Q Q Q 6 Q 7 Q 9 Q 0 Q Q 8 Q Q 8 79 Q 8 Q 80 R 0.7K Q 88 Q8 Q 89 Q 86 R 0.K Q 87 C 9.0pF V R.6K Q 8 Q 98 Q 9 Q 9 Q 99 R K Q 97 Q 0 Q 9 Q 9 Q R R 6. Q 96 Q Q VC Q 90 Q 9 Q VB Q7 VA TO ADDITIONAL INPUT STAGES Q R 8 K Q 6 R 9.K R K R K R K R 6 K D0 R 7.6K D Q R9.6K R 9 0.K V EE Diagram Includes: One Input Stage, Decode Control, Bias Network, and Output Stage

5 HA0 Typical Applications IN DECODE/ CONTROL D0 6 D ENABLE GND V PUT AMP V 9 V DIGITAL CONTROL DIGITAL GROUND pf V IN DECODE/ CONTROL D0 6 D ENABLE GND V PUT AMP V 9 S V DIGITAL GROUND C V H K Sample Charging Rate I = V s C K I Hold Drift Rate = V s C Q Switch Pedestal Error = V C I 0 x 6 A I 00 x 9 A at o C 600 x 9 A at o C 0 x 9 A at o C Q x C FIGURE. HA0 AMPLIFIER, NONINVERTING PROGRAMMABLE GAIN For more examples, see Intersil Application Note AN. FIGURE. HA0 SAMPLE AND HOLD Typical Performance Curves CURRENT (na) BIAS CURRENT 0 OFFSET CURRENT TEMPERATURE ( o C) NORMALIZED VALUE REFERRED TO o C. BANDWIDTH SLEW RATE TEMPERATURE ( o C) FIGURE. INPUT BIAS CURRENT AND OFFSET CURRENT vs TEMPERATURE FIGURE. NORMALIZED AC PARAMETERS vs TEMPERATURE

6 HA0 Typical Performance Curves (Continued) SUPPLY CURRENT (ma) V SUPPLY = ±0V V SUPPLY = ±V V SUPPLY = ±V TEMPERATURE ( o C) FIGURE. POWER SUPPLY CURRENT vs TEMPERATURE OPEN LOOP VOLTAGE GAIN (db) 0 CROSSTALK REJECTION, A V = PHASE C = 0pF C = pf GAIN 0 0 K K 0K M M 0M FREQUENCY (Hz) FIGURE 6. OPEN LOOP FREQUENCY AND PHASE RESPONSE PHASE (DEGREES) OPEN LOOP VOLTAGE GAIN (db) pF 00pF 00pF 0pF pf 0pF 0 0 K K 0K M M 0M FREQUENCY (Hz) FIGURE 7. FREQUENCY RESPONSE vs C NORMALIZED VALUE REFERRED TO ±V SLEW RATE SUPPLY VOLTAGE (V) BANDWIDTH 0.8 ± ± ±0 FIGURE 8. NORMALIZED AC PARAMETERS vs SUPPLY VOLTAGE GAIN (db) 0 9 V SUPPLY = ±0V V SUPPLY = ±V V SUPPLY = ±V PUT SWING (V PP ) 0.0 C = 0pF C = pf TEMPERATURE ( o C) 0. K 0K M M FREQUENCY (Hz) FIGURE 9. OPEN LOOP VOLTAGE GAIN vs TEMPERATURE FIGURE. PUT VOLTAGE SWING vs FREQUENCY 6

7 HA0 Typical Performance Curves (Continued) 0 00 INPUT NOISE (µv).0 K SOURCE RESISTANCE 0 SOURCE RESISTANCE THERMAL NOISE OF K RESISTOR 0. 0Hz khz khz 0kHz MHz UPPER db FREQUENCY (LOWER db FREQUENCYHz) BROADBAND NOISE CHARACTERISTICS INPUT NOISE VOLTAGE (nv/ Hz) 0 INPUT NOISE VOLTAGE INPUT NOISE CURRENT K K 0K FREQUENCY (Hz) 0. INPUT NOISE CURRENT (pa/ Hz) FIGURE. EQUIVALENT INPUT NOISE vs BANDWIDTH FIGURE. INPUT NOISE vs FREQUENCY IN A V = SELECTED CHANNEL pf.0v Ω A V =.0V Ω 800Ω 00Ω 0pF FIGURE. SLEW RATE AND TRANSIENT RESPONSE 7

8 HA0 Ceramic DualInLine Frit Seal Packages (CERDIP) BASE PLANE SEATING PLANE S b ccc M bbb S b C A B C A B S D A A e D S NOTES:. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer s identification shall not be used as a pin one identification mark.. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied.. Dimensions b and c apply to lead base metal only. Dimension M applies to lead plating and finish thickness.. Corner leads (, N, N/, and N/) may be configured with a partial lead paddle. For this configuration dimension b replaces dimension b.. This dimension allows for offcenter lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y.M 98.. Controlling dimension: INCH. E L M c ea/ S D S aaa M C A B LEAD FINISH BASE METAL b M (b) SECTION AA D A Q C A Bα S ea c D S (c) F6. MILSTD8 GDIPT6 (D, CONFIGURATION A) 6 LEAD CERAMIC DUALINLINE FRIT SEAL PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A b b b b c c D E e 0.0 BSC. BSC ea 0.00 BSC 7.6 BSC ea/ 0.0 BSC.8 BSC L Q S α 90 o o 90 o o aaa bbb ccc M , N Rev. 0 /9 All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation s quality certifications can be viewed at Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see 8