DATASHEET HA Features. Applications. Ordering Information. Pinouts. 250MHz Video Buffer. FN2924 Rev 8.00 Page 1 of 12.

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1 25MHz Video Buffer NOT RECOMMENDED FOR NEW DESIGNS NO RECOMMENDED REPLACEMENT contact our Technical Support Center at -888-INTERSIL or DATASHEET FN2924 Rev 8. The HA-533 is a unity gain monolithic IC designed for any application requiring a fast, wideband buffer. Featuring a bandwidth of 25MHz and outstanding differential phase/ gain characteristics, this high performance voltage follower is an excellent choice for video circuit design. Other features, which include a minimum slew rate of / s and high output drive capability, make the HA-533 applicable for line driver and high speed data conversion circuits. The high performance of this product is a result of the Intersil Dielectric Isolation process. A major feature of this process is that it produces both PNP and NPN high frequency transistors which makes wide bandwidth designs, such as the HA-533, practical. Alternative process methods typically produce a lower AC performance. Ordering Information PART NUMBER Pinouts PART MARKING TEMP. RANGE ( C) HA-533 (PDIP) TOP VIEW PACKAGE PKG. DWG. # HA HA to 25 2 Pin Metal Can T2.C HA HA to 75 8 Ld PDIP E8.3 V+ 8 OUT Features Differential Phase Error Degrees Differential Gain Error % High Slew Rate / s Wide Bandwidth (Small Signal) MHz Wide Power Bandwidth DC to 7.5MHz Fast Rise Time ns High Output Drive With Load Wide Power Supply Range V to 6V Replace Costly Hybrids Applications Video Buffer High Frequency Buffer Isolation Buffer High Speed Line Driver Impedance Matching Current Boosters High Speed A/D Input Buffers Related Literature - AN548, Designer s Guide for HA SUB- STRATE IN 4 5 V- HA-533 (METAL CAN) TOP VIEW V+ CASE 2 2 OUT V IN FN2924 Rev 8. Page of 2

2 Absolute Maximum Ratings Voltage Between V+ and V- Pins DC Input Voltage V+ to V- Output Current (Peak) (5ms On/ Second Off) mA ESD Rating Human Body Model (Per MIL-STD-883 Method 35.7) Operating Conditions Temperature Ranges (Note 3) HA C to 25 C HA C to 75 C Thermal Information Thermal Resistance (Typical, Note 2) JA ( C/W) JC ( C/W) Metal Can Package PDIP Package N/A Maximum Junction Temperature (Note ) C Maximum Junction Temperature (Plastic Packages) C Maximum Storage Temperature Range C to 5 C Maximum Lead Temperature (Soldering s) C CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES:. Maximum power dissipation, including load conditions, must be designed to maintain the maximum junction temperature below 75 C for the metal can package, and below 5 C for the plastic packages (See Figure 5.). 2. JA is measured with the component mounted on an evaluation PC board in free air. 3. The maximum operating temperature may have to be derated depending on the output load condition. See Figure 5 for more information. Electrical Specifications V SUPPLY = 2V, R S = 5, R L = C L = pf, Unless Otherwise Specified PARAMETER TEST CONDITIONS TEMP. ( C) HA HA MIN TYP MAX MIN TYP MAX UNITS INPUT CHARACTERISTICS Offset Voltage mv Full mv Average Offset Voltage Drift Full V/ C Bias Current A Full A Input Resistance M Input Capacitance pf Input Noise Voltage Hz to MHz V P-P TRANSFER CHARACTERISTICS Voltage Gain R L = V/V R L = k V/V R L = Full V/V -3dB Bandwidth MHz OUTPUT CHARACTERISTICS Output Voltage Swing R L = Full V R L = k, V S = 5V Full V Output Current ma Output Resistance Full Power Bandwidth V OUT = V RMS, R L = k MHz Full Power Bandwidth (Note 4) MHz TRANSIENT RESPONSE Rise Time V OUT = 5mV ns Propagation Delay ns FN2924 Rev 8. Page 2 of 2

3 Electrical Specifications V SUPPLY = 2V, R S = 5, R L = C L = pf, Unless Otherwise Specified (Continued) PARAMETER TEST CONDITIONS TEMP. ( C) HA HA MIN TYP MAX MIN TYP MAX UNITS Overshoot % Slew Rate (Note 4) V/ns Settling Time to.% ns Differential Phase Error (Note 5) Degree Differential Gain Error (Note 5) % POWER SUPPLY CHARACTERISTICS Supply Current ma Full ma Power Supply Rejection Ratio Full db Harmonic Distortion = V RMS at khz 25 - <. - - <. - % NOTES: 4. V SUPPLY = 5V, V OUT =, R L = k. 5. Differential gain and phase error are nonlinear signal distortions found in video systems and are defined as follows: Differential gain error is defined as the change in amplitude at the color subcarrier frequency as the picture signal is varied from blanking to white level. Differential phase error is defined as the change in the phase of the color subcarrier as the picture signal is varied from blanking to white level. R L = 3. Test Circuits and Waveforms +5V. F +2V. F IN OUT IN OUT R L. F. F -5V -2V FIGURE. SLEW RATE AND SETTLING TIME FIGURE 2. TRANSIENT RESPONSE 5mV INPUT 9% OUTPUT V % ERROR BAND SLEW mv FROM t RATE = FINAL VALUE V/ t SETTLING TIME INPUT 9% OUTPUT % OVERSHOOT NOTE: Measured on both positive and negative transitions. FIGURE 3. SETTLING TIME AND SLEW RATE FIGURE 4. RISE TIME AND OVERSHOOT FN2924 Rev 8. Page 3 of 2

4 Test Circuits and Waveforms (Continued) V OUT V OUT T A = 25 C, R S = 5 R L = T A = 25 C, R S = 5 R L = k + RESPONSE + RESPONSE 5mV 5mV V OUT T A = 25 C, R S = 5, R L = PULSE RESPONSE Schematic Diagram V+ R 5 R 4 R 2 R 2 Q 5 Q Q 6 Q Q 6 Q 2 Q R 9 Q 9 Q 7 R R 6 Q 3 R 8 Q 4 Q 8 V OUT R Q 7 Q 3 Q 5 Q 9 Q 2 Q 8 Q 4 R R 3 V- R 3 FN2924 Rev 8. Page 4 of 2

5 Application Information Layout Considerations The wide bandwidth of the HA-533 necessitates that high frequency circuit layout procedures be followed. Failure to follow these guidelines can result in marginal performance. Probably the most crucial of the RF/video layout rules is the use of a ground plane. A ground plane provides isolation and minimizes distributed circuit capacitance and inductance which will degrade high frequency performance. IC sockets contribute inter-lead capacitance which limits device bandwidth and should be avoided. Pin 6 can be tied to either supply, grounded, or simply not used. But to optimize device performance and improve isolation, it is recommended that this pin be grounded. Other considerations are proper power supply bypassing and keeping the input and output connections as short as possible which minimizes distributed capacitance and reduces board space. Power Supply Decoupling For optimum device performance, it is recommended that the positive and negative power supplies be bypassed with capacitors to ground. Ceramic capacitors ranging in value from. F to. F will minimize high frequency variations in supply voltage. Solid tantalum capacitors F or larger will optimize low frequency performance. It is also recommended that the bypass capacitors be connected close to the HA-533 (preferably directly to the supply pins). Figure 5 is based on: T JMAX T A P DMAX = JA Where: T JMAX = Maximum Junction Temperature of the Device T A = Ambient Temperature MAXIMUM TOTAL POWER DISSIPATION (W) JA = Junction to Ambient Thermal Resistance PDIP CAN QUIESCENT P D =.72W AT V S = 2V, I CC = 3mA TEMPERATURE ( C) FIGURE 5. MAXIMUM POWER DISSIPATION vs TEMPERATURE Typical Applications (Also see Application Note AN548) R S +2V. F 2 5. F -2V R M 5 RG R L VIDEO SIGNAL INPUT V+ HA-2539 R R 2 5 V- 9 V+ VIDEO HA-533 OUTPUT 75 V- 75 FIGURE 6. VIDEO COAXIAL LINE DRIVER 5 SYSTEM FIGURE 7. VIDEO GAIN BLOCK FN2924 Rev 8. Page 5 of 2

6 Typical Applications (Also see Application Note AN548) (Continued) V OUT V OUT T A = 25 C, R S = 5, R M = R L = 5 T A = 25 C, R S = 5, R M = R L = 5 R L V O = = R L + R M -- V 2 IN R L V O = = R L + R M -- V 2 IN POSITIVE PULSE RESPONSE NEGATIVE PULSE RESPONSE Typical Performance Curves 4 OFFSET VOLTAGE (mv) V S = 2V V S = 5V V S = INPUT BIAS CURRENT ( A) 3 2 V S = 2V V S = V S = 5V V S = 5V V S = 5V TEMPERATURE ( C) FIGURE 8. INPUT OFFSET VOLTAGE vs TEMPERATURE TEMPERATURE ( C) FIGURE 9. INPUT BIAS CURRENT vs TEMPERATURE 3 V S = 5V 3 V S = 5V, = SUPPLY CURRENT (ma) 2 V S = 2V V S = V S = 5V SLEW RATE (V/ s) 2 FALL (R L = k ) FALL (R L = ) RISE (R L = k ) RISE (R L = ) TEMPERATURE ( C) FIGURE. SUPPLY CURRENT vs TEMPERATURE TEMPERATURE ( C) FIGURE. SLEW RATE vs TEMPERATURE FN2924 Rev 8. Page 6 of 2

7 Typical Performance Curves (Continued) SLEW RATE (V/ s) V S = 5V, R L = k T A = 25 C, = RISE FALL SLEW RATE (V/ s) RISE FALL V S = 5V, R L = T A = 25 C, = CAPACITAE (pf) 5, CAPACITAE (pf) 5, FIGURE 2. SLEW RATE vs LOAD CAPACITAE FIGURE 3. SLEW RATE vs LOAD CAPACITAE 8 6 V S = 5V, T A = 25 C R L = k 9 7 V S = 5V, T A = 25 C R L = 5 OUTPUT INPUT V OS (mv) R L = k R L = k OUTPUT INPUT V OS (mv) R L = R L = R L = k INPUT VOLTAGE (V) R L = INPUT VOLTAGE (V) FIGURE 4. GAIN ERROR vs INPUT VOLTAGE FIGURE 5. GAIN ERROR vs INPUT VOLTAGE 6 4 V S = 5V, V O = 8 V S = 5, T A = 25 C OUTPUT INPUT V OS (mv) R L = k - V OUT (mv) V OUT = SINKING CURRENT V OUT = - V OUT = + V OUT = SOURCING CURRENT TEMPERATURE ( C) FIGURE 6. GAIN ERROR vs TEMPERATURE I OUT (ma) FIGURE 7. - V OUT vs I OUT FN2924 Rev 8. Page 7 of 2

8 Typical Performance Curves (Continued) PHASE ANGLE (DEGREES) Y 22 Y 2 Y Y 2 MAGNITUDE (S) Y Y 2 Y 2, Y 22 Y Y 2 Y 22 Y FREQUEY (Hz) FREQUEY (Hz) 9 FIGURE 8. Y - PARAMETERS PHASE vs FREQUEY FIGURE 9. Y - PARAMETER MAGNITUDE vs FREQUEY POWER SUPPLY REJECTION RATIO (db) V S = 2V, T A = 25 C TOTAL HARMONIC DISTORTION (%) V S = 2V, R L = = V RMS K K K M M FREQUEY (Hz) K K FREQUEY (Hz) K FIGURE 2. POWER SUPPLY REJECTION RATIO vs FREQUEY FIGURE 2. TOTAL HARMONIC DISTORTION vs FREQUEY TOTAL HARMONIC DISTORTION (%)... V S = 2V R L = V = 2V, R L = f = khz PEAK TO PEAK OUTPUT VOLTAGE (V) T A = 25 C V S = 5V V S = 5V V S = 2V V S = 2 3 INPUT VOLTAGE (RMS) FIGURE 22. TOTAL HARMONIC DISTORTION vs INPUT VOLTAGE K LOAD RESISTAE ( ) FIGURE 23. OUTPUT VOLTAGE SWING vs LOAD RESISTAE FN2924 Rev 8. Page 8 of 2

9 Typical Performance Curves (Continued) OUTPUT VOLTAGE (V RMS ) V S = 5V, R L = NO HEAT SINK IN 3. FREE AIR K K M M M G FREQUEY (Hz) OUTPUT VOLTAGE (V RMS ) V S = 5V, R L = k NO HEAT SINK 4. IN FREE AIR K K M M M G FREQUEY (Hz) FIGURE 24. OUTPUT SWING vs FREQUEY (NOTE) FIGURE 25. OUTPUT SWING vs FREQUEY (NOTE) NOTE: This curve was obtained by noting the output voltage necessary to produce an observable distortion for a given frequency. If higher distortion is acceptable, then a higher output voltage for a given frequency can be obtained. However, operating the HA-533 with increased distortion (to the right of curve shown), will also be accompanied by an increase in supply current. The resulting increase in chip temperature must be considered and heat sinking will be necessary to prevent thermal runaway. This characteristic is the result of the output transistor operation. If the signal amplitude or signal frequency or both are increased beyond the curve shown, the NPN, PNP output transistors will approach a condition of being simultaneously on. Under this condition, thermal runaway can occur. FN2924 Rev 8. Page 9 of 2

10 Die Characteristics SUBSTRATE POTENTIAL (POWERED UP): Unbiased TRANSISTOR COUNT: 2 PROCESS: Bipolar Dielectric Isolation Metallization Mask Layout HA-533 IN V+ OUT V- FN2924 Rev 8. Page of 2

11 Metal Can Packages (Can) ØD ØD A F L Øb REFEREE PLANE A A BASE METAL NOTES:. The reference, base, and seating planes are the same for this variation. 2. Measured from maximum diameter of the product. 3. N is the maximum number of terminal positions. 4. Dimensioning and tolerancing per ANSI Y4.5M Controlling dimension: IH. e SECTION A-A LEAD FINISH Øb2 2 N k e k T2.C 2 LEAD METAL CAN PACKAGE IHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A Øb Øb ØD ØD e.4 BSC.6 BSC - e. BSC 2.54 BSC - F k k L N Rev. 5/8/94 FN2924 Rev 8. Page of 2

12 Dual-In-Line Plastic Packages (PDIP) INDEX AREA BASE PLANE SEATING PLANE D B -C- -A- N 2 3 N/2 B D e D E -B- A. (.25) M C A A2 L B S NOTES:. Controlling Dimensions: IH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y4.5M Symbols are defined in the MO Series Symbol List in Section 2.2 of Publication No Dimensions A, A and L are measured with the package seated in JEDEC seating plane gauge GS D, D, and E dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed. inch (.25mm). 6. E and e A are measured with the leads constrained to be perpendicular to datum -C-. 7. e B and e C are measured at the lead tips with the leads unconstrained. e C must be zero or greater. 8. B maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed. inch (.25mm). 9. N is the maximum number of terminal positions.. Corner leads (, N, N/2 and N/2 + ) for E8.3, E6.3, E8.3, E28.3, E42.6 will have a B dimension of inch ( mm). A e C E C L e A C e B E8.3 (JEDEC MS--BA ISSUE D) 8 LEAD DUAL-IN-LINE PLASTIC PACKAGE IHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A A B B , C D D E E e. BSC 2.54 BSC - e A.3 BSC 7.62 BSC 6 e B L N Rev. 2/93 Copyright Intersil Americas LLC All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see Intersil products are manufactured, assembled and tested utilizing ISO9 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see FN2924 Rev 8. Page 2 of 2