DATASHEET. Features. Applications HS-2420EH. Radiation Hardened Fast Sample and Hold. FN8727 Rev 0.00 Page 1 of 11. March 17, FN8727 Rev 0.

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1 DATASHEET HS40EH Radiation Hardened Fast Sample and Hold The HS40EH is a radiation hardened monolithic circuit consisting of a high performance operational amplifier with its output in series with an ultralow leakage analog switch and a MOSFET input unity gain amplifier. With an external hold capacitor connected to the switch output, a versatile high performance sampleandhold or trackandhold circuit is formed. When the switch is closed, the device behaves as an operational amplifier and any of the standard op amp feedback networks may be connected around the device to control gain, frequency response, etc. When the switch is opened, the output will remain at its last level. Performance as a sampleandhold compares very favorably with other monolithic, hybrid, modular and discrete circuits. Accuracy to better than 0.0% is achievable over the temperature range. Fast acquisition is coupled with superior droop characteristics, even at high temperatures. High slew rate, wide bandwidth and low acquisition time produce excellent dynamic characteristics. The ability to operate at gains greater than frequently eliminates the need for external scaling amplifiers. The device may also be used as a versatile operational amplifier with a gated output for applications such as analog switches, peak holding circuits, etc. Specifications for Rad Hard QML devices are controlled by the Defense Logistics Agency Land and Maritime (DLA). The SMD numbers listed here must be used when ordering. Detailed Electrical Specifications for these devices are contained in SMD Features Electrically screened to SMD # FN877 Rev 0.00 QML qualified per MILPRF38535 requirements Maximum acquisition time Step to 0.% µs Step to 0.0% µs Maximum drift current nA (maximum overtemperature) TTL compatible control input Power supply rejection dB Radiation tolerance High dose rate (50 to 300rad(Si)/s) krad(Si) Low dose rate (0.0rad(Si)/s) krad(Si)* * Only the EH device is waferbywafer acceptance tested at the low dose rate and guaranteed to 50krad(Si). The 00krad(Si) limit is established by characterization only. No latchup Applications Data acquisition systems D to A deglitcher Auto zero systems Peak detector Gated op amp OFFSET ADJUST V OUTPUT SAMPLE/ HOLD 4 HS40EH 3 5 V HOLD CAPACITOR FIGURE. FUTIONAL DIAGRAM FN877 Rev 0.00 Page of

2 HS40EH 4 LD METALSEALED SIDEBRAZED CERAMIC DIP MILSTD835, CDIPT4 TOP VIEW IN 4 SAMPLE/HOLD IN+ 3 OFFSET ADJUST 3 OFFSET ADJUST 4 HOLD CAPACITOR V V+ OUTPUT 7 8 Pin Descriptions PIN # PIN NAME DESCRIPTION IN Inverting input to the operational amplifier IN+ Noninverting input to the operational amplifier 3, 4 OFFSET ADJUST Connect a 00kΩ potentiometer across these pins to null out the offset voltage. 5 V Negative power supply 6, 8, 0, No connect pin. 7 OUTPUT Output of the unity gain amplifier 9 V+ Positive Power Supply HOLD CAPACITOR Connect the hold capacitor between this pin and. 3 Ground connection of the device 4 SAMPLE/HOLD Control input to the series analog switch. Ordering Information ORDERING SMD NUMBER (Note ) PART NUMBER (Note ) TEMPERATURE RANGE ( C) PACKAGE (RoHS Compliant) PKG. DWG. # 596R95669CC HSB40EHQ 55 to +5 4 Ld SBDIP D4.3 HSB40EH/PROTO HSB40EH/PROTO 55 to +5 4 Ld SBDIP D4.3 NOTES:. These Intersil Pbfree Hermetic packaged products employ 00% Au plate e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pbfree soldering operations.. Specifications for Rad Hard QML devices are controlled by the Defense Logistics Agency Land and Maritime (DLA). The SMD numbers listed in the Ordering Information table must be used when ordering. FN877 Rev 0.00 Page of

3 Test Circuits V DC ALL RESISTORS = % ALL CAPACITORS = 0% 00kΩ 0kΩ +V CC V CC 50Ω 50Ω S S S 6 S7 S 7 CH = 000pF + DUT A S 3 50pF 3 +V CC MΩ OPEN 3 S 5 kω S 4 00kΩ + NULL AMP X X BUFFER V AC 50Ω + I LOAD AOUT 4 3 EOUT S 8 FIGURE. TEST FIXTURE SCHEMATIC (SWITCH POSITIONS S S 8 DETERMINE CONFIGURATION) +5V SINEWAVE IN IN IN3 IN4 IN5 IN6 IN7 IN8 A A EN A0 OUT +5V 5V + DUT kω V IN CH = 000pF V OUT 50pF 50Ω +5V 5V DUT + kω CH = 000pF V OUT 50pF SAMPLE/HOLD NOTE: Compute Hold mode feedthrough attenuation from the formula: FeedthroughAttenuation 0 log V OUT HOLD = V IN HOLD Where V OUT HOLD = peaktopeak value of output Sinewave during the Hold mode. FIGURE 3. HOLD MODE FEEDTHROUGH ATTENUATION NOTE: GBWP is the frequency of V at which: V OUT 0 log = 3dB V FIGURE 4. GAIN BANDWIDTH PRODUCT FN877 Rev 0.00 Page 3 of

4 Test Circuits (Continued) SEND SAMPLE COMMAND SET t TO 7µs INITIALLY COURSE t ACQ MEASUREMENT LOOP FINE t ACQ MEASUREMENT LOOP DIGITIZE V AT t ( 0µs) IREMENT t BY 50ns (50ns LONGER DELAY) DIGITIZE V AT t DECREMENT t BY 50ns CALCULATE V V IS V 0.0%? YES DIGITIZE V AT t ( 0µs) DIGITIZE V AT t NO DECREMENT t BY 50ns RECORD t ACQ YES CALCULATE V V IS V 0.0%? NO NOTE: See Test Diagram, Timing Diagram FIGURE 5. ACQUISITION TIME (t ACQ TO 0.0% IS SHOWN, t ACQ TO 0.% IS DONE IN THE SAME MANNER) t HS40EH V DIGITIZER V pF kω V DIGITIZER V COMPUTER LER 000pF OR t 0µs DELAY t VARIABLE DELAY t DELAY FIGURE 6. BLOCK DIAGRAM FOR ACQUISITION TIME MEASUREMENT FN877 Rev 0.00 Page 4 of

5 Timing Waveforms V IN (POS t ACQ CASE) V 0.0% OR 0.% ENVELOPE DUT OUTPUT (POS t ACQ CASE) (t DIGITIZER COMMAND) t 0µs t (t DIGITIZER COMMAND) t t FIGURE 7. TIMING DIAGRAM FOR ACQUISITION TIME, (POSITIVE t ACQ CASE) +V V PEAK V FINAL 90% 0% V +OS, t R OS, t F 0% 90% t R t F V FINAL V PEAK FIGURE 8A. FIGURE 8B. FIGURE 8. OVERSHOOT, RISE AND FALL TIME WAVEFORMS +V +V +V +V 75% 5% 5% 75% V +SL SL V V V t t FIGURE 9A. FIGURE 9B. FIGURE 9. SLEW RATE WAVEFORMS FN877 Rev 0.00 Page 5 of

6 Typical Performance Curves V SUPPLY = 5V DC, T A = +5 C, CH = 000pF, Unless Otherwise Specified DRIFT DURING HOLD AT +5 C mv/s MIN SAMPLE TIME FOR 0.% ACCURACY SWINGS (ms) UNITY GAIN PHASE MARGIN ( ) UNITY GAIN BANDWIDTH (MHz) SLEW RATE/ CHARGE RATE V/(ms) 0.0 0pF 00pF 000pF 0.0µF 0.µF.0µF CH VALUE HOLD STEP OFFSET ERROR (mv) mv RMS LOWER 3dB FREQUEY = 0Hz EQUIV. NOISE SAMPLE MODE 00K SOURCE RESISTAE OUTPUT NOISE HOLD MODE EQUIV. NOISE SAMPLE MODE 0K SOURCE RESISTAE 0 00 k 0k 00k M BANDWIDTH FIGURE 0. TYPICAL SAMPLE AND HOLD PERFORMAE vs HOLDING CAPACITOR FIGURE. BROADBAND NOISE CHARACTERISTICS ID (pa) TEMPERATURE ( C) FIGURE. DRIFT CURRENT vs TEMPERATURE OPEN LOOP VOLTAGE GAIN (db) 00 CH = 0.0µF 80 CH = 00pF CH = 000pF CH =.0µF CH = 0.µF k 0k 00k M 0M 00M FREQUEY (Hz) FIGURE 3. OPEN LOOP FREQUEY RESPONSE ATTENUATION (db) k 0k 00k M 0M ± SINUSOIDAL FREQUEY (Hz) OPEN LOOP PHASE ANGLE ( ) CH = 0.0µF CH = 000pF CH 00pF CH =.0µF CH = 0.µF 0 00 k 0k 00k M 0M 00M FREQUEY (Hz) FIGURE 4. HOLD MODE FEEDTHROUGH ATTENUATION CH = 000pF FIGURE 5. OPEN LOOP PHASE RESPONSE FN877 Rev 0.00 Page 6 of

7 Burnin Circuit HS40EH CERDIP Irradiation Circuit IN +IN CTL 4 3 R 4 3 5V R C D OFFSET ADJ OFFSET HOLD ADJ CAP V 0 +V 9 +5V V V 7 OUT 8 D C 7 8 NOTES: R = 00kΩ ±5% (per socket) C = C = 0.µF (one per row) or 0.0µF (one per socket) D = D = N400 or equivalent (per board) NOTES: V = +5V V = 5V R = 00kΩ HOLD STEP VOLTAGE (V) CH V DC VOLTAGE (V) CH = 0.µF CH = 0,000pF CH = 000pF + + HS40EH 5 IN +IN V OUT CH = 00pF 00kΩ OFFSET TRIM (±5mV RANGE) FIGURE 6. HOLD STEP vs VOLTAGE FIGURE 7. BASIC SAMPLEANDHOLD with OFFSET TRIM 0.00RF R F RI OUTPUT +IN IN HS40EH OUT OUTPUT IN +IN HS40EH OUT R I R F GAIN ~ R F R I 0.00RI GAIN ~ I + R F R I FIGURE 8. INVERTING CONFIGURATION with GAIN ADJUST FIGURE 9. NONINVERTING CONFIGURATION WITH GAIN ADJUST FN877 Rev 0.00 Page 7 of

8 Offset and Gain Adjustment Offset Adjustment The offset voltage of the HS40EH may be adjusted using a 00kΩ trim pot, as shown in Figure 7. The recommended adjustment procedure is:. Apply to the sampleandhold input, and a square wave to the control.. Adjust the trim pot for output in the hold mode. Gain Adjustment The linear variation in pedestal voltage with sampleandhold input voltage causes a 0.06% gain error (CH = 000pF). In some applications (D/A deglitcher, A/D converter) the gain error can be adjusted elsewhere in the system, while in other applications it must be adjusted at the sampleandhold. Figures 8 and 9 illustrate how to implement gain error adjust on the sampleandhold. The recommended procedure for adjusting gain error is:. Perform offset adjustment.. Apply the nominal input voltage that should produce a + output. 3. Adjust the trim pot for + output in the hold mode. 4. Apply the nominal input voltage that should produce a output. Measure the output hold voltage (V0 NOMINAL). Adjust the trim pot for an output hold voltage of: V0 NOMINAL + FN877 Rev 0.00 Page 8 of

9 Die Characteristics DIE DIMENSIONS: 97mils x 6mils x 9mils METALLIZATION: Type: Al Thickness: 6kÅ kå GLASSIVATION: Type: Silox Thickness: 4kÅ kå Metallization Mask Layout HS40EH WORST CASE CURRENT DENSITY:.0 x 0 5 A/cm TRANSISTOR COUNT: 78 PROCESS: BipolarDi FN877 Rev 0.00 Page 9 of

10 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION CHANGE FN877.0 Initial Release About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and highend consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at You may report errors or suggestions for improving this datasheet by visiting Reliability reports are also available from our website at Copyright Intersil Americas LLC 05. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see Intersil products are manufactured, assembled and tested utilizing ISO900 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see FN877 Rev 0.00 Page 0 of

11 Ceramic DualInLine Metal Seal Packages (SBDIP) BASE PLANE SEATING PLANE S b ccc M bbb S b C A B S C A B D A A e D S S D S NOTES:. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer s identification shall not be used as a pin one identification mark.. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b and c apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (, N, N/, and N/+) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b. 5. Dimension Q shall be measured from the seating plane to the base plane. 6. Measure dimension S at all four corners. 7. Measure dimension S from the top of the ceramic body to the nearest metallization or lead. 8. N is the maximum number of terminal positions. 9. Braze fillets shall be concave. 0. Dimensioning and tolerancing per ANSI Y4.5M 98.. Controlling dimension: IH. E M c L ea/ LEAD FINISH BASE METAL b M (b) SECTION AA D A S Q C A ea Baaa M C A B S D S c (c) D4.3 MILSTD835 CDIPT4 (D, CONFIGURATION C) 4 LEAD CERAMIC DUALINLINE METAL SEAL PACKAGE IHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A b b b b c c D E e 0.00 BSC.54 BSC ea BSC 7.6 BSC ea/ 0.50 BSC 3.8 BSC L Q S S o 05 o 90 o 05 o aaa bbb ccc M N Rev. 0 4/94 FN877 Rev 0.00 Page of