PIN CONFIGURATIONS FEATURES APPLICATION ORDERING INFORMATION. FE, N Packages

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Victor Harrell
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1 DESCRIPTION The are monolithic sample-and-hold circuits which utilize high-voltage ion-implant JFET technology to obtain ultra-high DC accuracy with fast acquisition of signal and low droop rate. Operating as a unity gain follower, DC gain accuracy is.% typical and acquisition time is as low as µs to.%. A bipolar input stage is used to achieve low offset voltage and wide bandwidth. Input offset adjust is accomplished with a single pin and does not degrade input offset drift. The wide bandwidth allows the LF9 to be included inside the feedback loop of MHz op amps without having stability problems. Input impedance of Ω allows high source impedances to be used without degrading accuracy. PIN CONFIGURATIONS FE, N Packages OFFSET VOLTAGE REFEREE h TOP VIEW P-channel junction FETs are combined with bipolar devices in the output amplifier to give droop rates as low as mv/min with a µf hold capacitor. The JFETs have much lower noise than MOS devices used in previous designs and do not exhibit high temperature instabilities. The overall design guarantees no feedthrough from input to output in the hold mode even for input signals equal to the supply voltages. Logic inputs are fully differential with low input current, allowing direct connection to TTL, PMOS, and CMOS; differential threshold is.v. The will operate from ±V to ±V supplies. They are available in -pin plastic DIP, -pin Cerdip, and -pin plastic SO packages. D Package 9 V OS Adj REF FEATURES Operates from ±V to ±V supplies Less than µs acquisition time TTL, PMOS, CMOS compatible logic input.mv typical hold step at CH=.µF Low input offset.% gain accuracy Low output noise in hold mode Input characteristics do not change during hold mode High supply rejection ratio in sample or hold Wide bandwidth TOP VIEW NOTE:. SO and non-standard pinouts. APPLICATION The are ideally suited for a wide variety of sample-and-hold applications, including data acquisition, analog-to-digital conversion, synchronous demodulation, and automatic test setup ORDERING INFORMATION DESCRIPTION TEMPERATURE RANGE ORDER CODE DWG # -Pin Ceramic Dual In-Line Package (CERDIP) - C to + C LF9FE A -Pin Plastic Small Outline (SO) Package to + C LF9D D -Pin Ceramic Dual In-Line Package (CERDIP) to + C LF9FE A -Pin Plastic Dual In-Line Package (DIP) to + C LF9N B -Pin Ceramic Dual In-Line Package (CERDIP) - C to + C LF9FE A -Pin Plastic Dual In-Line Package (DIP) - C to + C LF9N B August,

2 FUTIONAL DIAGRAM TYPICAL APPLICATIONS OFFSET k REFEREE + SAMPLE V HOLD V ANALOG S/H HOLD CAPACITOR ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER RATING UNIT V S Supply voltage ± V T A Maximum power dissipation T A = C (still-air) F package mw N package mw D package mw Operating ambient temperature range LF9 - to + C LF9 - to + C LF9 to + C T STG Storage temperature range - to + C V IN Input voltage Equal to supply voltage Logic-to-logic reference differential voltage +, - V Output short-circuit duration Indefinite Hold capacitor short-circuit duration sec T SOLD Lead soldering temperature (sec max) C NOTES:. The maximum junction temperature of the LF9 is C. When operating at elevated ambient temperature, the packages must be derated based on the thermal resistance specified.. Although the differential voltage may not exceed the limits given, the common-mode voltage on the logic pins must always be at least V below the positive supply and V above the negative supply.. Derate above C, at the following rates: F package at.mw/ C N package at 9.mW/ C D package at.mw/ C August, 99

3 DC ELECTRICAL CHARACTERISTICS Unless otherwise specified, the following conditions apply: unit is in sample mode; V S = ±V; T J = C; -.V V IN +.V; C H =.µf; and R L = kω. Logic reference voltage = V and logic voltage =.V. SYMBOL PARAMETER TEST CONDITIONS LF9/LF9 LF9 Min Typ Max Min Typ Max T J = C V OS Input offset voltage Full temperature range UNIT mv T J = C I BIAS Input bias current Full temperature range na Input impedance T J = C Ω Gain error Feedthrough attenuation ratio at khz Output impedance T J = C, R L =k.... Full temperature range.. T J = C, =.µf 9 9 db T J = C, HOLD mode.. Full temperature range HOLD step T J = C, =.µf, V OUT =.... mv I CC Supply current T J C.... ma Logic and logic reference input current T J = C µa Leakage current into hold capacitor T J = C, HOLD mode pa t AC Acquisition time to.% Hold capacitor charging current Supply voltage rejection ratio V OUT =V, =pf =.µf V IN -V OUT =V ma V OUT = db Differential logic threshold T J = C V NOTES:. Unless otherwise specified, the following conditions apply. Unit is in sample mode, V S =±V, T J = C, -.V V IN +.V, =.µf, and R L = kω. Logic reference voltage = V and logic voltage =.V.. Hold step is sensitive to stray capacitive coupling between input logic signals and the hold capacitor. pf, for instance, will create an additional.mv step with a V logic swing and a.µf hold capacitor. Magnitude of the hold step is inversely proportional to hold capacitor value.. Leakage current is measured at a junction temperature of C. The effects of junction temperature rise due to power dissipation or elevated ambient can be calculated by doubling the C value for each C increase in chip temperature. Leakage is guaranteed over full input signal range.. The parameters are guaranteed over a supply voltage of ± to ±V. % Ω µs August, 99

4 TYPICAL DC PERFORMAE CHARACTERISTICS CURRENT (ma) HOLD STEP (mv). Input Bias Current Output Short Circuit Current Gain Error. T J = C L = k. SAMPLE JUTION TEMPERATURE ( C) Hold Step. pf pf.µf.µf µf HOLD CAPACITOR = = V T J = C CURRENT (na) CURRENT (ma) JUTION TEMPERATURE ( C) Leakage Current Into Hold Capacitor V S = ±V V OUT = HOLD SOURCING SINKING JUTION TEMPERATURE ( C) NORMALIZED HOLD STEP AMPLITUDE VOLTAGE VOLTAGE (mv) VOLTAGE (V) Hold Step Input Voltage T J = C T J = C T J = C VOLTAGE (V) TYPICAL AC PERFORMAE CHARACTERISTICS TIME ( s) µ Acquisition Time Aperture Time Capacitor Hysteresis % V IN = TO ±V.% T J = C.%... HOLD CAPACITOR (µf) TIME (ns) = = V V OUT mv NEGATIVE STEP V IN = V POSITIVE STEP JUTION TEMPERATURE ( C).. SAMPLE TIME (ms) August, 99

5 TYPICAL AC PERFORMAE CHARACTERISTICS (Continued) Dynamic Sampling Error Output Droop Rate Hold Sampling Time ERROR (mv) ± pf. SLEW RATE (V/ms) pf pf V/ T (V/SEC) T J = C T J = C pf pf.µf.µf µf HOLD CAPACITOR TIME ( s) µ = = V SETTLING TIME JUTION TEMPERATURE ( C) GAIN TO (db) Phase And Gain (Input to Output, Small-Signal) Power Supply Rejection Output Noise C h = T J = C = = V = pf V OUT = C.µF h = pf POSITIVE HOLD =.µf NEGATIVE.µF = k k k M M FREQUEY (Hz) TO PHASE DELAY ( o ) REJECTION RATIO (db) k k k M FREQUEY (Hz) NOISE (nv/ Hz) SAMPLE k k k FREQUEY (Hz) RATIO (db) 9 Feedthrough Rejection Ratio (Hold Mode) =.µf =.µf = pf = = V T J = C V IN = Vp-p V. = k k k M FREQUEY (Hz) August, 99

Voltage comparator PIN CONFIGURATIONS FEATURES BLOCK DIAGRAM APPLICATIONS ORDERING INFORMATION. D, N Packages

Voltage comparator PIN CONFIGURATIONS FEATURES BLOCK DIAGRAM APPLICATIONS ORDERING INFORMATION. D, N Packages DESCRIPTION The is a high-speed analog voltage comparator which, for the first time, mates state-of-the-art Schottky diode technology with the conventional linear process. This allows simultaneous fabrication