Dual Picoampere Input Current Bipolar Op Amp AD706

Transcription

1 a FEATURE HIGH DC PRECISION V max Offset Voltage.6 V/ C max Offset Drift pa max Input Bias Current LOW NOISE. V p-p Voltage Noise,. Hz to Hz LOW POWER A Supply Current Available in -Lead Plastic Mini-DlP, Hermetic Cerdip and Surface Mount (SOIC) Packages Available in Tape and Reel in Accordance with EIA-A Standard Single Version: AD, Quad Version: AD PRIMARY APPLICATIONS Low Frequency Active Filters Precision Instrumentation Precision Integrators PRODUCT DESCRIPTION The is a dual, low power, bipolar op amp that has the low input bias current of a BiFET amplifier, but which offers a significantly lower I B drift over temperature. It utilizes superbeta bipolar input transistors to achieve picoampere input bias current levels (similar to FET input amplifiers at room temperature), while its I B typically only increases by at C (unlike a BiFET amp, for which I B doubles every C for a increase at C). The also achieves the microvolt offset voltage and low noise characteristics of a precision bipolar input amplifier. Since it has only the input bias current of an OP, the does not require the commonly used balancing resistor. Furthermore, the current noise is / that of the OP, which makes this amplifier usable with much higher source impedances. At /6 the supply current (per amplifier) of the OP, the is better suited for today s higher density boards. The is an excellent choice for use in low frequency active filters in - and -bit data acquisition systems, in precision instrumentation and as a high quality integrator. The is internally compensated for unity gain and is available in five performance grades. The J and K are rated over the commercial temperature range of C to + C. The A and B are rated over the industrial temperature range of C to + C. Dual Picoampere Input Current Bipolar Op Amp CONNECTION DIAGRAM Plastic Mini-DIP (N) Cerdip (Q) and Plastic SOIC (R) Packages AMPLIFIER AMPLIFIER OUTPUT IN IN V TOP VIEW 6 V OUTPUT IN The is offered in three varieties of an -lead package: plastic mini-dip, hermetic cerdip and surface mount (SOIC). J grade chips are also available. PRODUCT HIGHLIGHTS. The is a dual low drift op amp that offers BiFET level input bias currents, yet has the low I B drift of a bipolar amplifier. It may be used in circuits using dual op amps such as the LT.. The provides both low drift and high dc precision.. The can be used in applications where a chopper amplifier would normally be required but without the chopper s inherent noise. TYPICAL I B na. TYPICAL JFET AMP IN TEMPERATURE C Figure. Input Bias Current vs. Temperature Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 96, Norwood, MA 6-96, U.S.A. Tel: /9- World Wide Web Site: Fax: /6- Analog Devices, Inc., 99

2 SPECIFICATIONS T A = + C, V CM = V and V dc, unless otherwise noted) J/A K/B Parameter Conditions Min Typ Max Min Typ Max Units INPUT OFFSET VOLTAGE Initial Offset µv Offset T MIN to T MAX µv vs. Temp, Average TC....6 µv/ C vs. Supply (PSRR) V S = ± V to ± V db T MIN to T MAX V S = ±. V to ± V db Long Term Stability.. µv/month V CM = V pa V CM = ±. V 6 pa vs. Temp, Average TC.. pa/ C T MIN to T MAX V CM = V pa T MIN to T MAX V CM = ±. V pa INPUT OFFSET CURRENT V CM = V pa V CM = ±. V pa vs. Temp, Average TC.6. pa/ C T MIN to T MAX V CM = V pa T MIN to T MAX V CM = ±. V pa MATCHING CHARACTERISTICS Offset Voltage µv T MIN to T MAX µv Input Bias Current pa T MIN to T MAX pa Common-Mode Rejection 6 db T MIN to T MAX 6 db Power Supply Rejection 6 db T MIN to T MAX 6 db f = Hz (Figure 9a) R L = kω db FREQUENCY RESPONSE Unity Gain Crossover Frequency.. MHz Slew Rate G =.. V/µs T MIN to T MAX.. V/µs INPUT IMPEDANCE Differential MΩ pf Common Mode GΩ pf INPUT VOLTAGE RANGE Common-Mode Voltage ±. ± ±. ± V Common-Mode Rejection Ratio V CM = ±. V db T MIN to T MAX db INPUT CURRENT NOISE. Hz to Hz pa p-p f = Hz fa/ Hz INPUT VOLTAGE NOISE. Hz to Hz... µv p-p f = Hz nv/ Hz f = khz nv/ Hz OPEN-LOOP GAIN V O = ± V R LOAD = kω V/mV T MIN to T MAX V/mV V O = ± V R LOAD = kω V/mV T MIN to T MAX V/mV OUTPUT CHARACTERISTICS Voltage Swing R LOAD = kω ± ± ± ± V T MIN to T MAX ± ± ± ± V Current Short Circuit ± ± ma Capacitive Load Drive Capability Gain = +,, pf

3 J/A K/B Parameter Conditions Min Typ Max Min Typ Max Units POWER SUPPLY Rated Performance ± ± V Operating Range ±. ± ±. ± V Quiescent Current, Total.... ma T MIN to T MAX.... ma TRANSISTOR COUNT # of Transistors 9 9 NOTES l Bias current specifications are guaranteed maximum at either input. Input bias current match is the difference between corresponding inputs (I B of IN of Amplifier # minus I B of IN of Amplifier #). CMRR match is the difference between V OS # V CM for amplifier # and V OS # V CM for amplifier # expressed in db. V OS # PSRR match is the difference between V SUPPLY All min and max specifications are guaranteed. Specifications subject to change without notice. for amplifier #l and V OS # V SUPPLY for amplifier # expressed in db. ABSOLUTE MAXIMUM RATINGS l Supply Voltage ± V Internal Power Dissipation (Total: Both Amplifiers) mw Input Voltage ±V S Differential Input Voltage Volts Output Short Circuit Duration Indefinite Storage Temperature Range (Q) C to + C Storage Temperature Range (N, R) C to + C Operating Temperature Range J/K C to + C A/B C to + C Lead Temperature (Soldering secs) C NOTES Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Specification is for device in free air: -Lead Plastic Package: θ JA = C/Watt -Lead Cerdip Package: θ JA = C/Watt -Lead Small Outline Package: θ JA = C/Watt The input pins of this amplifier are protected by back-to-back diodes. If the differential voltage exceeds ±. volts, external series protection resistors should be added to limit the input current to less than ma. ORDERING GUIDE Temperature Package Model Range Description Option* AN C to + C Plastic DIP N- JN C to + C Plastic DIP N- KN C to + C Plastic DIP N- JR C to + C SOIC R- JR-REEL C to + C Tape and Reel AQ C to + C Cerdip Q- BQ C to + C Cerdip Q- AR C to + C SOIC R- AR-REEL C to + C Tape and Reel *N = Plastic DIP; Q = Cerdip, R = Small Outline Package. OUTPUT A INPUT A METALIZATION PHOTOGRAPH Dimensions shown in inches and (mm). Contact factory for latest dimensions.. (.) OUTPUT B +INPUT A 6 INPUT B +INPUT B. (.) CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as V readily accumulate on the human body and test equipment and can discharge without detection. Although the features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE

4 Typical Characteristics + C, V S = V, unless otherwise noted) SAMPLE SIZE: SAMPLE SIZE: SAMPLE SIZE: NUMBER OF UNITS 6 NUMBER OF UNITS 6 NUMBER OF UNITS 6 INPUT OFFSET VOLTAGE V Figure. Typical Distribution of Input Offset Voltage 6 6 INPUT BIAS CURRENT pa Figure. Typical Distribution of Input Bias Current 6 6 INPUT OFFSET CURRENT pa Figure. Typical Distribution of Input Offset Current INPUT COMMON-MODE VOLTAGE LIMIT Volts (REFERRED TO SUPPLY VOLTAGES) V S SUPPLY VOLTAGE Volts Figure. Input Common-Mode Voltage Range vs. Supply Voltage OUTPUT VOLTAGE Volts p-p k k k M Figure 6. Large Signal Frequency Response OFFSET VOLTAGE DRIFT V/ C. SOURCE RESISTANCE MAY BE EITHER BALANCED OR UNBALANCED FOR INDUSTRIAL TEMPERATURE RANGE. k k k M M M SOURCE RESISTANCE Figure. Offset Voltage Drift vs. Source Resistance NUMBER OF UNITS 6 SAMPLE SIZE: C TO C.... OFFSET VOLTAGE DRIFT V/ C Figure. Typical Distribution of Offset Voltage Drift CHANGE IN OFFSET VOLTAGE V WARM-UP TIME Minutes Figure 9. Change in Input Offset Voltage vs. Warm-Up Time INPUT BIAS CURRENT pa 6 POSITIVE I B NEGATIVE I B 6 COMMON-MODE VOLTAGE Volts Figure. Input Bias Current vs. Common-Mode Voltage

5 VOLTAGE NOISE nv/ Hz CURRENT NOISE fa/ Hz M k V OUT. V Figure. Input Noise Voltage Spectral Density Figure. Input Noise Current Spectral Density TIME Seconds Figure.. Hz to Hz Noise Voltage QUIESCENT CURRENT A 9 + C + C C CMRR db PSRR db 6 + PSRR PSRR 6 SUPPLY VOLTAGE Volts Figure. Quiescent Supply Current vs. Supply Voltage. k k k M Figure. Common-Mode Rejection Ratio vs. Frequency. k k k M Figure 6. Power Supply Rejection Ratio vs. Frequency M OPEN-LOOP VOLTAGE GAIN M + C C + C OPEN-LOOP VOLTAGE GAIN db 6 GAIN PHASE 6 9 PHASE SHIFT Degrees OUTPUT VOLTAGE SWING Volts (REFERRED TO SUPPLY VOLTAGES) k 6 LOAD RESISTANCE k Figure. Open-Loop Gain vs. Load Resistance vs. Load Resistance.. k k k M M Figure. Open-Loop Gain and Phase Shift vs. Frequency SUPPLY VOLTAGE Volts Figure 9. Output Voltage Swing vs. Supply Voltage

6 CROSSTALK db CLOSED-LOOP OUTPUT IMPEDANCE.. AV = I OUT = +ma AV = + 6 k k k Figure a. Crosstalk vs. Frequency. F. k k k Figure. Magnitude of Closed-Loop Output Impedance vs. Frequency R F SINE WAVE GENERATOR. F R L k V OUT # V p-p V IN. F R L k V OUT C L k SQUARE WAVE INPUT. F.k 6 F. F V OUT # Figure a. Unity Gain Follower (For Large Signal Applications, Resistor R F Limits the Current Through the Input Protection Diodes) V CROSSTALK = LOG OUT # db V OUT # Figure b. Crosstalk Test Circuit Figure b. Unity Gain Follower Large Signal Pulse Response, R F = kω, C L =, pf Figure c. Unity Gain Follower Small Signal Pulse Response, R F = Ω, C L = pf Figure d. Unity Gain Follower Small Signal Pulse Response, R F = Ω, C L = pf 6

7 k V IN k + +. F R L.k V OUT C L SQUARE WAVE INPUT.µF Figure a. Unity Gain Inverter Connection Figure b. Unity Gain Inverter Large Signal Pulse Response, C L =, pf Figure c. Unity Gain Inverter Small Signal Pulse Response, C L = pf Figure d. Unity Gain Inverter Small Signal Pulse Response, C L = pf Figure shows an in-amp circuit that has the obvious advantage of requiring only one, rather than three op amps, with subsequent savings in cost and power consumption. The transfer function of this circuit (without R G ) is: V OUT = (V IN # V IN # )+ R R for R = R and R = R Input resistance is high, thus permitting the signal source to have an unbalanced output impedance. V IN# R 9.9k V IN# R P * k R P * k + A R R R. F R G (OPTIONAL) + 9.9k A V OUT = (V IN# V IN# ) (+ R ) + ( R ) FOR R = R, R = R R R G OUTPUT. F *OPTIONAL INPUT PROTECTION RESISTOR FOR GAINS GREATER THAN OR INPUT VOLTAGES EXCEEDING THE SUPPLY VOLTAGE. Figure. A Two Op-Amp Instrumentation Amplifier Furthermore, the circuit gain may be fine trimmed using an optional trim resistor, R G. Like the three op-amp circuit, CMR 6 increases with gain, once initial trimming is accomplished but CMR is still dependent upon the ratio matching of Resistors R through R. Resistor values for this circuit, using the optional gain resistor, R G, can be calculated using: R= R = 9.9 kω 9.9 kω R = R =.9 G 99. kω R G =.6 G where G = Desired Circuit Gain Table I provides practical % resistance values. (Note that without resistor R G, R and R = 9.9 kω/g.) Table I. Operating Gains of Amplifiers A and A and Practical % Resistor Values for the Circuit of Figure Circuit Gain Gain of A Gain of A R, R R, R kω 9.9 kω... kω 9.9 kω... kω 9.9 kω kω 9.9 kω....9 kω 9.9 kω Ω 9.9 kω. 9.9 Ω 9.9 kω For a much more comprehensive discussion of in-amp applications, refer to the Instrumentation Amplifier Applications Guide available free from Analog Devices, Inc.

8 INPUT R M R M *WITHOUT THE NETWORK, PINS &, AND 6 & OF THE ARE TIED TOGETHER. CAPACITORS C & C ARE SOUTHERN ELECTRONICS MPCC, POLYCARB %, VOLT + C A Hz, -Pole, Active Filter Figure shows the in an active filter application. An important characteristic of the is that both the input bias current, input offset current and their drift remain low over most of the op amp s rated temperature range. Therefore, for most applications, there is no need to use the normal balancing resistor. Adding the balancing resistor enhances performance at high temperatures, as shown by Figure 6. C R M C R R M M C. F 6 C. F OPTIONAL BALANCE RESISTOR NETWORKS* Figure. A Hz, -Pole Active Filter OFFSET VOLTAGE OF FILTER CIRCUIT (RTI) V R6 M. F C6. F OUTPUT WITHOUT OPTIONAL BALANCE RESISTOR, R WITH OPTIONAL BALANCE RESISTOR, R TEMPERATURE C Figure 6. V OS vs. Temperature Performance of the Hz Filter C9b /9 Table II. Hz, -Pole, Low Pass Filter Recommended Component Values Section Section Desired Low Frequency Frequency C C C C Pass Response (Hz) Q (Hz) Q ( F) ( F) ( F) ( F) Bessel Butterworth db Chebychev db Chebychev db Chebychev db Chebychev (.) MIN NOTE Specified Values are for a db point of. Hz. For other frequencies simply scale capacitors C through C directly, i.e.: for Hz Bessel response, C =. µf, C =. µf, C =. µf, C =. µf.. (.) MAX Cerdip (Q-). (.). (.9) PIN. (.9) MAX.6 (.). (.). (.) MAX.. (.) (.) MIN. (.). (.). (.) SEATING. PLANE. (.6) (.). (.6) BSC. (.).9 (.). (.). (.). (.) MAX.6 (.6). (.9). (.). (.6) OUTLINE DIMENSIONS Dimensions shown in inches and (mm).. (.9). (.) Plastic Mini-DIP (N-). (.). (6.) PIN.6 (.). (.).. (.). (.) (.) BSC. (.) MIN SEATING PLANE. (.). (.6). (.). (.).9 (.9). (.9). (6.). (.).9 (.). (.) SEATING PLANE.96 (.).9 (.) SOIC (R-). (.).9 (.) PIN. (.) BSC. (.9).9 (.9).9 (.9). (.).9 (.). (.9).96 (.).99 (.) x. (.).6 (.) PRINTED IN U.S.A.