HA Microsecond Precision Sample and Hold Amplifier. Features. Applications. Pinouts. Ordering Information. Data Sheet August 24, 2005 FN2857.

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1 Data Sheet FN85. Microsecond Precision Sample and Hold Amplifier The was designed for use in precision, high speed data acquisition systems. The circuit consists of an input transconductance amplifier capable of providing large amounts of charging current, a low leakage analog switch, and an output integrating amplifier. The analog switch sees virtual ground as its load; therefore, charge injection on the hold capacitor is constant over the entire input/output voltage range. The pedestal voltage resulting from this charge injection can be adjusted to zero by use of the offset adjust inputs. The device includes a hold capacitor. However, if improved droop rate is required at the expense of acquisition time, additional hold capacitance may be added externally. This monolithic device is manufactured using the Intersil Dielectric Isolation Process, minimizing stray capacitance and eliminating SCRs. This allows higher speed and latchfree operation. For further information, please see Application Note AN538. Pinouts -INPUT +INPUT OFFSET ADJUST OFFSET ADJUST SIG. GND (PDIP, CERDIP) TOP VIEW (SOIC) TOP VIEW SUPPLY GND C EXT 9 V+ INTEGRATOR 8 BANDWIDTH Features Gain, DC x 0 6 V/V Acquisition Time µs (0.0%) Droop Rate µV/µs (5 C) µv/µs (Full Temperature) Aperture Time ns Hold Step Error (See Glossary) mV Internal Hold Capacitor Fully Differential Input TTL Compatible Pb-Free Plus Anneal Available (RoHS Compliant) Applications Precision Data Acquisition Systems Digital to Analog Converter Deglitcher Auto Zero Circuits Peak Detector Ordering Information PART NUMBER PART MARKING TEMP. RANGE ( C) PACKAGE PKG. DWG. # to 5 4 Ld CERDIP F to 5 4 Ld CERDIP F4.3 HA HA to 5 4 Ld PDIP E4.3 HA9P530-5 HA9P to 5 6 Ld SOIC M6.3 HA9P530-5Z (Note) HA9P530-5Z 0 to 5 6 Ld SOIC (Pb-free) M6.3 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 00% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-00. -INPUT 6 +INPUT 5 SUPPLY GND OFFSET ADJUST 3 4 OFFSET ADJUST 4 3 C EXT 5 SIG. GND V+ INTEGRATOR BANDWIDTH CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures INTERSIL or Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 003, 005. All Rights Reserved All other trademarks mentioned are the property of their respective owners.

2 Functional Diagram OFFSET ADJUST 3 4 V+ 9 00pF -INPUT +INPUT - + S/H CONTROL SUPPLY GND SIG. GND C EXT INTEGRATOR BANDWIDTH FN85.

3 Absolute Maximum Ratings Supply Voltage V Differential Input Voltage V Digital Input Voltage V, -5V Output Current, Continuous (Note ) ±0mA Operating Conditions Temperature Range C to 5 C C to 5 C Supply Voltage Range (Typical, Note ) ±3.5V to ±0V Thermal Information Thermal Resistance (Typical, Note 3) θ JA ( C/W) θ JC ( C/W) CERDIP Package PDIP Package N/A SOIC Package N/A Maximum Junction Temperature (Ceramic Package) C Maximum Junction Temperature (Plastic Package) C Maximum Storage Temperature Range C to 50 C Maximum Lead Temperature (Soldering 0s) C (SOIC - Lead Tips Only) CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES:. Internal Power Dissipation may limit Output Current below 0mA.. Specification based on a one time characterization. This parameter is not guaranteed. 3. θ JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications V SUPPLY = ±5.0V; C H = Internal; Digital Input: V IL = +0.8V (Sample), V IH = +.0V (Hold), Unity Gain Configuration (Output tied to -Input), Unless Otherwise Specified PARAMETER TEST CONDITIONS TEMP. ( C) - -5 MIN TYP MAX MIN TYP MAX UNITS INPUT CHARACTERISTICS Input Voltage Range Full ±0 - - ±0 - - V Input Resistance MΩ Input Capacitance pf Offset Voltage mv Full mv Bias Current na Full na Offset Current na Full na Common Mode Range Full ±0 - - ±0 - - V CMRR V CM = ±5V db Offset Voltage Temperature Coefficient Full µv/ C TRANSFER CHARACTERISTICS Gain DC, (Note ) x x 0 5 x V/V Gain Bandwidth Product (A V = +, Note 5) C H = 00pF MHz C H = 000pF MHz CHARACTERISTICS Output Voltage Full ±0 - - ±0 - - V Output Current 5 ±0 - - ±0 - - ma Full Power Bandwidth Note khz Output Resistance Hold Mode Ω Total Output Noise (DC to 0MHz) Sample µv RMS Hold µv RMS 3 FN85.

4 Electrical Specifications V SUPPLY = ±5.0V; C H = Internal; Digital Input: V IL = +0.8V (Sample), V IH = +.0V (Hold), Unity Gain Configuration (Output tied to -Input), Unless Otherwise Specified (Continued) PARAMETER TRANSIENT RESPONSE Rise Time Note ns Overshoot Note % Slew Rate Note V/µs DIGITAL INPUT CHARACTERISTICS Input Voltage V IH Full V V IL Full V Input Current V IL = 0V µa SAMPLE AND HOLD CHARACTERISTICS Full µa V IH = +5V Full µa Acquisition Time (Note ) To 0.% µs To 0.0% µs Aperture Time (Note 8) ns Effective Aperture Delay Time ns Aperture Uncertainty ns Droop Rate µv/µs Full µv/µs Drift Current Note pa Full na Charge Transfer Note pc Hold Step Error Note mv Hold Mode Settling Time To 0.0% Full ns Hold Mode Feedthrough 0V P-P, 00kHz Full mv POWER SUPPLY CHARACTERISTICS TEST CONDITIONS TEMP. ( C) - -5 MIN TYP MAX MIN TYP MAX Positive Supply Current Note ma Negative Supply Current Note ma Supply Voltage Range Note ±3.5 ±0 ±3.5 - ±0 V Power Supply Rejection V+, Note Full db, Note Full db NOTES: 4. V O = 0V P-P ; R L = kω; C L = 50pF; unattenuated output. 5. V O = 00mV P-P ; R L = kω; C L = 50pF. 6. V O = 0V Step; R L = kω; C L = 50pF.. V O = 0V Step; R L = kω; C L = 50pF. 8. Derived from computer simulation only; not tested. 9. V IN = 0V, V IH = +3.5V, t R < 0ns (V IL to V IH ). 0. Specified for a zero differential input voltage between +IN and -IN. Supply current will increase with differential input (as may occur in the Hold mode) to approximately ±46mA at 0V.. Based on a V delta in each supply, i.e. 5V ±0.5V DC.. R L = kω, C L = 30pF. UNITS 4 Teflon is a registered Trademark of Dupont Corporation. FN85.

5 Test Circuits and Waveforms S/H CONTROL INPUT -INPUT 4 +INPUT 8 V O (C H = 00pF) FIGURE. CHARGE TRANSFER AND DRIFT CURRENT HOLD (+3.5V) SAMPLE (0V) HOLD (+3.5V) SAMPLE (0V) V O V O V O V P NOTES: 3. Observe the hold step voltage V P. 4. Compute charge transfer: Q = V P C H. FIGURE. CHARGE TRANSFER TEST t NOTES: 5. Observe the voltage droop, V O / t. 6. Measure the slope of the output during hold, V O / t, and compute drift current: I D = C H V O / t. FIGURE 3. DRIFT CURRENT TEST V+ 0V P-P 00kHz SINE WAVE INPUT V IN ANALOG MUX OR SWITCH A IN 4 -IN +IN 9 5 SUPPLY GND C EXT 3 6 REF COM OUT INT. COMP. 8 V OUT NOTE: Feedthrough in V db = 0log OUT where: V IN V OUT = V P-P, Hold Mode, V IN = V P-P. TO SUPPLY COMMON TO SIGNAL GND FIGURE 4. HOLD MODE FEEDTHROUGH ATTENUATION Application Information The has the uncommitted differential inputs of an op amp, allowing the Sample and Hold function to be combined with many conventional op amp circuits. See the Intersil Application Note AN5 for a collection of circuit ideas. Layout A printed circuit board with ground plane is recommended for best performance. Bypass capacitors (0.0µF to 0.µF, ceramic) should be provided from each power supply terminal to the Supply Ground terminal on pin 3. The ideal ground connections are pin 6 (SIG. Ground) directly to the system Signal Ground, and pin 3 (Supply Ground) directly to the system Supply Common. Hold Capacitor The includes a 00pF MOS hold capacitor, sufficient for most high speed applications (the Electrical Specifications section is based on this internal capacitor). Additional capacitance may be added between pins and. This external hold capacitance will reduce droop rate at the expense of acquisition time, and provide other trade-offs as shown in the Performance Curves. If an external hold capacitor C EXT is used, then a noise bandwidth capacitor of value 0.C EXT should be connected from pin 8 to ground. Exact value and type are not critical. The hold capacitor C EXT should have high insulation resistance and low dielectric absorption, to minimize droop errors. Polystyrene dielectric is a good choice for operating temperatures up to 85 C. Teflon and glass dielectrics offer good performance to 5 C and above. 5 FN85.

6 The hold capacitor terminal (pin ) remains at virtual ground potential. Any PC connection to this terminal should be kept short and guarded by the ground plane, since nearby signal lines or power supply voltages will introduce errors due to drift current. Typical Application Figure 5 shows the connected as a unity gain noninverting amplifier - its most widely used configuration. As an input device for a fast successive - approximation A/D converter, it offers very high throughput rate for a monolithic IC sample/hold amplifier. Also, the s hold step error is adjustable to zero using the Offset Adjust potentiometer, to deliver a -bit accurate output from the converter. The application may call for an external hold capacitor C EXT as shown. As mentioned earlier, 0.C EXT is then recommended at pin 8 to reduce output noise in the Hold mode. The output circuit does not include short circuit protection, and consequently its output impedance remains low at high frequencies. Thus, the step changes in load current which occur during an A/D conversion are absorbed at the S/H output with minimum voltage error. A momentary short circuit to ground is permissible, but the output is not designed to tolerate a short of indefinite duration. Glossary of Terms Acquisition Time The time required following a sample command, for the output to reach its final value within ±0.% or ±0.0%. This is the minimum sample time required to obtain a given accuracy, and includes switch delay time, slewing time and settling time. Charge Transfer The small charge transferred to the holding capacitor from the inter-electrode capacitance of the switch when the unit is switched to the HOLD mode. Charge transfer is directly proportional to sample-to-hold offset pedestal error, where: Charge Transfer (pc) = C H (pf) x Hold Step Error (V) Aperture Time The time required for the sample-and-hold switch to open, independent of delays through the switch driver and input amplifier circuitry. The switch opening time is the interval between the conditions of 0% open and 90% open. Hold Step Error Hold Step Error is the output error due to Charge Transfer (see above). It may be calculated from the specified parameter, Charge Transfer, using the following relationship: Hold Step (V) Charge Transfer (pc) = Hold Capacitance (pf) See Performance Curves. Effective Aperture Delay Time (EADT) The difference between the digital delay time from the Hold command to the opening of the S/H switch, and the propagation time from the analog input to the switch. EADT may be positive, negative or zero. If zero, the S/H amplifier will output a voltage equal to V IN at the instant the Hold command was received. For negative EADT, the output in Hold (exclusive of pedestal and droop errors) will correspond to a value of V IN that occurred before the Hold command. Aperture Uncertainty The range of variation in Effective Aperture Delay Time. Aperture Uncertainty (also called Aperture Delay Uncertainty, Aperture Time Jitter, etc.) sets a limit on the accuracy with which a waveform can be reconstructed from sample data. Drift Current The net leakage current from the hold capacitor during the hold mode. Drift current can be calculated from the droop rate using the formula: V I D (pa) = C H ( pf) (V/s) t OFFSET ADJUST ±5mV 0kΩ -5V +5V HI-54A C EXT V IN H S pF CONVERT 3 5 INPUT R/C DIGITAL SYSTEM POWER GROUND 0.C EXT SYSTEM SIGNAL GROUND 9 ANALOG COMMON NOTE: Pin Numbers Refer to DIP Package Only. FIGURE 5. TYPICAL CONNECTIONS; NONINVERTING UNITY GAIN MODE 6 FN85.

7 Typical Performance Curves 0 5 ACQUISITION TIME FOR 0V STEP TO +0.0% (µs) 000 C H = 00pF, INTERNAL VOLTAGE DROOP DURING HOLD MODE, (mv/00ms) I DRIFT (pa) SAMPLE-TO-HOLD OFFSET (HOLD STEP) ERROR, (mv) K 00K C H VALUE (pf) FIGURE 6. TYPICAL SAMPLE AND HOLD PERFORMAE AS A FUTION OF HOLD CAPACITOR TEMPERATURE ( C) FIGURE. DRIFT CURRENT vs TEMPERATURE GAIN (db) GAIN (C H = 00pF) PHASE (C H = 00pF) GAIN PHASE (DEGREES) K 0K 00K M 0M FREQUEY (Hz) FIGURE 8. OPEN LOOP GAIN AND PHASE RESPONSE C H = 00pF T A = 5 C HOLD STEP VOLTAGE (mv) 5.0 C H = 00pF 0.5 C H = 000pF 0.05 C H = 0.0µF HOLD STEP VOLTAGE 5 C 5 C DC INPUT (V) FIGURE 9A. HOLD STEP vs INPUT VOLTAGE LOGIC LEVEL HIGH (V) FIGURE 9B. HOLD STEP vs LOGIC (V IH ) VOLTAGE FIGURE 9. TYPICAL SAMPLE-TO-HOLD OFFSET (HOLD STEP) ERROR FN85.

8 Die Characteristics DIE DIMENSIONS: 9 mils x 5 mils x 9 mils METALLIZATION: Type: Al, % Cu Thickness: 6kÅ ±kå PASSIVATION: Type: Nitride (Si 3 N 4 ) over Silox (SiO, 5% Phos) Silox Thickness: kå ±kå Nitride Thickness: 3.5kÅ ±.5kÅ TRANSISTOR COUNT: 84 SUBSTRATE POTENTIAL: Metallization Mask Layout SUPPLY GND (3) C EXT V+ () (9) S/H CTRL (4) -INPUT () (8) INT BW () +INPUT () (6) SIG GND (3) V IO ADJ (4) V IO ADJ (5) All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation s quality certifications can be viewed at Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see 8 FN85.