HIP V, 300mA Three Phase High Side Driver. Features. Applications. Ordering Information. Pinout. July 2004

Transcription

1 HIP0 Data Sheet July 00 FN. 0V, 00mA Three Phase High Side Driver The HIP0 is a three phase high side N-channel MOSFET driver, specifically targeted for PWM motor control. Two HIP0 may be used together for phase full bridge applications (see application block diagram). Alternatively, the lower gates may be controlled directly from a buffered microprocessor output. Unlike other members of the HIP0x family, the HIP0 has no built in turn-on delay. Each output (, BHO, and CHO) will turn-on 5ns after its input is switched low. Likewise, each output will turn-off 0ns after its input is switched high. Very short and very long dead times are possible when two HIP0 are used to drive a full bridge. This dead time is controlled by the input signal timing. The HIP0 does not have a built in charge pump. Therefore, the bootstrap capacitors must be recharged on a periodic basis by initiating a short refresh pulse. In most bridge applications, this will happen automatically every time the lower FETs turn-on and the upper FETs turn-off. However, it is still possible to use the HIP0 in applications that require the high side FETs to be on for extended periods of time. This can be easily accomplished by sending a short refresh pulse to the DIS pin. The HIP0 has reduced drive current compared to the HIP0 making it ideal for low to moderate power applications. The HIP0 is optimized for applications where size and cost are important. For high power applications driving large power FETs, the HIP0 is recommended. Features Independently Drives Three High Side N-Channel MOSFETs in Three Phase Bridge Configuration Bootstrap Supply Max Voltage to 95VDC Bias Supply Operation from V to 5V Drives 000pF Load with Typical Rise Times of 5ns and Fall Times of 0ns CMOS/TTL Compatible Inputs Programmable Undervoltage Protection Pb-free Available Applications Brushless Motors High Side Switches AC Motor Drives Switched Reluctance Motor Drives Ordering Information PART NUMBER TEMP. RANGE ( C) PACKAGE PKG. DWG. # HIP0AB -0 to 05 Ld SOIC M.5 HIP0ABZ (Note) -0 to 05 Ld SOIC (Pb-free) M.5 HIP0AP -0 to 05 Ld PDIP E. HIP0APZ (Note) -0 to 05 Ld PDIP (Pb-free) E. Pinout HIP0 (PDIP, SOIC) TOP VIEW CHB NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 00% matte tin plate termination finish, which is compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J Std-00B. 5 CHO CHS DIS UVLO V SS 5 V DD BHB 0 BHO AHS 9 BHS CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. --INTERSIL or -- Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Harris Corporation 995. Copyright Intersil Americas Inc. 00, 00. All Rights Reserved All other trademarks mentioned are the property of their respective owners.

2 Application Block Diagram Functional Block Diagram V 0V GND GND BHO CHO HIP0 V GND BHO CHO MICRO- CONTROLLER (OPTIONAL) HIP0 V DD DIS AHS UV UVLO LEVEL SHIFTER DRIVER AHS UV DRIVER AHS UV DRIVER LEVEL SHIFTER LEVEL SHIFTER LOGIC EN UNDERVOLTAGE DETECTOR UV HIP0

3 HIP0 TRUTH TABLE INPUT OUTPUT,, UV DIS, BHO, CHO X X 0 X X NOTE: X signifies that input can be either a or 0. Typical Application: Three Phase Bridge Driver with Programmable Dead Time P SUPPLY C BYPASS CHB POWER BUS OPTIONAL MICROPROCESSOR INPUTS CHO 5 CHS C BS DIS UVLO 5 V SS V DD BHB BHO 0 C BS C BS AHS BHS 9 OC SENSE R CURRENT SENSE OPTIONAL MICROPROCESSOR INPUTS CHB CHO 5 CHS DIS UVLO 5 V SS V DD BHB -PHASE LOAD BHO 0 AHS BHS 9

4 HIP0 Typical Application: High Side Switch BOOT STRAP CAPACITOR AND DIODE REQUIRED 0V REFRESH V DIS MICRO- PROCESSOR HIP0 BHO CHO GND LIGHT Pin Descriptions PIN NUMBER SYMBOL DESCRIPTION BHB CHB (xhb) (xhi) Gate driver supplies. One external bootstrap diode and one capacitor are required for each. The bootstrap diode and capacitor may be omitted when the HIP0 is used to drive the lower gates in three phase full bridge applications. In this case, tie all three xhb pins to V DD and tie the xhs pins to the sources of the lower FETs. In full bridge applications, the lower FETs must be turned on first at start up to refresh the bootstrap capacitors. In high side switch applications, the load will keep xhs low and refresh should happen automatically at start up. Logic level inputs. Logic at these three pins controls the three output drivers,, BHO and CHO. When xhi is low, xho is high. When xhi is high, xho is low. DIS (Disable) overrides all input signals. xhi can be driven by signal levels of 0V to 5V (no greater than V DD ). 5 V SS Chip ground. UVLO Undervoltage setting. A resistor can be connected between this pin and V SS to program the under voltage set point - see Figure. With this pin not connected the undervoltage set point is typically V. When this pin is tied to V DD, the undervoltage set point is typically.v. DIS Disable input. Logic level input that when taken high sets all three outputs low. DIS high overrides all other inputs. When DIS is taken low the outputs are controlled by the other inputs. DIS can be driven by signal levels of 0V to 5V (no greater than V DD ) BHO CHO (xho) AHS BHS CHS (xhs) Gate connections. Connect to the gates of the power MOSFETs in each phase. MOSFET source connection. Connect the sources of the power MOSFETs and the negative side of the bootstrap capacitors to these pins. In high side switch applications, ma of current will flow out of these pins into the load when the upper FETs are off. This current is necessary to guarantee that the upper FETs stay off. This current tends to pull xhs high. For proper refresh, the load must pull the voltage on xhs down to at least V below V DD. For example, when V DD = V, xhs must be pulled down to 5V. Therefore, the minimum load necessary for proper refresh is given by the following equation: R MIN = 5V/mA =.5kΩ. So in this case, if the load has an impedance less than 5kΩ, refresh will happen automatically at start up. V DD Positive supply rail. Bypass this pin to V SS with a capacitor >µf. In applications where the bus voltage and chip V DD are at the same potential, it is a good idea to run a separate line from the supply to each. This greatly simplifies the filtering requirements.

5 HIP0 Absolute Maximum Ratings T A = 5 C Thermal Information Supply Voltage, V DD V to V Logic I/O Voltages V to V DD +0.V Voltage on xhs V (Transient) to 5V (-0 C to 50 C) Voltage on xhb V xhs -0.V to V xhs +V DD Voltage on xlo V SS -0.V to V DD +0.V Voltage on xho V xhs -0.V to V xhb +0.V Phase Slew Rate V/ns Thermal Resistance (Typical, Note ) θ JA ( C/W) SOIC Package DIP Package Maximum Storage Temperature Range C to 50 C Maximum Junction Temperature C Maximum Lead Temperature (Soldering 0s) C (SOIC - Lead Tips Only) Operating Conditions Supply Voltage, V DD V to +5V Voltage on xhs V to 0V Voltage on xhb V xhs +V DD Operating Ambient Temperature Range C to 5 C CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES:. θ JA is measured with the component mounted on an evaluation PC board in free air.. All voltages are relative to V SS unless otherwise specified.. x = A, B and C. For example, xhs refers to AHS, BHS and CHS. Electrical Specifications V DD = V xhb = V, V SS = V xhs = 0V, Gate Capacitance (C GATE ) = 000pF, R UV = T J = 5 C T J = -0 C TO 50 C PARAMETER TEST CONDITIONS MIN TYP MAX MIN MAX UNITS SUPPLY CURRENTS AND UNDER VOLTAGE PROTECTION V DD Quiescent Current xhi = 5V ma V DD Operating Current f = 0kHz, 50% Duty Cycle ma xhb On Quiescent Current xhi = 0V µa xhb Off Quiescent Current xhi = 5V ma xhb Operating Current f = 0kHz, 50% Duty Cycle ma V DD Rising Undervoltage Threshold R UV OPEN V V DD Falling Undervoltage Threshold R UV OPEN V Minimum Undervoltage Threshold R UV = V DD V INPUT PINS:,, AND DIS Low Level Input Voltage V High Level Input Voltage V Input Voltage Hysteresis mv Low Level Input Current V IN = 0V µa High Level Input Current V IN = 5V µa GATE DRIVER OUTPUT PINS:, BHO, AND CHO Average Turn-On Current V OUT 0V to 5V ma Average Turn-Off Current V OUT V DD to V ma 5

6 HIP0 Switching Specifications V DD = V xhb = V, V SS = V xhs = 0V, C GATE = 000pF T J = 5 C T JS = -0 C TO 50 C PARAMETER TEST CONDITIONS MIN TYP MAX MIN MAX UNITS Turn-Off Propagation Delay (xhi - xho) No Load ns Turn-On Propagation Delay (xhi - xho) No Load ns Rise Time (0-90%) C GATE = 000pF ns Fall Time (90-0%) C GATE = 000pF ns Disable Turn-Off Propagation Delay No Load ns Disable to Output Enable (DIS - xho) No Load ns Typical Performance Curves.0.5 V DD SUPPLY CURRENT (ma).... V DD = V V DD = 0V V DD = V V DD = V V DD = 5V V DD = V V DD SUPPLY CURRENT (ma) kHz 50kHz 0kHz 0kHz 00kHz.0 FIGURE. V DD SUPPLY CURRENT vs V DD SUPPLY VOLTAGE.0 FIGURE. V DD SUPPLY CURRENT vs SWITNG FREQUENCY xhb SUPPLY OFF CURRENT (µa) (V XHB - V XHS ) = 0V (V XHB - V XHS ) = V (V XHB - V XHS ) = V (V XHB - V XHS ) = 5V (V XHB - V XHS ) = V (V XHB - V XHS ) = V (V XHB - V XHS ) = V xhb ON SUPPLY CURRENT (µa) (V XHB - V XHS ) = V (V XHB - V XHS ) = 0V (V XHB - V XHS ) = V (V XHB - V XHS ) = V (V XHB - V XHS ) = 5V 50 FIGURE. FLOATING SUPPLY OFF BIAS CURRENT 0 FIGURE. FLOATING SUPPLY ON BIAS CURRENT

7 HIP0 Typical Performance Curves (Continued) xhb SUPPLY CURRENT (ma) 00kHz 00kHz 50kHz 0kHz 0kHz C GATE = 000pF xhb SUPPLY CURRENT (ma) kHz 00kHz 50kHz 0kHz 0kHz NO LOAD 0 FIGURE 5. FLOATING SUPPLY SWITNG BIAS CURRENT 0 FIGURE. FLOATING SUPPLY SWITNG BIAS CURRENT UNDERVOLTAGE SHUTDOWN/ENABLE VOLTAGE (V) 0 9 ENABLE (50K, UVLO TO GND) 5 TRIP (50K, UVLO TO GND) ENABLE (UVLO OPEN) TRIP (UVLO OPEN) TRIP/ENABLE (OK, UVLO TO V DD ) FIGURE. UNDERVOLTAGE THRESHOLD PROPAGATION DELAY (ns) DISABLE TURN-OFF ENABLE TURN-ON TURN-ON 0 FIGURE. PROPAGATION DELAY TURN-OFF RISE AND FALL TIME (ns) C GATE = 000pF TURN-ON TURN-OFF AVERAGE TURN-ON CURRENT (A) V V 0V V V 0V TO 5V 0 FIGURE 9. RISE AND FALL TIME (0-90%) 0. FIGURE 0. GATE DRIVER AVERAGE TURN-ON CURRENT

8 HIP0 Typical Performance Curves (Continued) AVERAGE TURN-OFF CURRENT (A) V 0V V V 5V V DD TO V xhs LEAKAGE CURRENT (µa) FIGURE. GATE DRIVER AVERAGE TURN-OFF CURRENT 0 FIGURE. HIGH VOLTAGE LEAKAGE CURRENT

9 HIP0 Dual-In-Line Plastic Packages (PDIP) INDEX AREA BASE PLANE SEATING PLANE D B N N/ B D e D -C- -A- NOTES:. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control.. Dimensioning and tolerancing per ANSI Y.5M-9.. Symbols are defined in the MO Series Symbol List in Section. of Publication No Dimensions A, A and L are measured with the package seated in JEDEC seating plane gauge GS-. 5. D, D, and E dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.00 inch (0.5mm).. E and e A are measured with the leads constrained to be perpendicular to datum -C-.. e B and e C are measured at the lead tips with the leads unconstrained. e C must be zero or greater.. B maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.00 inch (0.5mm). 9. N is the maximum number of terminal positions. 0. Corner leads (, N, N/ and N/ + ) for E., E., E., E., E. will have a B dimension of inch (0. -.mm). E -B- A 0.00 (0.5) M C A A L B S A e C E C L e A e B C E. (JEDEC MS-00-BB ISSUE D) LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A A B B , 0 C D D E E e 0.00 BSC.5 BSC - e A 0.00 BSC. BSC e B L N 9 Rev. 0 /9 9

10 HIP0 N Small Outline Plastic Packages (SOIC) INDEX AREA e D B 0.5(0.00) M C A M E -B- -A- -C- SEATING PLANE A B S H A µ 0.5(0.00) M B α 0.0(0.00) L M h x 5 o C M.5 (JEDEC MS-0-AC ISSUE C) LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A B C D E e BSC. BSC - H h L N α 0 o o 0 o o - Rev. 0/0 NOTES:. Symbols are defined in the MO Series Symbol List in Section. of Publication Number 95.. Dimensioning and tolerancing per ANSI Y.5M-9.. Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.5mm (0.00 inch) per side.. Dimension E does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.5mm (0.00 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area.. L is the length of terminal for soldering to a substrate.. N is the number of terminal positions.. Terminal numbers are shown for reference only. 9. The lead width B, as measured 0.mm (0.0 inch) or greater above the seating plane, shall not exceed a maximum value of 0.mm (0.0 inch) 0. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation s quality certifications can be viewed at Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see 0