DATASHEET HI-1818A. Features. Applications. Ordering Information. Pinout. Low Resistance, Single 8-Channel, CMOS Analog Multiplexer

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1 NOT RECOMMDED FOR NEW DESIGNS NO RECOMMDED REPLACEMT contact our Technical Support Center at INTERSIL or Low Resistance, Single 8-Channel, CMOS Analog Multiplexer DATASHEET FN3141 Rev 4.00 The Hl-1818A is a monolithic, high performance CMOS analog multiplexer offering built-in channel selection decoding plus an inhibit (enable) input for disabling all channels. Dielectric Isolation (Dl) processing is used for enhanced reliability and performance. Substrate leakage and parasitic capacitance are much lower, resulting in extremely low static errors and high throughput rates. Low output leakage (typically 0.1nA) and low channel ON resistance (250) assure optimum performance in low level or current mode applications. The is a single-ended, 8-Channel multiplexer, and is ideally suited for medical instrumentation, telemetry systems, and microprocessor based data acquisition systems. Features Signal Range V ON Resistance Input Leakage (Max) nA Access Time ns Power Consumption mW DTL/TTL Compatible Address Operation o C to 125 o C Applications Data Acquisition Systems Precision Instrumentation Demultiplexing Selector Switch Ordering Information PART NUMBER TEMP. RANGE ( o C) PACKAGE PKG. DWG. # HI1-1818A-2-55 to Ld CERDIP F16.3 Pinout (CERDIP) TOP VIEW A A 0 +5V SUPPLY V SUPPLY ABLE V SUPPLY A IN IN IN 2 IN IN 3 IN IN 4 FN3141 Rev 4.00 Page 1 of 8

2 Truth Table TRUTH TABLE A 2 A 1 A 0 ON CHANNEL L L L L 1 L L H L 2 L H L L 3 L H H L 4 H L L L 5 TRUTH TABLE A 2 A 1 A 0 ON CHANNEL H L H L 6 H H L L 7 H H H L 8 X X X H None Functional Block Diagram DIGITAL A 0 A 1 A 2 ABLE INPUT BUFFERS ABLE BUFFER MULTIPLEX SWITCHES DECODERS N P IN 8 N P Schematic Diagrams INPUT BUFFER P3 P1 P5 V+ N1 V CC P4 All N-Channel Bodies to V- All P-Channel Bodies to V+ Unless Otherwise Specified INPUT D1 200 D2 V- P2 N2 N4 P6 N6 N5 P7 N7 P8 N8 P9 N9 P10 N10 A A N3 V- FN3141 Rev 4.00 Page 2 of 8

3 Schematic Diagrams DECODER V+ All N-Channel Bodies to V- All P-Channel Bodies to V+ A2 OR A2 N11 A1 OR A1 N12 A0 OR A0 N13 P11 P12 P13 P14 N14 P15 N15 P16 N16 TO P-CHANNEL SWITCH TO N-CHANNEL SWITCH V- IN SWITCH CELL MULTIPLEXER SWITCH FROM DECODE N18 All N-Channel Bodies to V- All P-Channel Bodies to V+ Unless Otherwise Specified IN V+ N19 N17 P17 P18 V+ FROM DECODE FN3141 Rev 4.00 Page 3 of 8

4 Absolute Maximum Ratings V+ to V V Logic Supply Voltage V Analog Signal (V IN, V ) (V-) -2V to (V+) +2V Digital Input Voltage (V, V A ) (V-) to (V+) Operating Conditions Temperature Range o C to 125 o C Thermal Information Thermal Resistance (Typical, Note 1) JA ( o C/W) JC ( o C/W) CERDIP Package Maximum Junction Temperature Ceramic Package o C Maximum Storage Temperature Range o C to 150 o C Maximum Lead Temperature (Soldering 10s) o C CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief 379 for details. Electrical Specifications Supplies = +15V, -15V, +5V; V AL = 0.4V, V AH = 4.0V, Unless Otherwise Specified PARAMETER TEST CONDITIONS TEMP ( o C) MIN TYP MAX UNITS DYNAMIC CHARACTERISTICS Access Time, t A Note ns Full ns Break-Before-Make Delay, t OP ns Enable Delay (ON), t ON() ns Full ns Enable Delay (OFF), t OFF() ns Full ns Settling Time To 0.1% s To 0.025% s Channel Input Capacitance, C S(OFF) pf Channel Output Capacitance, C D(OFF) pf Input to Output Capacitance, C DS(OFF) pf Digital Input Capacitance, C A pf DIGITAL INPUT CHARACTERISTICS Input Low Threshold, V AL Full V Input High Threshold, V AH Note 3 Full V Input Leakage Current, I A Full A ANALOG CHANNEL CHARACTERISTICS Analog Signal Range, V ln Full V ON Resistance, r ON Note Full OFF Input Leakage Current, I S(OFF) Full na ON Channel Leakage Current, l D(ON) Full na OFF Output Leakage Current, I D(OFF) Full na FN3141 Rev 4.00 Page 4 of 8

5 Electrical Specifications PARAMETER TEST CONDITIONS TEMP ( o C) MIN TYP MAX UNITS POWER SUPPLY CHARACTERISTICS Power Dissipation, P D Full mw Current, I+ Full ma Current, I- Full ma Current, I L Full ma NOTES: 2. V = 10V, I = 1mA. Supplies = +15V, -15V, +5V; V AL = 0.4V, V AH = 4.0V, Unless Otherwise Specified (Continued) 3. To drive from DTL/TTL circuits, 1k pull-up resistors to 5.0V supply are recommended. 4. Time measured to 90% of final output level; V = -5.0V to 5.0V, Digital Inputs = 0V to 4.0V. Test Circuits and Waveforms +15V -15V +5V V AH = 4.0V A 2 A 1 V+ V- V L +5V ABLE DRIVE 2V/DIV. 50% ABLE DRIVE V AL = 0V (V A ) t ON 90% PUT () 10% V A 50 A 0 IN pf DISABLED ABLED (S 1 ON) PUT 2V/DIV. t OFF () 100ns/DIV. FIGURE 1A. MEASUREMT POINTS FIGURE 1B. TEST CIRCUIT FIGURE 1. ABLE DELAYS FIGURE 1C. WAVEFORMS +15V -15V +5V 0V 50% 4.0V 50% DRIVE (V A ) PUT V A 50 A 2 A 1 A 0 V+ V- V L IN 2 IN V pf S 1 ON V A INPUT 2V/DIV. S 2 ON PUT 1V/DIV. t OP 100ns/DIV. FIGURE 2A. MEASUREMT POINTS FIGURE 2B. TEST CIRCUIT FIGURE 2. BREAK-BEFORE-MAKE DELAY FIGURE 2C. WAVEFORMS FN3141 Rev 4.00 Page 5 of 8

6 1mA V 2 V IN IN R ON = V 2 1mA V A ON RESISTANCE () o C 25 o C -55 o C SWITCH CURRT (ma) o C 25 o C -55 o C 125 o C ANALOG INPUT (V) 25 o C -55 o C VOLTAGE ACROSS SWITCH (V) FIGURE 3. ON RESISTANCE vs ANALOG INPUT VOLTAGE FIGURE 4. ON CHANNEL CURRT vs VOLTAGE OFF LEAKAGE ON LEAKAGE ACCESS TIME TEST CIRCUIT 10V 4V A I D(OFF) 10V 10V A A 0 A 1 0.4V I D(ON) 10V +5V IN 2-5V IN 3-8 A 0 A 1 A 2 10 k 50pF I S(OFF) 10V A 10V 4V NOTE: Two measurements per channel: 10V and 10V Two measurements per device for I D(OFF) : 10V and 10V 0V TO 4V nA 4V 10nA I D(ON) - I D(OFF) 50% A 0 INPUT 2V/DIV. 1nA I S(OFF) +5V 100pA 10% PUT 5V/DIV. -5V 10pA TEMPERATURE ( o C) t A 100ns/DIV. FIGURE 5. LEAKAGE CURRTS vs TEMPERATURE FIGURE 6. ACCESS TIME FN3141 Rev 4.00 Page 6 of 8

7 Die Characteristics METALLIZATION: Type: CuAl Thickness: 16kÅ 2kÅ PASSIVATION: Type: Nitride/Silox Thickness: Silox: 12kÅ 2kÅ, Nitride: 3.5kÅ 1kÅ WORST CASE CURRT DSITY: 1.43 x 10 5 A/cm 2 at 25mA Metallization Mask Layout V L A 1 A 0 -V SUPPLY A 2 +V SUPPLY IN 8 PUT IN 7 IN 6 IN 5 IN 4 IN 3 IN 2 FN3141 Rev 4.00 Page 7 of 8

8 Ceramic Dual-In-Line Frit Seal Packages (CERDIP) BASE PLANE SEATING PLANE S1 b2 ccc M bbb S b C A - B Q -C- A -B- C A - B S D A A e D S -D- -A- NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer s identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M Controlling dimension: INCH. E L M c1 ea/2 S D S aaa M C A - B LEAD FINISH BASE METAL b1 M (b) SECTION A-A S ea c D S (c) F16.3 MIL-STD-1835 GDIP1-T16 (D-2, CONFIGURATION A) 16 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A b b b b c c D E e BSC 2.54 BSC - ea BSC 7.62 BSC - ea/ BSC 3.81 BSC - L Q S o 105 o 90 o 105 o - aaa bbb ccc M , 3 N Rev. 0 4/94 Copyright Intersil Americas LLC All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see FN3141 Rev 4.00 Page 8 of 8