DATASHEET CA3096, CA3096A, CA3096C. Description. Applications. CA3096, CA3096A, CA3096C Essential Differences. Part Number Information.

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1 DATASHEET CA39, CA39A, CA39C NPN/PNP Transistor Arrays Applications Five-Independent Transistors - Three NPN and - Two PNP Differential Amplifiers DC Amplifiers Sense Amplifiers Level Shifters Timers Lamp and Relay Drivers Thyristor Firing Circuits Temperature Compensated Amplifiers Operational Amplifiers Part Number Information PART NUMBER (BRAND) TEMP. RANGE ( o C) PACKAGE PKG. NO. CA39AE - to Ld PDIP E.3 CA39AM (39A) - to Ld SOIC M. CA39AM9 (39A) Pinout - to Ld SOIC Tape and Reel CA39, CA39A, CA39C (PDIP, SOIC) TOP VIEW M. CA39CE - to Ld PDIP E.3 CA39E - to Ld PDIP E.3 CA39M (39) - to Ld SOIC M. CA39M9 (39) 3 - to Ld SOIC Tape and Reel Q Q Q 3 Q Q 3 9 SUBSTRATE M. Description FN9 Rev.. January The CA39C, CA39, and CA39A are general purpose high voltage silicon transistor arrays. Each array consists of five independent transistors (two PNP and three NPN types) on a common substrate, which has a separate connection. Independent connections for each transistor permit maximum flexibility in circuit design. Types CA39A, CA39, and CA39C are identical, except that the CA39A specifications include parameter matching and greater stringency in I CBO, I CEO, and V CE (SAT). The CA39C is a relaxed version of the CA39. CA39, CA39A, CA39C Essential Differences CHARACTERISTIC CA39A CA39 CA39C V (BR)CEO (V) (Min) NPN 3 3 PNP V (BR)CBO (V) (Min) NPN 3 PNP h FE at ma NPN PNP h FE at A PNP I CBO (na) (Max) NPN PNP I CEO (na) (Max) NPN PNP V CE SAT (V) (Max) NPN... V IO (mv) (Max) NPN - - PNP - - I IO ( A) (Max) NPN. - - PNP. - - FN9 Rev.. Page of January

2 CA39, CA39A, CA39C Absolute Maximum Ratings NPN PNP Collector-to-Emitter Voltage, V CEO CA39, CA39A V -V CA39C V -V Collector-to-Base Voltage, V CBO CA39, CA39A V -V CA39C V -V Collector-to-Substrate Voltage, V CIO (Note ) CA39, CA39A V - CA39C V - Emitter-to-Substrate Voltage, V EIO CA39, CA39A V CA39C V Emitter-to-Base Voltage, V EBO CA39, CA39A V -V CA39C V -V Collector Current, I C (All Types) ma -ma Temperature Range o C to o C Operating Conditions Thermal Information Thermal Resistance (Typical, Note ) JA ( o C/W) PDIP Package SOIC Package Maximum Power Dissipation (Each Transistor, Note 3)......mW Maximum Junction Temperature (Plastic Package) o C Maximum Storage Temperature Range o C to o C Maximum Lead Temperature (Soldering s) o C (SOIC - Lead Tips Only) CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES:. The collector of each transistor of the CA39 is isolated from the substrate by an integral diode. The substrate (Terminal ) must be connected to the most negative point in the external circuit to maintain isolation between transistors and to provide for normal transistor action.. JA is measured with the component mounted on an evaluation PC board in free air. 3. Care must be taken to avoid exceeding the maximum junction temperature. Use the total power dissipation (all transistors) and thermal resistances to calculate the junction temperature. Electrical Specifications For Equipment Design, At T A = o C TEST CA39 CA39A CA39C PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS DC CHARACTERISTICS FOR EACH NPN TRANSISTOR I CBO V CB = V, I E = na I CEO V CE = V, I B = na V (BR)CEO I C = ma, I B = V V (BR)CBO I C = A, V I E = V (BR)CIO V (BR)EBO I CI = A, I B = I E = I E = A, I C = V V V Z I Z = A V V CE SAT l C = ma, V I B = ma V BE (Note ) I C = ma, V h FE (Note ) V BE / T (Note ) I C = ma, mv/ o C DC CHARACTERISTICS FOR EACH PNP TRANSISTOR I CBO V CB = -V, I E = na I CEO V CE = -V, I B = na FN9 Rev.. Page of January

3 CA39, CA39A, CA39C Electrical Specifications For Equipment Design, At T A = o C (Continued) PARAMETER V (BR)CEO V (BR)CBO V (BR)EBO V (BR)ElO V CE SAT V BE (Note ) h FE (Note ) V BE / T (Note ) TEST CONDITIONS I C = - A, I B = I C = - A, I E = I E = - A, I C = I EI = A, I B = I C = I C = -ma, I B = - A I C = - A, V CE = -V I C = - A, V CE = -V I C = -ma, V CE = -V I C = - A, V CE = -V V V V V V V mv/ o C I CBO Collector-Cutoff Current V Z Emitter-to-Base Zener Voltage I CEO Collector-Cutoff Current V CE SAT Collector-to-Emitter Saturation Voltage V (BR)CEO Collector-to-Emitter Breakdown Voltage V BE Base-to-Emitter Voltage V (BR)CBO Collector-to-Base Breakdown Voltage h FE DC Forward-Current Transfer Ratio V (BR)CIO Collector-to-Substrate Breakdown Voltage V BE / T Magnitude of Temperature Coefficient: V (BR)EBO Emitter-to-Base Breakdown Voltage (for each transistor) NOTE:. Actual forcing current is via the emitter for this test. CA39 CA39A CA39C MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS Electrical Specifications For Equipment Design At T A = o C (CA39A Only) PARAMETER SYMBOL TEST CONDITIONS FOR TRANSISTORS Q AND Q (AS A DIFFERENTIAL AMPLIFIER) CA39A MIN TYP MAX UNITS Absolute Input Offset Voltage V IO, I C = ma -.3 mv Absolute Input Offset Current I IO -.. A Absolute Input Offset Voltage Temperature Coefficient V IO T -. - V/ o C FOR TRANSISTORS Q AND Q (AS A DIFFERENTIAL AMPLIFIER) Absolute Input Offset Voltage V IO V CE = -V, I C = - A -. mv R S = Absolute Input Offset Current I IO - na Absolute Input Offset Voltage Temperature Coefficient V IO T -. - V/ o C FN9 Rev.. Page 3 of January

4 CA39, CA39A, CA39C Electrical Specifications Typical Values Intended Only for Design Guidance At T A = o C PARAMETER SYMBOL TEST CONDITIONS DYNAMIC CHARACTERISTICS FOR EACH NPN TRANSISTOR TYPICAL VALUES UNITS Noise Figure (Low Frequency) NF f = khz,, I C = ma, R S = k. db Low-Frequency, Input Resistance R I f =.khz, I C = ma k Low-Frequency Output Resistance R O f =.khz, I C = ma k Admittance Characteristics Forward Transfer Admittance Input Admittance Output Admittance g FE f = MHz,, I C = ma. ms y FE b FE f = MHz,, I C = ma -j3 ms g IE f = MHz,, I C = ma. ms y IE b IE f = MHz,, I C = ma j3. ms y g OE f = MHz,, I C = ma. ms OE b OE f = MHz,, I C = ma j. ms Gain-Bandwidth Product f T, I C =.ma MHz, I C = ma 33 MHz Emitter-To-Base Capacitance C EB V EB = 3V. pf Collector-To-Base Capacitance C CB V CB = 3V. pf Collector-To-Substrate Capacitance C CI V CI = 3V 3. pf DYNAMIC CHARACTERISTICS FOR EACH PNP TRANSISTOR Noise Figure (Low Frequency) NF f = khz, I C = A, R S = k 3 db Low-Frequency Input Resistance R I f = khz,, I C = A k Low-Frequency Output Resistance R O f = khz,, I C = A k Gain-Bandwidth Product f T, I C = A. MHz Emitter-To-Base Capacitance C EB V EB = -3V. pf Collector-To-Base Capacitance C CB V CB = -3V. pf Base-To-Substrate Capacitance C BI V BI = 3V 3. pf Typical Applications f 3k. F Q 3 k Q V+ = V 3k 3 k. F 9 f Q 3 NOTE: F OR F < khz (SUBSTRATE) F OUTPUT OUTPUT VOLTAGE (V) 9 3 CENTER FREQUENCY: khz - - f - f > f = f f - f > FREQUENCY DEVIATION (khz) FIGURE. FREQUENCY COMPARATOR USING CA39 FIGURE. FREQUENCY COMPARATOR CHARACTERISTICS FN9 Rev.. Page of January

5 CA39, CA39A, CA39C Typical Applications (Continued) 3 V AC Q F V + - NTC SENSOR k 3 Q Q k.k k G MT MT T3B.k W Q 3 9 R P.k k Q LOAD FIGURE 3. LINE-OPERATED LEVEL SWITCH USING CA39A OR CA39 +V 3 Q MOSFET k k k Q k 3 Q Q k 9 Q 3 OUTPUT M F k 3.9k k TIME DELAY CHANGES % FOR SUPPLY VOLTAGE CHANGE OF % FIGURE. ONE-MINUTE TIMER USING CA39A AND A MOSFET FN9 Rev.. Page of January

6 CA39, CA39A, CA39C Typical Applications (Continued) V+ 3 V T = I R O L IF I O = ma AND R L = k V T = 3mV V IN k Q 3 Q R L k Q 3 Q k EO +V T V IN -V T E O t k 9 I O Q 3 k V- t FIGURE. CA39A SMALL-SIGNAL ZERO VOLTAGE DETECTOR HAVING NOISE IMMUNITY 3.V LAMP GE D OR EQUIVALENT Q Q k k 9 Q 3.M 3 Q Q k F k k (SUBSTRATE) FIGURE. TEN-SECOND TIMER OPERATED FROM.V SUPPLY USING CA39 FN9 Rev.. Page of January

7 CA39, CA39A, CA39C Typical Applications (Continued) +V k %.k %.k % OUTPUT INPUT k % Q 3 3 Q Q Q k % Q 3 9 NOTES:. Can be operated with either dual supply or single supply.. Wide-input common mode range +V to -V.. Low bias current: < A. k % k % k % 3 % k % -V FIGURE. CASCADE OF DIFFERENTIAL AMPLIFIERS USING CA39A VOLTAGE GAIN (db) 3 FIGURE. FREQUENCY RESPONSE FN9 Rev.. Page of January

8 CA39, CA39A, CA39C Typical Performance Curves ZENER CURRENT (ma) - V Z COLLECTOR CUT-OFF CURRENT (pa) 3 V CE = V ZENER VOLTAGE (V) TEMPERATURE ( o C) FIGURE 9. BASE-TO-EMITTER ZENER CHARACTERISTIC (NPN) FIGURE. COLLECTOR CUT-OFF CURRENT (I CEO ) vs TEMPERATURE (NPN) COLLECTOR CUT-OFF CURRENT (pa) 3 V CB = V V CB = V V CB = V TEMPERATURE ( o C) DC FORWARD CURRENT TRANSFER RATIO 3 T A = o C T A = o C T A = - o C.. FIGURE. COLLECTOR CUT-OFF CURRENT (I CBO ) vs TEMPERATURE (NPN) FIGURE. TRANSISTOR (NPN) h FE vs COLLECTOR CURRENT.9 BASE TO EMITTER VOLTAGE (V).... BASE TO EMITTER VOLTAGE (V) I C = ma,.mv/ o C I C = ma,.mv/ o C I C = ma,.9mv/ o C I C = A,.mV/ o C TEMPERATURE ( o C) FIGURE 3. V BE (NPN) vs COLLECTOR CURRENT FIGURE. V BE (NPN) vs TEMPERATURE FN9 Rev.. Page of January

9 CA39, CA39A, CA39C Typical Performance Curves (Continued) COLLECTOR TO EMITTER SATURATION VOLTAGE (V)..... T A = o C T A = o C = T A = - o C... COLLECTOR CUT-OFF CURRENT (pa) V CE = -V 3 V CE = -V V CE = -V - - TEMPERATURE ( o C) FIGURE. V CE SAT (NPN) vs COLLECTOR CURRENT FIGURE. COLLECTOR CUT-OFF CURRENT (I CEO ) vs TEMPERATURE (PNP) COLLECTOR CUT-OFF CURRENT (pa) 3 V CB = -V V CB = -V V CB = -V - - TEMPERATURE ( o C) DC FORWARD CURRENT TRANSFER RATIO 9 V CE = V V CE = V 3... FIGURE. COLLECTOR CUT-OFF CURRENT (I CBO ) vs TEMPERATURE (PNP) FIGURE. TRANSISTOR (PNP) h FE vs COLLECTOR CURRENT DC FORWARD CURRENT TRANSFER RATIO I C = A I C = A I C = ma I C = ma - - TEMPERATURE ( o C) BASE TO EMITTER VOLTAGE (V) FIGURE 9. TRANSISTOR (PNP) h FE vs TEMPERATURE FIGURE. V BE (PNP) vs COLLECTOR CURRENT FN9 Rev.. Page 9 of January

10 CA39, CA39A, CA39C Typical Performance Curves (Continued) BASE TO EMITTER VOLTAGE (V) I C = A, -.mv/ o C I C = ma, V BE / T -.9mV/ o C I C = ma, -.mv/ o C. - - TEMPERATURE ( o C) MAGNITUDE OF INPUT OFFSET VOLTAGE (mv) FIGURE. V BE (PNP) vs TEMPERATURE FIGURE. MAGNITUDE OF INPUT OFFSET VOLTAGE V IO vs COLLECTOR CURRENT FOR NPN TRANSISTOR Q - Q MAGNITUDE OF INPUT OFFSET VOLTAGE (mv) NOISE FIGURE (db) R SOURCE = I C = 3mA ma A A... FIGURE 3. MAGNITUDE OF INPUT OFFSET VOLTAGE V IO vs COLLECTOR CURRENT FOR PNP TRANSISTOR Q - Q FIGURE. NOISE FIGURE vs FREQUENCY FOR NPN TRANSISTORS NOISE FIGURE (db) I C = 3mA ma A R SOURCE = k NOISE FIGURE (db) R SOURCE = k I C = 3mA ma A A A.. FIGURE. NOISE FIGURE vs FREQUENCY FOR NPN TRANSISTORS... FIGURE. NOISE FIGURE vs FREQUENCY FOR NPN TRANSISTORS FN9 Rev.. Page of January

11 CA39, CA39A, CA39C Typical Performance Curves (Continued) NOISE FIGURE (db) A A I C = ma R SOURCE = k R SOURCE = M A GAIN-BANDWIDTH PRODUCT (MHz) 3 A.... FIGURE. NOISE FIGURE vs FREQUENCY FOR NPN TRANSISTORS FIGURE. GAIN-BANDWIDTH PRODUCT vs COLLECTOR CUR- RENT (NPN). 3. f = khz CAPACITANCE (pf) C EB C CI INPUT RESISTANCE (k ) PNP NPN C CB. 3 9 BIAS VOLTAGE (V) FIGURE 9. CAPACITANCE vs BIAS VOLTAGE (NPN).. FIGURE 3. INPUT RESISTANCE vs COLLECTOR CURRENT OUTPUT RESISTANCE (k ) f = khz 3 NPN PNP... FORWARD TRANSFER CONDUCTANCE (g FE ) OR FORWARD TRANSFER SUSCEPTANCE (b FE ) (ms) g FE b FE I C = ma ma g FE b FE A A FREQUENCY (MHz) FIGURE 3. OUTPUT RESISTANCE vs COLLECTOR CURRENT FIGURE 3. FORWARD TRANSCONDUCTANCE vs FREQUENCY FN9 Rev.. Page of January

12 CA39, CA39A, CA39C Typical Performance Curves (Continued) g IE INPUT CONDUCTANCE (g IE ) OR INPUT SUSCEPTANCE (b IE ) (ms) 3 b IE A A ma I C = ma ma ma A A FREQUENCY (MHz) OUTPUT CONDUCTANCE (g OE ) OR OUTPUT SUSCEPTANCE (b OE ) (ms)..... A b OE I C = ma b OE A g OE ma g OE FREQUENCY (MHz) FIGURE 33. INPUT ADMITTANCE vs FREQUENCY FIGURE 3. OUTPUT ADMITTANCE vs FREQUENCY 3 RSOURCE = 3 R SOURCE = k NOISE FIGURE (db) A A I C = ma NOISE FIGURE (db) A A I C = ma... FIGURE 3. NOISE FIGURE vs FREQUENCY (PNP).. FIGURE 3. NOISE FIGURE vs FREQUENCY (PNP) R SOURCE = k NOISE FIGURE (db) 3 A A I C = ma GAIN-BANDWIDTH PRODUCT (MHz)... FIGURE 3. NOISE FIGURE vs FREQUENCY (PNP).. FIGURE 3. GAIN-BANDWIDTH PRODUCT vs COLLECTOR CUR- RENT (PNP) FN9 Rev.. Page of January

13 CA39, CA39A, CA39C Typical Performance Curves (Continued) CAPACITANCE (pf) 3 C BC C BI C BE 3 9 BIAS VOLTAGE (V) Metallization Mask Layout FIGURE 39. CAPACITANCE vs BIAS VOLTAGE (PNP) CA39H (.9-.3) Dimensions in parentheses are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils ( -3 inch). The photographs and dimensions represent a chip when it is part of the wafer. When the wafer is cut into chips, the cleavage angles are degrees instead of 9 degrees with respect to the face of the chip. Therefore, the isolated chip is actually mils (.mm) larger in both dimensions. - (.-.) 3- (.9-.3) FN9 Rev.. Page 3 of January

14 CA39, CA39A, CA39C Dual-In-Line Plastic Packages (PDIP) BASE PLANE SEATING PLANE D B B D e D -C- A. (.) M C A NOTES:. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control.. Dimensioning and tolerancing per ANSI Y.M Symbols are defined in the MO Series Symbol List in Section. of Publication No. 9.. Dimensions A, A and L are measured with the package seated in JE- DEC seating plane gauge GS-3.. D, D, and E dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed. inch (.mm).. E and e A are measured with the leads constrained to be perpendicular to datum -C-.. e B and e C are measured at the lead tips with the leads unconstrained. e C must be zero or greater.. B maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed. inch (.mm). 9. N is the maximum number of terminal positions.. Corner leads (, N, N/ and N/ + ) for E.3, E.3, E.3, E.3, E. will have a B dimension of.3 -. inch (. -.mm). A L B S A e C E C L e A e B C E.3 (JEDEC MS--BB ISSUE D) LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A A B B...., C D D E E.... e. BSC. BSC - e A.3 BSC. BSC e B L N 9 Rev. /93 FN9 Rev.. Page of January

15 CA39, CA39A, CA39C Small Outline Plastic Packages (SOIC) N INDEX AREA 3 e D B.(.) M C A M E -B- -A- -C- SEATING PLANE A B S H A µ.(.) M B.(.) L M h x o NOTES:. Symbols are defined in the MO Series Symbol List in Section. of Publication Number 9.. Dimensioning and tolerancing per ANSI Y.M Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed.mm (. inch) per side.. Dimension E does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed.mm (. inch) per side.. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area.. L is the length of terminal for soldering to a substrate.. N is the number of terminal positions.. Terminal numbers are shown for reference only. 9. The lead width B, as measured.3mm (. inch) or greater above the seating plane, shall not exceed a maximum value of.mm (. inch).. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. C M. (JEDEC MS--AC ISSUE C) LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A B C D E e. BSC. BSC - H h L.... N o o o o - Rev. /93 Copyright Intersil Americas LLC. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see Intersil products are manufactured, assembled and tested utilizing ISO9 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see FN9 Rev.. Page of January