DATASHEET. Features. Applications. Pin Configurations HS-139RH, HS-139EH. Radiation Hardened Quad Voltage Comparator. FN3573 Rev 6.

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1 DTSHEET Radiation Hardened Quad Voltage Comparator The Radiation Hardened consists of four independent single or dual supply voltage comparators on a single monolithic substrate. The common mode input voltage range includes ground, even when operated from a single supply and the low supply current makes these comparators suitable for low power applications. These types were designed to directly interface with TTL and COS. The are fabricated on our dielectrically isolated Rad Hard Silicon Gate (RSG) process, which provides an immunity to Single Event Latch-up and the capability of highly reliable performance in any radiation environment. Specifications for Rad Hard QL devices are controlled by the Defense Logistics gency Land and aritime (DL). The SD numbers listed below must be used when ordering. Detailed Electrical Specifications for the are contained in SD hot-link is provided on our homepage with instructions for downloading. Features FN3573 Rev 6.00 QL qualified per IL-PRF requirements Radiation environment - Latch-up free under any conditions - Total dose (ax) x 10 5 RD(Si) - SEU LET threshold eV/cm 2 /mg - Low dose rate effects immunity 100V output voltage withstand capability ESD protection to >3000V Differential input voltage range equal to the supply voltage Input offset voltage (V IO ) mV (ax) Quiescent supply current m (ax) Pb-Free (RoHS Compliant) pplications Pulse generators Timing circuitry Level shifting nalog-to-digital conversion Pin Configurations (SBDIP CDIP2-T14) TOP VIEW (FLTPCK CDFP3-F14) TOP VIEW OUT OUT 3 OUT OUT 3 OUT OUT 4 OUT OUT 4 V GND V GND - IN 1 + IN 1 - IN IN 4 - IN 4 + IN 3 - IN 1 + IN 1 - IN 2 +IN IN 4 - IN 4 + IN 3 - IN 3 + IN IN 3 FN3573 Rev 6.00 Page 1 of 6

2 Ordering Information ORDERING SD NUBER (Note 1) PRT NUBER (Note 2) PRT RKING TEP. RNGE ( C) PCKGE (RoHS Compliant) PKG. DWG. # 5962F VCC HS1-139EH-Q Q 5962F VCC -55 to Ld SBDIP D F VCC HS1-139RH-Q Q 5962F VCC -55 to Ld SBDIP D F QCC HS1-139RH-8 Q 5962F QCC -55 to Ld SBDIP D14.3 HS1-139RH/PROTO HS1-139RH/PROTO HS1-139RH/PROTO -55 to Ld SBDIP D F VXC HS9-139RH-Q Q 5962F VXC -55 to Ld FLTPCK K F QXC HS9-139RH-8 Q 5962F QXC -55 to Ld FLTPCK K F VXC HS9-139EH-Q Q 5962F VXC -55 to Ld FLTPCK K14. HS9-139RH/PROTO HS9-139RH/PROTO HS9-139RH /PROTO -55 to Ld FLTPCK K F V9 HS0-139EH-Q -55 to +125 Die 5962F V9 HS0-139RH-Q -55 to +125 Die HS0-139RH/SPLE HS0-139RH/SPLE -55 to +125 Die NOTES: 1. Specifications for Rad Hard QL devices are controlled by the Defense Logistics gency Land and aritime (DL). The SD numbers listed in the Ordering Information table on page 2 must be used when ordering. 2. These Intersil Pb-free Hermetic packaged products employ 100% u plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. FN3573 Rev 6.00 Page 2 of 6

3 Die Characteristics DIE DIENSIONS: 3750µm x 2820µm (148 mils x 111 mils) 483µm ±25.4µm (19 mils ±1 mil) INTERFCE TERILS: Glassivation: Type: Silox (SiO 2 ) Thickness: 8.0kÅ ±1.0kÅ Top etallization: Type: lsicu Thickness: 16.0kÅ ±2kÅ etallization ask Layout Substrate: Radiation Hardened Silicon Gate, Dielectric Isolation Backside Finish: Silicon SSEBLY RELTED INFORTION: Substrate Potential: Unbiased (DI) DDITIONL INFORTION: Worst Case Current Density: <2.0 x 10 5 /cm 2 Transistor Count: 49 GND +IN4 -IN4 (12) (11) (10) OUT4 (13) +IN3 (9) OUT3 (14) -IN3 (8) +IN2 (7) OUT2 (1) -IN2 (6) OUT1 (2) V+ -IN1 +IN1 (3) (4) (5) FN3573 Rev 6.00 Page 3 of 6

4 PIN NUBER TBLE 1. PD COORDINTES PD NE X COORDINTES RELTIVE TO PIN 1 Y COORDINTES 1 OUT OUT V IN IN IN IN IN IN IN IN GND OUT OUT NOTE: Dimensions in microns Copyright Intersil mericas LLC ll Rights Reserved. ll trademarks and registered trademarks are the property of their respective owners. For additional products, see Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. ccordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see FN3573 Rev 6.00 Page 4 of 6

5 Ceramic Dual-In-Line etal Seal Packages (SBDIP) BSE PLNE SETING PLNE S1 b2 ccc NOTES: bbb S b C - B S C - B 3. Index area: notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer s identification shall not be used as a pin one identification mark. 4. The maximum limits of lead dimensions b and c or shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 5. Dimensions b1 and c1 apply to lead base metal only. Dimension applies to lead plating and finish thickness. 6. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 7. Dimension Q shall be measured from the seating plane to the base plane. 8. easure dimension S1 at all four corners. 9. easure dimension S2 from the top of the ceramic body to the nearest metallization or lead. 10. N is the maximum number of terminal positions. 11. Braze fillets shall be concave. 12. Dimensioning and tolerancing per NSI Y Controlling dimension: INCH. D e S E c1 L e/2 LED FINISH BSE ETL b1 (b) SECTION - -D- -- S2 Q -C- e -Baaa C - B S c (c) D14.3 IL-STD-1835 CDIP2-T14 (D-1, CONFIGURTION C) 14 LED CERIC DUL-IN-LINE ETL SEL PCKGE SYBOL INCHES ILLIETERS IN X IN X NOTES b b b b c c D E e BSC 2.54 BSC - e BSC 7.62 BSC - e/ BSC 3.81 BSC - L Q S S o 105 o 90 o 105 o - aaa bbb ccc N Rev. 0 4/94 FN3573 Rev 6.00 Page 5 of 6

6 Ceramic etal Seal Flatpack Packages (Flatpack) -Hb e NOTES: H - B Q SETING ND BSE PLNE L 1. Index area: notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer s identification shall not be used as a pin one identification mark. lternately, a tab (dimension k) may be used to identify pin one. 2. If a pin one identification mark is used in addition to a tab, the limits of dimension k do not apply. 3. This dimension allows for off-center lid, meniscus, and glass overrun. 4. Dimensions b1 and c1 apply to lead base metal only. Dimension applies to lead plating and finish thickness. The maximum limits of lead dimensions b and c or shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 5. N is the maximum number of terminal positions. 6. easure dimension S1 at all four corners. c1 S E3 PIN NO. 1 ID RE E1 E E2 LED FINISH BSE ETL b1 (b) SECTION H - B 7. For bottom-brazed lead packages, no organic or polymeric materials shall be molded to the bottom of the package to cover the leads. 8. Dimension Q shall be measured at the point of exit (beyond the meniscus) of the lead from the body. Dimension Q minimum shall be reduced by inch (0.038mm) maximum when solder dip lead finish is applied. 9. Dimensioning and tolerancing per NSI Y Controlling dimension: INCH. E3 (c) L S1 C S -D- -C- -B- D K14. IL-STD-1835 CDFP3-F14 (F-2, CONFIGURTION B) 14 LED CERIC ETL SEL FLTPCK PCKGE INCHES ILLIETERS SYBOL IN X IN X NOTES b b c c D E E E E e BSC 1.27 BSC - k L Q S N Rev. 0 5/18/94 FN3573 Rev 6.00 Page 6 of 6