DATASHEET. Features. Applications. Related Literature ISL70227SRH. 36V Radiation Hardened Dual Precision Operational Amplifier

Transcription

1 V OS (µv) DATASHEET ISL7227SRH 36V Radiation Hardened Dual Precision Operational Amplifier FN792 Rev 2. July 8, 24 The ISL7227SRH is a high precision dual operational amplifier featuring very low noise, low offset voltage, low input bias current and low temperature drift. These features, plus its radiation tolerance, make the ISL7227SRH the ideal choice for applications requiring both high DC accuracy and AC performance. The combination of precision, low noise and small footprint provides the user with outstanding value and flexibility relative to similar competitive parts. Applications for these amplifiers include precision and analytical instrumentation, active filters, precision power supply controls, and industrial controls. The ISL7227SRH is available in a Ld hermetic ceramic flatpack and operates over the extended temperature range of - C to +2 C. Applications Precision Instruments Industrial Controls Active Filter Blocks Data Acquisition Power Supply Control Features Wide supply range V to 36V max. Very low voltage noise nV/ Hz, typ. Gain-bandwidth product MHz Superb offset drift µv/ C, max Operating temperature range C to +2 Low input voltage offset µv, typ. Input bias current na, typ. Unity gain stable No phase reversal Radiation tolerance - High dose rate krad(si) - SEB LET TH (V S = ±8V) MeV/mg/cm 2 - SEL immune (SOI process) Related Literature AN669, ISL7227SRH Evaluation Board User s Guide AN76, Single Events Effects Testing of the ISL7227SRH, Dual 36V Rad Hard Precision Operational Amplifiers C.nF - V + - R R 2 V IN ISL7227SRH + OUTPUT - -2 BIASED 68.3nF C 2 V - Sallen-Key Low Pass Filter (MHz) FIGURE. TYPICAL APPLICATION -2 GROUNDED TOTAL DOSE (krad(si)) FIGURE 2. OFFSET VOLTAGE vs RADIATION FN792 Rev 2. Page of 4 July 8, 24

2 . ISL7227SRH Ordering Information ORDERING NUMBER PART MARKING TEMP RANGE ( C) PACKAGE (Pb-Free) PKG. DWG. # ISL7227SRHMF (Note ) ISL7227 SRHMF - to +2 Ld FLATPACK K.A ISL7227SRHF/PROTO (Note ) ISL7227 SRHF/PROTO - to +2 Ld FLATPACK K.A ISL7227SRHMX - to +2 DIE ISL7227SRHX/SAMPLE - to +2 DIE ISL7227MHEVALZ Evaluation Board NOTES:. These Intersil Pb-free Hermetic packaged products employ % Au plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Pin Configuration ISL7227SRH ( LD FLATPACK) TOP VIEW OUTA V+ -IN A +IN A NC OUT B -IN B +IN B V- 6 NC Pin Descriptions PIN NUMBER PIN NAME EQUIVALENT CIRCUIT DESCRIPTION 3 +IN_A Circuit Amplifier A Non-inverting Input V- Circuit 3 Negative Power Supply 7 +IN_B Circuit Amplifier B Non-inverting Input 8 -IN_B Circuit Amplifier B Inverting Input 9 OUT B Circuit 2 Amplifier B Output V+ Circuit 3 Positive Power Supply OUT A Circuit 2 Amplifier A Output 2 -IN_A Circuit Amplifier A Inverting Input 4, 6 NC - Not Connected This pin is not electrically connected internally. V+ V+ V+ IN- V- IN+ OUT V- V- CAPACITIVELY TRIGGERED ESD CLAMP CIRCUIT CIRCUIT 2 CIRCUIT 3 FN792 Rev 2. Page 2 of 4 July 8, 24

3 ISL7227SRH Absolute Maximum Ratings Maximum Supply Voltage V Maximum Differential Input Current mA Maximum Differential Input Voltage V Min/Max Input Voltage V- -.V to V+ +.V Max/Min Input Current for Input Voltage >V+ or <V ±2mA Output Short-Circuit Duration ( Output at a Time) Indefinite ESD Tolerance Human Body Model (Tested per JESD22-A4F) kV Machine Model (Tested per EIA/JESD22-A-A) V Charged Device Model (Tested per JESD22-CD) V Di-electrically Isolated PR4 Process Latch-up free Thermal Information Thermal Resistance (Typical) JA ( C/W) JC ( C/W) Ld Ceramic Flatpack (Notes 2, 3) Storage Temperature Range C to + C Recommended Operating Conditions Ambient Operating Temperature Range C to +2 C Maximum Operating Junction Temperature C Supply Voltage V (±2.V) to 3V (±V) CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 2. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 3. For JC, the case temp location is the center of the exposed metal pad on the package underside. Electrical Specifications V S ±V, V CM =, V O = V, R L = Open, T A = +2 C, unless otherwise noted. Boldface limits apply across the operating temperature range, - C to +2 C, and over the radiation tolerance limit with exposure at a high dose rate. PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT V OS Offset Voltage -7-7 µv - - µv TCV OS Offset Voltage Drift -. µv/ C I OS Input Offset Current - na -2-2 na I B Input Bias Current - na -2-2 na V CM Input Voltage Range Guaranteed by CMRR -3-3 V -2-2 V CMRR Common-Mode Rejection Ratio V CM = -3V to +3V 2 - db V CM = -2V to +2V - - db PSRR Power Supply Rejection Ratio V S = ±2.2V to ±V 7 - db V S = ±3V to ±V - - db A VOL Open-Loop Gain V O = -3V to +3V R L = kω to ground - V/mV V OH Output Voltage High R L = kω to ground V V R L = 2kΩ to ground V V V OL Output Voltage Low R L = kω to ground V V R L = 2kΩ to ground V V FN792 Rev 2. Page 3 of 4 July 8, 24

4 ISL7227SRH Electrical Specifications V S ±V, V CM =, V O = V, R L = Open, T A = +2 C, unless otherwise noted. Boldface limits apply across the operating temperature range, - C to +2 C, and over the radiation tolerance limit with exposure at a high dose rate. (Continued) PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT I S Supply Current/Amplifier ma ma I SC Short-Circuit R L = Ω to ground - ±4 - ma V SUPPLY Supply Voltage Range Guaranteed by PSRR ±2.2 - ± V AC SPECIFICATIONS GBW Gain Bandwidth Product - - MHz e np-p Voltage Noise.Hz to Hz nv P-P e n Voltage Noise Density f = Hz nv/ Hz e n Voltage Noise Density f = Hz nv/ Hz e n Voltage Noise Density f = khz nv/ Hz e n Voltage Noise Density f = khz nv/ Hz in Current Noise Density f = khz pa/ Hz THD + N Total Harmonic Distortion + Noise khz, G =, V O = 3.V RMS, R L = 2kΩ % TRANSIENT RESPONSE SR Slew Rate A V =, R L = 2kΩ V O = 4V P-P - ±3.6 - V/µs t r, t f, Small Signal Rise Time A V = -, V OUT = mv P-P, ns % to 9% of V OUT R f = R g = 2kΩ R L = 2kΩ to V CM Fall Time A V = -, V OUT = mv P-P, ns 9% to % of V OUT R f = R g = 2kΩ R L = 2kΩ to V CM t s Settling Time to.% V Step; % to V OUT A V = -, V OUT = V P-P, R g = R f = k, R L = 2kΩ to V CM µs Settling Time to.% A V = -, V OUT = V P-P, µs V Step; % to V OUT R L = 2kΩ to V CM t OL Output Overload Recovery Time A V =, V IN =.2V, R L = 2kΩ to V CM µs Electrical Specifications V S ±V, V CM =, V O = V, T A = +2 C, unless otherwise noted. Boldface limits apply across the operating temperature range, - C to +2 C. PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT V OS Offset Voltage µv TCV OS Offset Voltage Drift -. - µv/ C I OS Input Offset Current - - na I B Input Bias Current - - na CMRR Common-Mode Rejection Ratio V CM = -3V to +3V db PSRR Power Supply Rejection Ratio V S = ±2.2V to ±V db A VOL Open-Loop Gain V O = -3V to +3V R L = kω to ground - - V/mV V OH Output Voltage High R L = kω to ground V R L = 2kΩ to ground FN792 Rev 2. Page 4 of 4 July 8, 24

5 ISL7227SRH Electrical Specifications V S ±V, V CM =, V O = V, T A = +2 C, unless otherwise noted. Boldface limits apply across the operating temperature range, - C to +2 C. (Continued) PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT V OL Output Voltage Low R L = kω to ground V R L = 2kΩ to ground I S Supply Current/Amplifier ma I SC Short-Circuit - ±4 - ma AC SPECIFICATIONS GBW Gain Bandwidth Product - - MHz THD + N Total Harmonic Distortion + Noise khz, G =, Vo = 2.V RMS, R L = 2kΩ % TRANSIENT RESPONSE SR Slew Rate A V =, R L = 2kΩ OH - ±3.6 - V/µs t r, t f, Small Signal Rise Time A V = -, V OUT = mv P-P, ns % to 9% of V OUT R f = R g = 2kΩ R L = 2kΩ to V CM Fall Time A V = -, V OUT = mv P-P, ns 9% to % of V OUT R f = R g = 2kΩ R L = 2kΩ to V CM t s Settling Time to.% A V = -, V OUT = 4V P-P, R f = R g = 2kΩ R L = 2kΩ to V CM µs Settling Time to.% A V = -, V OUT = 4V P-P, R f = R g = 2kΩ R L = 2kΩ to V CM µs NOTE: 4. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. Post Radiation Characteristics V S ±V, V CM = V, V O = V, R L = Open, T A = +2 C, unless otherwise noted. This data is ATE test data of the ISL7227SRH post radiation exposure at a high dose rate of to 3rad(Si)/s, these are not limits nor are they guaranteed. PARAMETER DESCRIPTION CONDITIONS k RAD 7k RAD k RAD UNIT V OS Offset Voltage µv I OS Input Offset Current na I B Input Bias Current na CMRR Common-Mode Rejection Ration V CM = -3V to +3V db PSRR Power Supply Rejection Ratio V S = ±2.2V to ±V db A VOL Open-Loop Gain V O = -3V to +3V R L = kω to ground V/mV I S Supply Current/Amplifier ma FN792 Rev 2. Page of 4 July 8, 24

6 I B- (na) I IO (na) V OS (µv) I B+ (na) ISL7227SRH Post Radiation Characteristics V S ±V, V CM = V, V O = V, R L = Open, T A = +2 C, unless otherwise noted. This data is ATE test data of the ISL7227SRH post radiation exposure at a low dose rate of <mrad(si)/s, these are not limits nor are they guaranteed. - - BIASED BIASED GROUNDED GROUNDED TOTAL DOSE (krad(si)) FIGURE 3. OFFSET VOLTAGE vs RADIATION TOTAL DOSE (krad(si)) FIGURE 4. POSITIVE INPUT BIAS CURRENT vs RADIATION BIASED GROUNDED BIASED GROUNDED TOTAL DOSE (krad(si)) FIGURE. NEGATIVE INPUT BIAS CURRENT vs RADIATION TOTAL DOSE (krad(si)) FIGURE 6. OFFSET CURRENT vs RADIATION SUPPLY CURRENT (ma) BIASED GROUNDED TOTAL DOSE (krad(si)) FIGURE 7. TOTAL SUPPLY CURRENT vs RADIATION FN792 Rev 2. Page 6 of 4 July 8, 24

7 ISL7227SRH Typical Performance Curves, V CM = V, R L = Open, unless otherwise specified. INPUT NOISE VOLTAGE (nv) V + = 38V -6 R L = k C L = 3.pF -8 R g =, R f = k A V =, TIME (s) FIGURE 8. INPUT NOISE VOLTAGE.Hz TO Hz INPUT NOISE VOLTAGE (nv/ Hz) V S = ±9V A V =. k k k FIGURE 9. INPUT NOISE VOLTAGE SPECTRAL DENSITY INPUT NOISE CURRENT (pa/ Hz) V S = ±9V A V =.. k k k PSRR (db ) PSRR+ AND PSRR- V S = ±V R L = INF C L =.2pF A V = + V S = V P-P PSRR+ and PSRR- k k k M M FIGURE. INPUT NOISE CURRENT SPECTRAL DENSITY FIGURE. PSRR vs FREQUENCY, V S = ±V, ±V CMRR (db) 3 2 V S = ±V V S = ±2.2V R L = INF 3 C 2 L =.2pF A V = + V CM = V P-P - k k k M M FIGURE 2. CMRR vs FREQUENCY, V S = ±2.2, ±V, ±V V OS (µv) TEMPERATURE ( C) FIGURE 3. V OS vs TEMPERATURE FN792 Rev 2. Page 7 of 4 July 8, 24

8 ISL7227SRH Typical Performance Curves, V CM = V, R L = Open, unless otherwise specified. (Continued). I B+ (na) I B+ I B- (na) I B TEMPERATURE ( C) TEMPERATURE ( C) FIGURE 4. I B+ vs TEMPERATURE FIGURE. I B- vs TEMPERATURE 3. I IO (na) I IO I CC (ma) I CC TEMPERATURE ( C) FIGURE 6. I OS vs TEMPERATURE TEMPERATURE ( C) FIGURE 7. SUPPLY CURRENT vs TEMPERATURE V OUT (V) V OH k V OH 2k V OUT (V) V OL k V OL 2k TEMPERATURE ( C) TEMPERATURE ( C) FIGURE 8. V OH vs TEMPERATURE, FIGURE 9. V OL vs TEMPERATURE, FN792 Rev 2. Page 8 of 4 July 8, 24

9 ISL7227SRH Typical Performance Curves, V CM = V, R L = Open, unless otherwise specified. (Continued) V OH (V) V OUT (V) - C V OUT (V) C 9 V OUT (V) +2 C 8 V OUT (V) +2 C A V =, 3 V IN =.3V OUTPUT CURRENT (ma) FIGURE 2. V OH vs OUTPUT CURRENT OPEN-LOOP GAIN (db)/phase ( ) PHASE GAIN -2 R L = k -4 C -6 L = pf -8 SIMULATION -.m m m m k k k M M M FIGURE 2. OPEN-LOOP GAIN, PHASE vs FREQUENCY, R L =kω C L = pf V OL (V) V OUT (V) +2 C V OUT (V) +2 C V OUT (V) C V OUT (V) - C.... OUTPUT CURRENT (ma) FIGURE 22. V OL vs OUTPUT CURRENT A V =, V IN = -.3V OPEN-LOOP GAIN (db)/phase( ) PHASE GAIN -2 R L = k -4 C -6 L = pf SIMULATION -8 -.m m m m k k k M M M FIGURE 23. OPEN-LOOP GAIN, PHASE vs FREQUENCY, R L =kω C L = pf R g = k, R f = k 4 A V = C L = 3.pF 3 R L = INF A V OUT = mv P-P V = 2 R g = k, R f = k A V = R g = OPEN, R f = - k k k M M M FIGURE 24. FREQUENCY RESPONSE vs CLOSED LOOP GAIN GAIN (db) 7 6 A V = R g =, R f = k GAIN (db) C +2 C -6 C +2 C 4 3 A V =, V OUT = mv P-P, 2 V S = +-V, R L = 2kΩ k k k M M FIGURE 2. GAIN vs FREQUENCY vs TEMPERATURE FN792 Rev 2. Page 9 of 4 July 8, 24

10 ISL7227SRH Typical Performance Curves, V CM = V, R L = Open, unless otherwise specified. (Continued) NORMALIZED GAIN (db) R L = k - C L = 3.pF A V = +2-3 V OUT = mv P-P - k k R f = R g = k R f = R g = k M M M R f = R g = k R f = R g = k FIGURE 26. FREQUENCY RESPONSE vs FEEDBACK RESISTANCE R f /R g NORMALIZED GAIN (db) C L = 3.pF A V = + -4 V OUT = mv P-P R L = k R L = k R L = 499 R L = R L = k k k M M M FIGURE 27. GAIN vs FREQUENCY vs R L NORMALIZED GAIN (db) k R L = k A V = + V OUT = mv P-P k C L = pf C L = 22pF C L = pf C L = 2.pF C L = 3.pF k M M M FIGURE 28. GAIN vs FREQUENCY vs C L NORMALIZED GAIN (db) k C L = 3.pF R L = k A V = + V OUT = mv P-P k V S = ±2.2V k M M M V S = ±V FIGURE 29. GAIN vs FREQUENCY vs SUPPLY VOLTAGE LARGE SIGNAL (V) C L = 3.pF A V = R f = R g = inf V OUT = V P-P R L = 2k R L = k TIME (µs) FIGURE 3. LARGE SIGNAL V STEP RESPONSE, LARGE SIGNAL (V) OUTPUT +2 C OUTPUT +2 C OUTPUT - C R L = 2k A V = R f = R g = inf V OUT = V P-P TIME (µs) FIGURE 3. LARGE SIGNAL V STEP RESPONSE, vs TEMPERATURE FN792 Rev 2. Page of 4 July 8, 24

11 ISL7227SRH Typical Performance Curves, V CM = V, R L = Open, unless otherwise specified. (Continued) , R L = 2k, k V S = ±V, R L = 2k, k -.2 C -.6 L = 3.pF A V = -2. V OUT = 4V P-P TIME (µs) FIGURE 32. LARGE SIGNAL TRANSIENT RESPONSE vs R L, V S = ±V, ±V LARGE SIGNAL (V) SMALL SIGNAL (mv) V S = ±V, ±V 4 R L = 2k C L = 3.pF 6 A V = V OUT = mv P-P TIME (ms) FIGURE 33. SMALL SIGNAL TRANSIENT RESPONSE, V S = ±V, ±V.6.2 INPUT OUTPUT 2 INPUT (V) R L = k C L = 3.pF A V = R f = k, R g = k V IN = 2mV P-P OUTPUT (V) INPUT (V) R L = k C L = 3.pF A V = R f = k, R g = k V IN = 2mV P-P INPUT OUTPUT (V) TIME (µs) OUTPUT FIGURE 34. POSITIVE OUTPUT OVERLOAD RESPONSE TIME, TIME (µs) FIGURE 3. NEGATIVE OUTPUT OVERLOAD RESPONSE TIME, V S =±V -2 OVERSHOOT (%) R L = k A V = V OUT = mv P-P OVERSHOOT + OVERSHOOT - CAPACITANCE (pf) FIGURE 36. % OVERSHOOT vs LOAD CAPACITANCE, FN792 Rev 2. Page of 4 July 8, 24

12 ISL7227SRH Applications Information Functional Description The ISL7227SRH is a dual, low noise MHz BW precision op amp fabricated in a new precision 4V complementary bipolar DI process. A super-beta NPN input stage with input bias current cancellation provides low input bias current (na typical), low input offset voltage (µv typ), low input noise voltage (3nV/ Hz), and low /f noise corner frequency (Hz). These amplifiers also feature high open-loop gain (V/mV) for excellent CMRR (2dB) and THD+N performance (.2% at 3.V RMS, khz into 2kΩ). A complimentary bipolar output stage enables high capacitive load drive without external compensation. Operating Voltage Range The devices are designed to operate over the 4.V (±2.2V) to 36V (±8V) range and are fully characterized at 3V (±V). Parameter variation with operating voltage is shown in the Typical Performance Curves beginning on page 7. Input ESD Diode Protection The input terminals (IN+ and IN-) have internal ESD protection diodes to the positive and negative supply rails, and an additional anti-parallel diode pair across the inputs (see Figures 37 and 38). V IN R IN - + V+ V- FIGURE 37. INPUT ESD DIODE CURRENT LIMITING - UNITY GAIN For unity gain applications (see Figure 37) where the output is connected directly to the non-inverting input a current limiting resistor (R IN ) will be needed under the following conditions to protect the anti-parallel differential input protection diodes. The amplifier input is supplied from a low impedance source. The input voltage rate-of-rise (dv/dt) exceeds the maximum slew rate of the amplifier (±3.6V/µs). If the output lags far enough behind the input, the anti-parallel input diodes can conduct. For example, if an input pulse ramps from V to +V in µs, then the output of the ISL7227SRH will reach only +3.6V (slew rate = 3.6V/µs) while the input is at V, The input differential voltage of 6.4V will force input ESD diodes to conduct, dumping the input current directly into the output stage and the load. The resulting current flow can cause permanent damage to the ESD diodes. The ESD diodes are rated to 2mA, and in the previous example, setting R IN to k resistor (see Figure 37) would limit the current to <6.4mA, and provide additional protection up to ±2V at the input. In applications where one or both amplifier input terminals are at risk of exposure to high voltage, current limiting resistors may be needed at each input terminal (see Figure 38 R IN +, R IN -) to limit current through the power supply ESD diodes to 2mA. R L V OUT V IN - V IN + FIGURE 38. INPUT ESD DIODE CURRENT LIMITING - DIFFERENTIAL INPUT Output Current Limiting The output current is internally limited to approximately ±4mA at +2 C and can withstand a short circuit to either rail as long as the power dissipation limits are not exceeded. This applies to only amplifier at a time. Continuous operation under these conditions may degrade long term reliability. Output Phase Reversal Output phase reversal is a change of polarity in the amplifier transfer function when the input voltage exceeds the supply voltage. The ISL7227SRH are immune to output phase reversal, even when the input voltage is V beyond the supplies. Power Dissipation It is possible to exceed the + C maximum junction temperatures under certain load and power supply conditions. It is therefore important to calculate the maximum junction temperature (T JMAX ) for all applications to determine if power supply voltages, load conditions, or package type need to be modified to remain in the safe operating area. These parameters are related using Equation : where: where: R IN - R IN V+ V- T MAX = Maximum ambient temperature JA = Thermal resistance of the package PD MAX = Maximum power dissipation of amplifier V S = Total supply voltage I qmax = Maximum quiescent supply current of amplifier V OUTMAX = Maximum output voltage swing of the application R L = Load resistance R L V OUT T JMAX = T MAX + JA xpd (EQ. ) MAXTOTAL P DMAXTOTAL is the sum of the maximum power dissipation of each amplifier in the package (PD MAX ) PD MAX for each amplifier can be calculated using Equation 2: V OUTMAX PD MAX = V S I qmax + V S - V OUTMAX (EQ. 2) R L FN792 Rev 2. Page 2 of 4 July 8, 24

13 ISL7227SRH Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. DATE REVISION CHANGE July 8, 24 FN792.2 Updated Radiation tolerance on page from: High Dose Ratekrad(Si) Low Dose Ratekrad(Si) SEL/SEB LETTH86MeV/mg/cm2 to: High Dose Ratekrad(Si) SEB LETTH (VS = ±8V)86.4MeV/mg/cm2 SEL Immune (SOI Process) Removed MSL note in the Ordering Information table on page 2 as it is not applicable to Hermetic packages Replaced Figures 8 and 9. Updated About Intersil verbiage from Products verbiage. September 2, 2 FN792. Added Related Literature on page. Made correction to Ordering Information - Eval board name changed from "ISL7227SRHEVALZ" TO "ISL7227MHEVALZ" September 7, 2 FN792. Initial Release. About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at You may report errors or suggestions for improving this datasheet by visiting Reliability reports are also available from our website at Copyright Intersil Americas LLC All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see Intersil products are manufactured, assembled and tested utilizing ISO9 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see FN792 Rev 2. Page 3 of 4 July 8, 24

14 ISL7227SRH Ceramic Metal Seal Flatpack Packages (Flatpack) -Hb A e -A-.4 M H A - B Q SEATING AND BASE PLANE L M c S E3 D S PIN NO. ID AREA E E E2 LEAD FINISH BASE METAL b (b) SECTION A-A.36 M H A - B NOTES:. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer s identification shall not be used as a pin one identification mark. Alternately, a tab (dimension k) may be used to identify pin one. 2. If a pin one identification mark is used in addition to a tab, the limits of dimension k do not apply. 3. This dimension allows for off-center lid, meniscus, and glass overrun. 4. Dimensions b and c apply to lead base metal only. Dimension M applies to lead plating and finish thickness. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied.. N is the maximum number of terminal positions. 6. Measure dimension S at all four corners. 7. For bottom-brazed lead packages, no organic or polymeric materials shall be molded to the bottom of the package to cover the leads. 8. Dimension Q shall be measured at the point of exit (beyond the meniscus) of the lead from the body. Dimension Q minimum shall be reduced by. inch (.38mm) maximum when solder dip lead finish is applied. 9. Dimensioning and tolerancing per ANSI Y4.M Controlling dimension: INCH. M E3 (c) L C S S A A D S -D- -C- -B- D K.A MIL-STD-83 CDFP3-F (F-4A, CONFIGURATION B) LEAD CERAMIC METAL SEAL FLATPACK PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A b b c c D E E E E e. BSC.27 BSC - k L Q S M N - Rev. 3/7 FN792 Rev 2. Page 4 of 4 July 8, 24