DATASHEET ISL Features. Applications Ordering Information. Pinouts. 5MHz, Single Precision Rail-to-Rail Input-Output (RRIO) Op Amp

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1 DATASHEET ISL2836 MHz, Single Precision Rail-to-Rail Input-Output (RRIO) Op Amp FN63 Rev 6. January 6, 2 The ISL2836 is a low-power single operational amplifier optimized for single supply operation from 2.V to.v, allowing operation from one lithium cell or two Ni-Cd batteries. This device features a gain-bandwidth product of MHz and is unity-gain stable with a -3dB bandwidth of 3MHz. This device features an Input Range Enhancement Circuit (IREC), which enables it to maintain CMRR performance for input voltages greater than the positive supply. The input signal is capable of swinging.2v above the positive supply and to the negative supply with only a slight degradation of the CMRR performance. The output operation is rail-to-rail. The part typically draws less than ma supply current while meeting excellent DC accuracy, AC performance, noise and output drive specifications. Operation is guaranteed over - C to +2 C temperature range. Features MHz Gain bandwidth A V = 3MHz -3dB unity gain bandwidth 9µA typical supply current µv maximum offset voltage (8 Ld SOIC) na typical input bias current Down to 2.V single supply voltage range Rail-to-rail input and output Enable pin - C to +2 C operation Pb-free (RoHS compliant) Applications Ordering Information PART NUMBER (Notes 2, 3) ISL2836FHZ-T7 (Note ) PART MARKING PACKAGE (Pb-Free) GABP (Note ) 6 Ld SOT-23 PKG. DWG. # P6.6A Low-end audio ma to 2mA current loops Medical devices Sensor amplifiers ADC buffers ISL2836FHZ-T7A (Note ) GABP (Note ) 6 Ld SOT-23 P6.6A DAC output amplifiers ISL2836FBZ 2836 FBZ 8 Ld SOIC M8.E ISL2836FBZ-T7 (Note ) ISL2836EVALZ 2836 FBZ 8 Ld SOIC M8.E Evaluation Board. Please refer to TB37 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and % matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-2. Pinouts OUT V- IN+ ISL2836 (6 LD SOT-23) TOP VIEW V+ EN NC IN- IN- IN+ 2 3 ISL2836 (8 LD SOIC) TOP VIEW - + V- NC EN V+ OUT 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL2836. For more information on MSL please see techbrief TB363.. The part marking is located on the bottom of the parts. FN63 Rev 6. Page of January 6, 2

2 Absolute Maximum Ratings (T A = +2 C) Supply Voltage V Supply Turn-on Voltage Slew Rate V/µs Differential Input Current ma Differential Input Voltage V Input Voltage V- -.V to V+ +.V ESD Rating Human Body Model kV Machine Model V Thermal Information Thermal Resistance (Typical) JA ( C/W) JC ( C/W) 6 Ld SOT-23 Package (Note ) 23 N/A 8 Ld SOIC Package (Notes, 6) 2 7 Ambient Operating Temperature Range C to +2 C Storage Temperature Range C to + C Operating Junction Temperature C Pb-free reflow profile see link below CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES:. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 6. For JC, the case temp location is taken at the package top center. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: T J = T C = T A Electrical Specifications V + = V, V - = V, V CM = 2.V, R L = Open, T A = +2 C unless otherwise specified. Boldface limits apply over the operating temperature range, - C to +2 C. Temperature data established by characterization. PARAMETER DESCRIPTION CONDITIONS (Note 7) TYP (Note 7) UNIT DC SPECIFICATIONS V OS Input Offset Voltage 8 Ld SOIC - ± µv Ld SOT-23 - ± µv - V OS Input Offset Voltage vs Temperature. µv/ C T I OS Input Offset Current T A = - C to +8 C - - na I B Input Bias Current T A = - C to +8 C -3 3 na - V CM Common-Mode Voltage Range Guaranteed by CMRR V CMRR Common-Mode Rejection Ratio V CM = V to V 9 db 8 PSRR Power Supply Rejection Ratio V + = 2.V to.v 9 99 db 8 A VOL Large Signal Voltage Gain V O =.V to V, to V CM 6 77 V/mV V O =.V to V, to V CM V/mV V OUT Maximum Output Voltage Swing Output low, to V CM 3 6 mv Output low, to V CM 7 9 mv Output high, to V CM V.98 Output high, to V CM.92.9 V.89 I S,ON Supply Current, Enabled Per Amp.8.9. ma. FN63 Rev 6. Page 2 of January 6, 2

3 Electrical Specifications V + = V, V - = V, V CM = 2.V, R L = Open, T A = +2 C unless otherwise specified. Boldface limits apply over the operating temperature range, - C to +2 C. Temperature data established by characterization. (Continued) PARAMETER DESCRIPTION CONDITIONS (Note 7) TYP (Note 7) UNIT I S,OFF Supply Current, Disabled µa 6 I O + Short-Circuit Output Source Current R L = to V CM 8 6 ma I O - Short-Circuit Output Sink Current R L = to V CM ma V SUPPLY Supply Operating Range V + to V V V ENH EN Pin High Level 2 V V ENL EN Pin Low Level.8 V I ENH EN Pin Input High Current V EN = V +. µa.6 I ENL EN Pin Input Low Current V EN = V na 3 AC SPECIFICATIONS GBW Gain Bandwidth Product A V =, R F = k R G = k to V CM MHz Unity Gain Bandwidth -3dB Bandwidth A V =, R F = to V CM 3 MHz V OUT = mv P-P e N Input Noise Voltage Peak-to-Peak f =.Hz to Hz, to V CM. µv P-P Input Noise Voltage Density f O = khz, to V CM nv/ Hz i N Input Noise Current Density f O = khz, to V CM.3 pa/ Hz CMRR Input Common Mode Rejection Ratio f O = to 2Hz; V CM = V P-P, to V CM -9 db PSRR+ to 2Hz PSRRto 2Hz Power Supply Rejection Ratio (V + ) Power Supply Rejection Ratio (V - ) V +, V - = ±.2V and ±2.V, -88 db V SOURCE = V P-P, to V CM V +, V - = ±.2V and ±2.V - db V SOURCE = V P-P, to V CM TRANSIENT RESPONSE SR Slew Rate V OUT = ±.V; R f = k R G = k to ±.9 V/µs V CM t r, t f, Large Signal t r, t f, Small Signal Rise Time, % to 9%, V OUT Fall Time, 9% to %, V OUT A V = +2, V OUT = 2V P-P, R g = R f =.6 µs to V CM A V = +2, V OUT = 2V P-P, R g = R f =. µs to V CM Rise Time, % to 9%, V OUT A V = +2, V OUT = mv P-P, R g = R f = to V CM 6 ns Fall Time, 9% to %, V OUT A V = +2, V OUT = mv P-P, R g = R f = to V CM 62 ns t EN Enable to Output Turn-on Delay Time, % EN to % V OUT V EN = V to V, A V = +2, µs R g = R f = to V CM Enable to Output Turn-off Delay Time, % V EN = V to V, A V = +2,.3 µs EN to % V OUT R g = R f = to V CM NOTE: 7. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. FN63 Rev 6. Page 3 of January 6, 2

4 Typical Performance Curves NORMALIZED GAIN (db) - - V + = V A V = +2 V OUT = mv P-P R f = R g = k R f = R g = k - k k k M M M FIGURE. GAIN vs FREQUENCY vs FEEDBACK RESISTOR VALUES R f /R g V + = V, V - = V, V CM = 2.V, R L = Open R f = R g = k NORMALIZED GAIN (db) V OUT = V V OUT = mv V OUT = mv V OUT = mv - V + = V V OUT = mv P-P -9 k k M M M FIGURE 2. GAIN vs FREQUENCY vs V OUT, NORMALIZED GAIN (db) - V OUT = V -2 V OUT = mv -3 V OUT = mv - V OUT = mv - V + = V V OUT = mv P-P -9 k k M M M NORMALIZED GAIN (db) V OUT = V V OUT = mv V OUT = mv V OUT = mv - V + = V R -6 L = k -7-8 V OUT = mv P-P -9 k k M M M FIGURE 3. GAIN vs FREQUENCY vs V OUT, FIGURE. GAIN vs FREQUENCY vs V OUT, NORMALIZED GAIN (db) V + = V -7-8 V OUT = mv P-P -9 k k M M M FIGURE. GAIN vs FREQUENCY vs R L GAIN (db) 7 6 A V = A V =, R g = k, R f = M A V = A V =, R g = k, R f = k V 3 + = V A V = R 2 L = k V OUT = mv P-P A V =, R g = k, R f = 9.9k A V = A V =, R g = INF, R f = - k k k M M M FIGURE 6. FREQUENCY RESPONSE vs CLOSED LOOP GAIN FN63 Rev 6. Page of January 6, 2

5 Typical Performance Curves NORMALIZED GAIN (db) V + = 2.V V OUT = mv P-P -9 k k M M M FIGURE 7. GAIN vs FREQUENCY vs SUPPLY VOLTAGE V + = V, V - = V, V CM = 2.V, R L = Open (Continued) V + = V NORMALIZED GAIN (db) V + = V V OUT = mv P-P C L =.7pF C L = 3.7pF C L = 37.7pF C L = 26.7pF C L = 6.7pF C L =.7pF k k M M M FIGURE 8. GAIN vs FREQUENCY vs C L CMRR (db) V + = 2.V, V V CM = V P-P k k k M M PSRR (db) V +, V - = ±.2V V SOURCE = V P-P PSRR+ k k k M M FIGURE 9. CMRR vs FREQUENCY; V + = 2.V AND V FIGURE. PSRR vs FREQUENCY, V +, V - = ±.2V PSRR (db) V +, V - = ±2.V V SOURCE = V P-P PSRR- PSRR- PSRR+ k k k M M FIGURE. PSRR vs FREQUENCY, V +, V - = ±2.V INPUT VOLTAGE NOISE (nv Hz) V + = V k k k FIGURE 2. INPUT VOLTAGE NOISE DENSITY vs FREQUENCY FN63 Rev 6. Page of January 6, 2

6 Typical Performance Curves INPUT CURRENT NOISE (pa Hz). k k k FIGURE 3. INPUT CURRENT NOISE DENSITY vs FREQUENCY V + = V, V - = V, V CM = 2.V, R L = Open (Continued) V + = V INPUT NOISE (µv) V + = V R g =, R f = k A V = TIME (s) FIGURE. INPUT VOLTAGE NOISE.Hz TO Hz LARGE SIGNAL (V) V +, V - = ±2.V.8.6 R g = R f = k A V = 2. V OUT =.V P-P TIME (µs) FIGURE. LARGE SIGNAL STEP RESPONSE SMALL SIGNAL (V).22.2 V +, V - = ±2.V R g = R f = k A V = 2 V OUT = mv P-P TIME (µs) FIGURE 6. SMALL SIGNAL STEP RESPONSE V-ENABLE (V) V-ENABLE V-OUT V + = V R g = R f = A V = +2 V OUT = V P-P TIME (µs) FIGURE 7. ENABLE TO OUTPUT RESPONSE OUTPUT (V) V OS (µv) V + = V R L = OPEN R f = k, R g = V CM (V) FIGURE 8. INPUT OFFSET VOLTAGE vs COMMON-MODE INPUT VOLTAGE FN63 Rev 6. Page 6 of January 6, 2

7 Typical Performance Curves I-BIAS (na) V + = V R L = OPEN R f = k, R g = V CM (V) FIGURE 9. INPUT OFFSET CURRENT vs COMMON-MODE INPUT VOLTAGE V + = V, V - = V, V CM = 2.V, R L = Open (Continued) CURRENT (µa) N = FIGURE 2. SUPPLY CURRENT ENABLED vs TEMPERATURE, V +, V - = ±2.V CURRENT (µa) N = V OS (µv) N = FIGURE 2. SUPPLY CURRENT DISABLED vs TEMPERATURE, V +, V - = ±2.V FIGURE 22. V OS vs TEMPERATURE, V +, V - = ±2.V, SOT PACKAGE V OS (µv) 3 2 N = V OS (µv) N = FIGURE 23. V OS vs TEMPERATURE, V +, V - = ±2.V, SOIC PACKAGE FIGURE 2. V OS vs TEMPERATURE, V +, V - = ±.2V, SOT PACKAGE FN63 Rev 6. Page 7 of January 6, 2

8 Typical Performance Curves V OS (µv) V + = V, V - = V, V CM = 2.V, R L = Open (Continued) N = I BIAS + (na) N = FIGURE 2. V OS vs TEMPERATURE, V +, V - = ±.2VSOIC PACKAGE FIGURE 26. I BIAS + vs TEMPERATURE, V +, V - = ±2.V I BIAS - (na) I BIAS + (na) N = FIGURE 27. I BIAS - vs TEMPERATURE, V +, V - = ±2.V -2 N = FIGURE 28. I BIAS + vs TEMPERATURE, V +, V - = ±.2V I BIAS - (na) 2 N = FIGURE 29. I BIAS - vs TEMPERATURE, V +, V - = ±.2V I OS (na) N = FIGURE 3. I OS vs TEMPERATURE, V +, V - = ±2.V FN63 Rev 6. Page 8 of January 6, 2

9 Typical Performance Curves I OS (na) N = V + = V, V - = V, V CM = 2.V, R L = Open (Continued) CMRR (db) N = FIGURE 3. I OS vs TEMPERATURE, V +, V - = ±.2V FIGURE 32. CMRR vs TEMPERATURE, V CM = -2.V TO +2.V, V +, V - = ±2.V PSRR (db) 2 9 N = AVOL (V/mV) N = FIGURE 33. PSRR vs TEMPERATURE, V +, V - = ±.2V TO ±2.7V FIGURE 3. AVOL vs TEMPERATURE, V +, V - = ±2.V, V O = -2V TO +2V, AVOL (V/mV) N = V OUT (V).96 N = FIGURE 3. AVOL vs TEMPERATURE, V +, V - = ±2.V, V O = -2V TO +2V, FIGURE 36. V OUT HIGH vs TEMPERATURE, V +, V - = ±2.V, R L =k FN63 Rev 6. Page 9 of January 6, 2

10 Typical Performance Curves V + = V, V - = V, V CM = 2.V, R L = Open (Continued) 7 V OUT (m V) N = FIGURE 37. V OUT LOW vs TEMPERATURE, V +, V - = ±2.V, R L =k Pin Descriptions ISL2836 (6 Ld SOT-23) ISL2836 (8 Ld SOIC) PIN NAME FUNCTION EQUIVALENT CIRCUIT, NC Not connected 2 IN- inverting input V+ IN- IN+ Circuit V- 3 3 IN+ Non-inverting input See Circuit 2 V- Negative supply V+ CAPACITIVELY COUPLED ESD CLAMP 6 OUT Output V- Circuit 2 V+ OUT Circuit 3 V- 6 7 V+ Positive supply See Circuit 2 8 EN Chip enable V+ LOGIC PIN V- Circuit 3 FN63 Rev 6. Page of January 6, 2

11 Applications Information Introduction The ISL2836 is a single channel Bi-CMOS rail-to-rail input, output (RRIO) micropower precision operational amplifier. The part is designed to operate from a single supply 2.V to.v. The part has an input common mode range that extends.2v above the positive rail and down to the negative supply rail. The output operation can swing within about 3mV of the supply rails with a k load. Rail-to-Rail Input Many rail-to-rail input stages use two differential input pairs; a long-tail PNP (or PFET) and an NPN (or NFET). Severe penalties have to be paid for this circuit topology. As the input signal moves from one supply rail to another, the operational amplifier switches from one input pair to the other causing drastic changes in input offset voltage and an undesired change in magnitude and polarity of input offset current. The ISL2836 achieves input rail-to-rail operation without sacrificing important precision specifications and degrading distortion performance. The device s input offset voltage exhibits a smooth behavior throughout the entire commonmode input range. The input bias current versus the commonmode voltage range gives an undistorted behavior from typically down to the negative rail to.2v higher than the positive rail. Rail-to-Rail Output The output stage uses drain-connected N and P-channel MOSFETs to achieve rail-to-rail output swing. The P-channel device sources current to swing the output in the positive direction and the N-channel sinks current to swing the output in the negative direction. The ISL2836 with a k load will swing to within 3mV of the positive supply rail and within 3mV of the negative supply rail. Results of Over-Driving the Output Caution should be used when over-driving the output for long periods of time. Over-driving the output can occur in two ways. ) The input voltage times the gain of the amplifier exceeds the supply voltage by a large value or, 2) the output current required is higher than the output stage can deliver. These conditions can result in a shift in the Input Offset Voltage (V OS ) as much as µv/hr. of exposure under these conditions. IN+ and IN- Input Protection All input terminals have internal ESD protection diodes to both positive and negative supply rails, limiting the input voltage to within one diode beyond the supply rails. They also contain back-to-back diodes across the input terminals (see Pin Descriptions on page - Circuit ). For applications where the input differential voltage is expected to exceed.v, an external series resistor must be used to ensure the input currents never exceed ma (Figure 38). V IN R IN FIGURE 38. INPUT CURRENT LIMITING Enable/Disable Feature The ISL2836 offers an EN pin that disables the device when pulled up to at least 2.V. In the disabled state (output in a high impedance state), the part consumes typically µa at room temperature. By disabling the part, multiple ISL2836 parts can be connected together as a MUX. In this configuration, the outputs are tied together in parallel and a channel can be selected by the EN pin. The loading effects of the feedback resistors of the disabled amplifier must be considered when multiple amplifier outputs are connected together. Note that feed through from the IN+ to IN- pins occurs on any Mux Amp disabled channel where the input differential voltage exceeds.v (e.g., active channel V OUT = V, while disabled channel V IN = GND), so the mux implementation is best suited for small signal applications. If large signals are required, use series IN+ resistors, or a large value R F, to keep the feed through current low enough to minimize the impact on the active channel. See Limitations of the Differential Input Protection on page for more details. To disable the part, the user needs to supply the.µa required to pull the EN pin to the V + rail. If left open, the EN pin will pull to the negative rail and the device will be enabled by default. If the EN function is not required (no need to turn the part off), as a precaution, it is recommended that the user tie the EN pin to the V - pin. Limitations of the Differential Input Protection If the input differential voltage is expected to exceed.v, an external current limiting resistor must be used to ensure the input current never exceeds ma. For non-inverting unity gain applications, the current limiting can be via a series IN+ resistor, or via a feedback resistor of appropriate value. For other gain configurations, the series IN+ resistor is the best choice, unless the feedback (R F ) and gain setting (R G ) resistors are both sufficiently large to limit the input current to ma. Large differential input voltages can arise from several sources: - +. During open loop (comparator) operation. Used this way, the IN+ and IN- voltages don t track, so differentials arise. 2. When the amplifier is disabled but an input signal is still present. An R L or R G to GND keeps the IN- at GND, while the varying IN+ signal creates a differential voltage. Mux Amp applications are similar, except that the active channel V OUT determines the voltage on the IN- terminal. R L V OUT FN63 Rev 6. Page of January 6, 2

12 3. When the slew rate of the input pulse is considerably faster than the op amp s slew rate. If the V OUT can t keep up with the IN+ signal, a differential voltage results, and visible distortion occurs on the input and output signals. To avoid this issue, keep the input slew rate below.9v/µs, or use appropriate current limiting resistors. Large (>2V) differential input voltages can also cause an increase in disabled I CC. Current Limiting These devices have no internal current-limiting circuitry. If the output is shorted, it is possible to exceed the Absolute Maximum Rating for output current or power dissipation, potentially resulting in the destruction of the device. Power Dissipation It is possible to exceed the +2 C maximum junction temperatures under certain load and power-supply conditions. It is therefore important to calculate the maximum junction temperature (T J ) for all applications to determine if power supply voltages, load conditions, or package type need to be modified to remain in the safe operating area. These parameters are related in Equation : T J = T + JA xpd TOTAL (EQ. ) where: P DTOTAL is the sum of the maximum power dissipation of each amplifier in the package (PD ) PD for each amplifier can be calculated using Equation 2: V OUT PD = 2*V S I S + V S - V OUT R L (EQ. 2) where: T = Maximum ambient temperature JA = Thermal resistance of the package PD = Maximum power dissipation of amplifier V S = Supply voltage (Magnitude of V + and V - ) I = Maximum supply current of amplifier V OUT = Maximum output voltage swing of the application R L = Load resistance Copyright Intersil Americas LLC All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see Intersil products are manufactured, assembled and tested utilizing ISO9 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see FN63 Rev 6. Page 2 of January 6, 2

13 Package Outline Drawing M8.E 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE Rev, 8/9.9 ±. A DETAIL "A".22 ±.3 B 6. ± ±. PIN NO. ID MARK.27.3 ±.76 (.3) x ± TOP VIEW.2 MCAB SIDE VIEW B.7. ±..7 ±.7 SIDE VIEW A.2 GAUGE PLANE C SEATING PLANE. C.63 ±.23 (.27) (.6) DETAIL "A" (.) NOTES:. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. (.) Dimensioning and tolerancing conform to AMSE Y.m-99. Unless otherwise specified, tolerance : Decimal ±. Dimension does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed.2mm per side. The pin # identifier may be either a mold or mark feature. Reference to JEDEC MS-2. TYPICAL RECOMMENDED LAND PATTERN FN63 Rev 6. Page 3 of January 6, 2

14 Package Outline Drawing P6.6A 6 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE Rev, 2/.9 A.9 D PIN INDEX AREA C 2x D C 2x (.6) B. ±. 3 SEE DETAIL X.2 M C A-B D TOP VIEW END VIEW 2.9. C 2x A-B TYP (2 PLCS) H. ±. C. SIDE VIEW.-.. C SEATING PLANE (.2) GAUGE PLANE DETAIL "X".±. (.6) (.2) (2.) NOTES:. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to ASME Y.M-99. (.9) Dimension is exclusive of mold flash, protrusions or gate burrs. Foot length is measured at reference to guage plane. This dimension is measured at Datum H. Package conforms to JEDEC MO-78AA. (.9) TYPICAL RECOMMENDED LAND PATTERN FN63 Rev 6. Page of January 6, 2

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