DATASHEET. Features. Related Literature. Applications ISL70218SEH, ISL70218SRH

Transcription

1 DATASHEET ISL728SEH, ISL728SRH Radiation Hardened Dual 36V Precision Single-Supply, Rail-to-Rail Output, Low-Power Operational Amplifiers FN7957 Rev 3. May 9, 26 The ISL728SEH, ISL728SRH are dual, low-power precision amplifiers optimized for single-supply applications. These op amps feature a common-mode input voltage range extending to.5v below the V - rail, a rail-to-rail differential input voltage range, and rail-to-rail output voltage swing, which makes it ideal for single-supply applications where input operation at ground is important. These op amps feature low-power, low-offset voltage and low-temperature drift, making it ideal for applications requiring both high DC accuracy and AC performance. They are designed to operate over a single supply range of 3V to 36V or a split supply voltage range of +.8V/-.2V to ±8V. The combination of precision and small footprint provides the user with outstanding value and flexibility relative to similar competitive parts. Applications for these amplifiers include precision instrumentation, data acquisition and precision power supply controls. ISL728SEH, ISL728SRH are available in a lead hermetic ceramic flatpack and operate across the extended temperature range of to +25 C. Related Literature AN653, ISL728SRH Evaluation Board User s Guide AN677, Single Events Effects Testing of the ISL728SRH, Dual 36V Rad Hard Low Power Operational Amplifiers Features DLA SMD# (ISL728SEH Only) Wide single and dual supply range V to 42V, Abs. Max. Low current consumption µa, typical Low input offset voltage µV, typical Rail-to-rail output <mv Rail-to-rail input differential voltage range for comparator applications Operating temperature range to +25 C Below-ground(V - ) input capability to -.5V Low noise voltage nV/ Hz, typical Low noise current fA/ Hz, typical Offset voltage temperature drift µv/ C, typical No phase reversal Radiation tolerance - High dose rate (5-3rad(Si)/s) krad(si) - Low dose rate (.rad(si)/s) krad(si)* - SEB LET TH (V S = ±8V) MeV cm 2 /mg - SEL Immune (SOI Process) * Product capability established by initial characterization. The EH version is acceptance tested on a wafer-by-wafer basis to 5krad(Si) at low dose rate. Applications Precision instruments Active filter blocks Data acquisition Power supply control R SENSE LOAD R IN - kω R IN + kω IN- IN+ R REF + kω R F kω - V + ISL728SxH V V to 36V V OUT GAIN = V OS (µv) C -4 C V REF INPUT COMMON-MODE VOLTAGE (V) FIGURE. TYPICAL APPLICATION: SINGLE-SUPPLY, LOW-SIDE CURRENT SENSE AMPLIFIER FIGURE 2. INPUT OFFSET VOLTAGE vs INPUT COMMON-MODE VOLTAGE, FN7957 Rev 3. Page of 22 May 9, 26

2 ISL728SEH, ISL728SRH Pin Configuration ISL728SEH, ISL728SRH ( LD FLATPACK) TOP VIEW OUT_A V + -IN_A 2 9 OUT_B +IN_A IN_B NC IN_B V NC Pin Descriptions PIN NUMBER PIN NAME EQUIVALENT CIRCUIT DESCRIPTION OUT_A Circuit 2 Amplifier A output 2 -IN_A Circuit Amplifier A inverting input 3 +IN_A Circuit Amplifier A noninverting input 4, 6 NC No connect 5 V - Circuit, 2, 3 Negative power supply 7 +IN_B Circuit Amplifier B noninverting input 8 -IN_B Circuit Amplifier B inverting input 9 OUT_B Circuit 2 Amplifier B output V + Circuit, 2, 3 Positive power supply V + V + V + IN- IN + V - OUT V - V - CAPACITIVELY TRIGGERED ESD CLAMP CIRCUIT CIRCUIT 2 CIRCUIT 3 FN7957 Rev 3. Page 2 of 22 May 9, 26

3 ISL728SEH, ISL728SRH Ordering Information ORDERING SMD NUMBER PART NUMBER (Note ) TEMP RANGE ( C) PACKAGE (RoHS Compliant) PKG. DWG. # 5962R2222VXC (Note 2) ISL728SEHVF -55 to +25 Ld Flatpack K.A NA ISL728SEHF/PROTO -55 to +25 Ld Flatpack K.A 5962R2222V9A (Note 2) ISL728SEHVX -55 to +25 Die NA ISL728SEHVX/SAMPLE -55 to +25 Die NA ISL728SRHMF -55 to +25 Ld Flatpack K.A NA ISL728SRHF/PROTO -55 to +25 Ld Flatpack K.A NA ISL728SRHMX -55 to +25 Die NA ISL728SRHX/SAMPLE -55 to +25 Die NA ISL728SRHMEVALZ Evaluation Board NOTES:. These Intersil Pb-free Hermetic packaged products employ % Au plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. 2. Specifications for Rad Hard QML devices are controlled by the Defense Logistics Agency Land and Maritime (DLA). The SMD numbers listed in the Ordering Information table must be used when ordering. FN7957 Rev 3. Page 3 of 22 May 9, 26

4 ISL728SEH, ISL728SRH Absolute Maximum Ratings Maximum Supply Voltage V Maximum Supply Voltage (Note 5) V Maximum Differential Input Current mA Maximum Differential Input Voltage V - -.5V to V + +.5V Min/Max Input Voltage V - -.5V to V + +.5V Max/Min Input Current ±2mA Output Short-Circuit Duration ( output at a time) Indefinite ESD Tolerance Human Body Model (Tested per MIL-PRF ) kV Machine Model (Tested per JESD22-A5-A) V Charged Device Model (Tested per CDM-22CIID) V Dielectrically Isolated PR4 Process Latch-Up Free Thermal Information Thermal Resistance (Typical) JA ( C/W) JC ( C/W) Ld Flatpack Package (Notes 3, 4) Storage Temperature Range C to +5 C Recommended Operating Conditions Ambient Operating Temperature Range to +25 C Maximum Operating Junction Temperature C Supply Voltage V (+.8V/-.2V) to 3V (±5V) CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 3. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 4. For JC, the case temp location is the center of the package underside. 5. Tested in a heavy ion environment at LET = 86.4 MeV cm 2 /mg at +25 C (T C ) for SEB. Please refer to AN677 for more information. Electrical Specifications V S ±5V, V CM =, V O = V, R L = Open, T A =, unless otherwise noted. Boldface limits apply across the operating temperature range, to +25 C. SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT V OS Offset Voltage 4 23 µv 29 µv TCV OS Offset Voltage Drift.3.4 µv/ C V OS Input Offset Voltage Match Channel-to-Channel µv 365 µv I OS Input Offset Current na na I B Input Bias Current na -8 na V CMIR Common-Mode Input Voltage Range Guaranteed by CMRR Test (V - ) -.5 (V + ) -.8 V V - (V + ) -.8 V CMRR Common-Mode Rejection Ratio V CM = V - to V + -.8V 8 db V CM = V - to V + -.8V 97 db PSRR Power Supply Rejection Ratio V S = 3V to 4V, V CMIR = Valid Input Voltage A VOL Open-Loop Gain R L = kω to ground V O = -3V to +3V 5 24 db db 2 3 db 5 db V OH Output Voltage High, V + to V OUT R L = kω mv 2 mv V OL Output Voltage Low, V OUT to V - R L = kω 7 mv 8 mv I S Supply Current/Amplifier.85. ma.4 ma I S+ Source Current Capability ma FN7957 Rev 3. Page 4 of 22 May 9, 26

5 ISL728SEH, ISL728SRH Electrical Specifications V S ±5V, V CM =, V O = V, R L = Open, T A =, unless otherwise noted. Boldface limits apply across the operating temperature range, to +25 C. (Continued) SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT I S- Sink Current Capability ma V SUPPLY Supply Voltage Range Guaranteed by PSRR 3 4 V AC SPECIFICATIONS GBW Gain Bandwidth Product A CL =, V OUT = mv P-P ; R L = 2k 4 MHz e np-p Voltage Noise.Hz to Hz, V S = ±8V 3 nv P-P e n Voltage Noise Density f = Hz, V S = ±8V 8.5 nv/ Hz e n Voltage Noise Density f = Hz, V S = ±8V 5.8 nv/ Hz e n Voltage Noise Density f = khz, V S = ±8V 5.6 nv/ Hz e n Voltage Noise Density f = khz, V S = ±8V 5.6 nv/ Hz in Current Noise Density f = khz, V S = ±8V 355 fa/ Hz THD + N Total Harmonic Distortion + Noise khz, G =, V O = 3.5V RMS, R L = kω.3 % TRANSIENT RESPONSE SR Slew Rate A V =, R L = 2kΩ, V O = V P-P ±. ±.2 V/µs ±.4 V/µs t r, t f, Small Signal Rise Time % to 9% of V OUT A V =, V OUT = mv P-P, R f = Ω, 2 ns R L =2kΩ to V CM 4 ns Fall Time 9% to % of V OUT t s Settling Time to.% V Step; % to V OUT A V =, V OUT = mv P-P, R f = Ω 23 ns R L = 2kΩ to V CM 4 ns A V =, V OUT = V P-P, R f = Ω 8.5 µs R L =2kΩ to V CM OS+ Positive Overshoot A V =, V OUT = V P-P, R f = Ω 5 % R L =2kΩ to V CM 35 % OS- Negative Overshoot A V =, V OUT = V P-P, R f = Ω 5 % R L =2kΩ to V CM 35 % Electrical Specifications V S ±5V, V CM =, V O = V, R L = Open, T A =, unless otherwise noted. Boldface limits apply over a total ionizing dose of krad(si) with exposure at a high dose rate of 5-3krad(Si)/s; and over a total ionizing dose of 5krad(Si) with exposure at a low dose rate of <mrad(si)/s. SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT V OS Offset Voltage 4 23 µv 29 µv TCV OS Offset Voltage Drift.3.4 µv/ C V OS Input Offset Voltage Match Channel-to-Channel µv 365 µv I OS Input Offset Current na na I B Input Bias Current na -5 na FN7957 Rev 3. Page 5 of 22 May 9, 26

6 ISL728SEH, ISL728SRH Electrical Specifications V S ±5V, V CM =, V O = V, R L = Open, T A =, unless otherwise noted. Boldface limits apply over a total ionizing dose of krad(si) with exposure at a high dose rate of 5-3krad(Si)/s; and over a total ionizing dose of 5krad(Si) with exposure at a low dose rate of <mrad(si)/s. (Continued) SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT V CMIR Common-Mode Input Voltage Range Guaranteed by CMRR Test (V - ) -.5 (V + ) -.8 V V - (V + ) -.8 V CMRR Common-Mode Rejection Ratio V CM = V - to V + -.8V 8 db V CM = V - to V + -.8V 97 db PSRR Power Supply Rejection Ratio V S = 3V to 4V, V CMIR = Valid Input Voltage 5 24 db db A VOL Open-Loop Gain R L = kω to ground V O = -3V to +3V 2 3 db 5 db V OH Output Voltage High, V + to V OUT R L = kω mv 2 mv V OL Output Voltage Low, V OUT to V - R L = kω 7 mv 8 mv I S Supply Current/Amplifier.85. ma.4 ma I S+ Source Current Capability ma I S- Sink Current Capability ma V SUPPLY Supply Voltage Range Guaranteed by PSRR 3 4 V AC SPECIFICATIONS GBW Gain Bandwidth Product A CL =, V OUT = mv P-P ; R L = 2kΩ 4 MHz e np-p Voltage Noise.Hz to Hz, V S = ±8V 3 nv P-P e n Voltage Noise Density f = Hz, V S = ±8V 8.5 nv/ Hz e n Voltage Noise Density f = Hz, V S = ±8V 5.8 nv/ Hz e n Voltage Noise Density f = khz, V S = ±8V 5.6 nv/ Hz e n Voltage Noise Density f = khz, V S = ±8V 5.6 nv/ Hz in Current Noise Density f = khz, V S = ±8V 355 fa/ Hz THD + N Total Harmonic Distortion + Noise khz, G =, V O = 3.5V RMS, R L = kω.3 % TRANSIENT RESPONSE SR Slew Rate A V =, R L = 2kΩ, V O = V P-P ±. ±.2 V/µs ±.4 V/µs t r, t f, Small Signal Rise Time % to 9% of V OUT A V =, V OUT = mv P-P, R f = Ω, 23 ns R L =2kΩ to V CM 4 ns Fall Time 9% to % of V OUT A V =, V OUT = mv P-P, R f = Ω, 2 ns R L = 2kΩ to V CM 4 ns t s Settling Time to.% V Step; % to V OUT A V =, V OUT = V P-P, R f = Ω 8.5 µs R L =2kΩ to V CM OS+ Positive Overshoot A V =, V OUT = V P-P, R f = Ω 5 % R L =2kΩ to V CM 35 % FN7957 Rev 3. Page 6 of 22 May 9, 26

7 ISL728SEH, ISL728SRH Electrical Specifications V S ±5V, V CM =, V O = V, R L = Open, T A =, unless otherwise noted. Boldface limits apply over a total ionizing dose of krad(si) with exposure at a high dose rate of 5-3krad(Si)/s; and over a total ionizing dose of 5krad(Si) with exposure at a low dose rate of <mrad(si)/s. (Continued) SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OS- Negative Overshoot A V =, V OUT = V P-P, R f = Ω 5 % R L =2kΩ to V CM 35 % Electrical Specifications V S ±5V, V CM =, V O = V, T A =, unless otherwise noted. Boldface limits apply over the operating temperature range, to +25 C. SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT V OS Offset Voltage 4 µv V OS Input Offset Voltage Match Channel to Channel 44 µv I OS Input Offset Current 4 na I B Input Bias Current -23 na V CMIR Common-Mode Input Voltage Range Guaranteed by CMRR Test (V - ) -.5 (V + ) -.8 V V - (V + ) -.8 V CMRR Common-Mode Rejection Ratio V CM = V - -.5V to V V CM = V - to V + -.8V PSRR Power Supply Rejection Ratio V S = 3V to 4V, V CMIR = Valid Input Voltage A VOL Open-Loop Gain R L = kω to ground V O = -3V to +3V 7 db 24 db 3 db V OH Output Voltage High, V + to V OUT R L = kω 65 mv 7 mv V OL Output Voltage Low, R L = kω 38 mv V OUT to V - 45 mv I S Supply Current/Amplifier.85 ma I S+ Source Current Capability 8 ma I S- Sink Current Capability 8 ma AC SPECIFICATIONS GBW Gain Bandwidth Product 3.2 MHz e np-p Voltage Noise.Hz to Hz 32 nv P-P e n Voltage Noise Density f = Hz 9 nv/ Hz e n Voltage Noise Density f = Hz 5.7 nv/ Hz e n Voltage Noise Density f = khz 5.5 nv/ Hz e n Voltage Noise Density f = khz 5.5 nv/ Hz in Current Noise Density f = khz 38 fa/ Hz THD + N Total Harmonic Distortion + Noise khz, G =, V O =.25V RMS, R L =kω.3 % TRANSIENT RESPONSE SR Slew Rate A V =, R L = 2kΩ V O = 4V P-P ± V/µs FN7957 Rev 3. Page 7 of 22 May 9, 26

8 ISL728SEH, ISL728SRH Electrical Specifications V S ±5V, V CM =, V O = V, T A =, unless otherwise noted. Boldface limits apply over the operating temperature range, to +25 C. (Continued) SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT t r, t f, Small Signal Rise Time % to 9% of V OUT AV =, V OUT = mv P-P, R f = Ω, R L =2kΩ to V CM ns Fall Time 9% to % of V OUT A V =, V OUT = mv P-P, R f = Ω, R L = 2kΩ to V CM ns t s Settling Time to.% 4V Step; % to V OUT A V =, V OUT = 4V P-P, R f = Ω 4 µs R L =2kΩ to V CM OS+ Positive Overshoot A V =, V OUT = V P-P, R f = Ω R L =2kΩ to V CM 5 % OS- Negative Overshoot A V =, V OUT = V P-P, R f = Ω R L =2kΩ to V CM 5 % NOTE: 6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. High Dose Rate Post Radiation Characteristics V S ±5V, V CM = V, V O = V, R L = Open, T A =, unless otherwise noted. This data is typical test data post radiation exposure at a rate of 5 to 3rad(Si)/s. This data is intended to show typical parameter shifts due to high dose rate radiation. These are not limits nor are they guaranteed. SYMBOL PARAMETER TEST CONDITIONS 5k RAD 75k RAD k RAD UNIT V OS Offset Voltage µv I OS Input Offset Current na I B Input Bias Current na CMRR Common-Mode Rejection Ration V CM = -3V to +3V db PSRR Power Supply Rejection Ratio V S = ±2.25V to ±5V db A VOL Open-Loop Gain V O = -3V to +3V R L = kω to ground db V OH V OL Output Voltage High R L = kω to ground mv V + to V OUT Output Voltage Low R L = kω to ground mv V OUT to V - I S Supply Current/Amplifier µa TRANSIENT RESPONSE SR Slew Rate A V =, R L = 2kΩ V O = 4V P-P V/µs Low Dose Rate Post Radiation Characteristics V S ±5V, V CM = V, V O = V, R L = Open, T A =, unless otherwise noted. This data is typical test data post radiation exposure at a rate of mrad(si)/s. This data is intended to show typical parameter shifts due to low dose rate radiation. These are not limits nor are they guaranteed. SYMBOL PARAMETER TEST CONDITIONS k RAD 2k RAD 5k RAD UNIT V OS Offset Voltage µv I OS Input Offset Current 6 8 na I B Input Bias Current na I S Supply Current/Amplifier µa FN7957 Rev 3. Page 8 of 22 May 9, 26

9 V OS (µv) ISL728SEH, ISL728SRH Typical Performance Curves, V CM = V, R L = Open, T A =, unless otherwise specified TEMPERATURE ( C) FIGURE 3. V OS vs TEMPERATURE V OS (µv) C +25 C INPUT COMMON-MODE VOLTAGE (V) FIGURE 4. INPUT OFFSET VOLTAGE vs INPUT COMMON-MODE VOLTAGE, I BIAS (na) V S (V) I BIAS (na) -5 V S = +4V -2 V S = +3V V S = +3.V V S = +4.5V V S = +V TEMPERATURE ( C) FIGURE 5. I BIAS vs V S FIGURE 6. I BIAS vs TEMPERATURE vs SUPPLY CMRR (db) CHANNEL-A CHANNEL-B TEMPERATURE ( C) FIGURE 7. CMRR vs TEMPERATURE, FIGURE 8. CMRR vs TEMPERATURE, CMRR (db) CHANNEL-A CHANNEL-B TEMPERATURE ( C) FN7957 Rev 3. Page 9 of 22 May 9, 26

10 GAIN (db) PSRR (db) PSRR (db) GAIN (db) ISL728SEH, ISL728SRH Typical Performance Curves, V CM = V, R L = Open, T A =, unless otherwise specified. (Continued) CMRR (db) SIMULATION m.. k k k M M M G TEMPERATURE ( C) FIGURE 9. CMRR vs FREQUENCY, FIGURE. PSRR vs TEMPERATURE, PSRR (db) PSRR A V = 2 R L = k PSRR- V CM = V P-P - k k k M M PSRR A V = 2 R L = k PSRR- V CM = V P-P - k k k M M FIGURE. PSRR vs FREQUENCY, FIGURE 2. PSRR vs FREQUENCY, R L = MΩ GAIN m.. k k k M MM G PHASE FIGURE 3. OPEN-LOOP GAIN, PHASE vs FREQUENCY, 7 R A CL = F = kω, R G = Ω 6 R F = kω, R G = Ω 5 V A CL = S = ±5V & ±5V 4 R L = 2k 3 V OUT = mv P-P A CL = 2 R F = kω, R G = kω A CL = R F =, R G = - k k k M M FIGURE 4. FREQUENCY RESPONSE vs CLOSED LOOP GAIN FN7957 Rev 3. Page of 22 May 9, 26

11 ISL728SEH, ISL728SRH Typical Performance Curves, V CM = V, R L = Open, T A =, unless otherwise specified. (Continued) NORMALIZED GAIN (db) A V = + V OUT = mv p-p k R L = OPEN, k, k k R L = k R L = 499 R L = R L = 49.9 k M M NORMALIZED GAIN (db) A V = + V OUT = mv p-p k R L = OPEN, k, k k R L = k R L = 499 R L = R L = 49.9 k M M FIGURE 5. GAIN vs FREQUENCY vs R L, FIGURE 6. GAIN vs FREQUENCY vs R L, NORMALIZED GAIN (db) V -6 S = ±5V -7 A V = + -8 R L = INF -9 k V OUT = mv P-P V OUT = 5mV P-P V OUT = mv P-P V OUT = 5mV P-P V OUT = V P-P k k M M NORMALIZED GAIN (db) V S = ±.5V R L = k A V = + -8 V OUT = mv P-P -9 k k k M M FIGURE 7. GAIN vs FREQUENCY vs OUTPUT VOLTAGE FIGURE 8. GAIN vs FREQUENCY vs SUPPLY VOLTAGE V OH AND V OL (mv) R L = k V OH V OL TEMPERATURE ( C) FIGURE 9. OUTPUT OVERHEAD VOLTAGE vs TEMPERATURE,, R L =k V OH AND V OL (mv) R L = k V OH TEMPERATURE ( C) V OL FIGURE 2. OUTPUT OVERHEAD VOLTAGE vs TEMPERATURE,, R L =k FN7957 Rev 3. Page of 22 May 9, 26

12 V + - V OH (V) V OL - V - (V) ISL728SEH, ISL728SRH Typical Performance Curves, V CM = V, R L = Open, T A =, unless otherwise specified. (Continued). AND ±5V. AND ±5V. +25 C. +25 C LOAD CURRENT (ma) FIGURE 2. OUTPUT OVERHEAD VOLTAGE HIGH vs LOAD CURRENT, AND ±5V..... LOAD CURRENT (ma) FIGURE 22. OUTPUT OVERHEAD VOLTAGE LOW vs LOAD CURRENT, V S = ±5V AND ±5V 5 5 V OH V OL A V = 2 R F = R G = k V IN = ±7.5V-DC C 6 8 C 2 4 I-FORCE (ma) +25 C +75 C V OH V OL 4 3 A V = 2 R F = R G = k +25 C 2 V IN = ±2.5V-DC +75 C C C I-FORCE (ma) FIGURE 23. OUTPUT VOLTAGE SWING vs LOAD CURRENT, FIGURE 24. OUTPUT VOLTAGE SWING vs LOAD CURRENT, CURRENT (µa) V S = ±2V V S = ±2.25V TEMPERATURE ( C) FIGURE 25. SUPPLY CURRENT vs TEMPERATURE vs SUPPLY VOLTAGE I SUPPLY PER AMPLIFIER (µa) V SUPPLY (V) FIGURE 26. SUPPLY CURRENT vs SUPPLY VOLTAGE FN7957 Rev 3. Page 2 of 22 May 9, 26

13 ISL728SEH, ISL728SRH Typical Performance Curves, V CM = V, R L = Open, T A =, unless otherwise specified. (Continued) INPUT NOISE VOLTAGE (nv/ Hz) V S = ±8V INPUT NOISE CURRENT (fa/ Hz) INPUT NOISE VOLTAGE (nv/ Hz) INPUT NOISE CURRENT (fa/ Hz) INPUT NOISE VOLTAGE INPUT NOISE VOLTAGE INPUT NOISE CURRENT INPUT NOISE CURRENT... k k k FIGURE 27. INPUT NOISE VOLTAGE (en) AND CURRENT (in) vs FREQUENCY, V S = ±8V... k k k FIGURE 28. INPUT NOISE VOLTAGE (en) AND CURRENT (in) vs FREQUENCY, INPUT NOISE VOLTAGE (nv) V S = ±8V A V = k TIME (s) INPUT NOISE VOLTAGE (nv) A V = k TIME (s) FIGURE 29. INPUT NOISE VOLTAGE.Hz TO Hz, V S = ±8V FIGURE 3. INPUT NOISE VOLTAGE.Hz TO Hz, THD + N (%). R L = 2k V OUT = V P-P. C-WEIGHTED 22Hz TO 5kHz A V = +25 C THD + N (%). R L = k V OUT = V P-P. C-WEIGHTED 22Hz TO 5kHz A V = +25 C C A V =. k k k FIGURE 3. THD+N vs FREQUENCY vs TEMPERATURE, A V =,, R L = 2k +25 C A V =. k k k FIGURE 32. THD+N vs FREQUENCY vs TEMPERATURE, A V =,, R L = k FN7957 Rev 3. Page 3 of 22 May 9, 26

14 V OUT (V) V OUT (V) V OUT (V) ISL728SEH, ISL728SRH Typical Performance Curves, V CM = V, R L = Open, T A =, unless otherwise specified. (Continued) THD + N (%)... R L = 2k f = khz C-WEIGHTED 22Hz TO 22kHz A V = +25 C THD + N (%)... R L = k f = khz C-WEIGHTED 22Hz TO 22kHz A V = +25 C.. A V =. +25 C V OUT (V P-P ) FIGURE 33. THD+N vs OUTPUT VOLTAGE (V OUT ) vs TEMPERATURE, A V =,, R L = 2k. +25 C A V = V OUT (V P-P ) FIGURE 34. THD+N vs OUTPUT VOLTAGE (V OUT ) vs TEMPERATURE, A V =,, R L = k A V = R L = 2k TIME (µs) A V = R L = 2k TIME (µs) FIGURE 35. LARGE SIGNAL V STEP RESPONSE, FIGURE 36. LARGE SIGNAL 4V STEP RESPONSE, TIME (µs) FIGURE 37. SMALL SIGNAL TRANSIENT RESPONSE,, ±5V AND A V = R L = 2k INPUT AND OUTPUT (V) V IN = ±5.9V INPUT OUTPUT TIME (ms) FIGURE 38. NO PHASE REVERSAL FN7957 Rev 3. Page 4 of 22 May 9, 26

15 Z OUT (Ω) Z OUT (Ω) INPUT (mv) OUTPUT (V) INPUT (mv) OUTPUT (V) INPUT (mv) OUTPUT (V) INPUT (mv) ISL728SEH, ISL728SRH Typical Performance Curves, V CM = V, R L = Open, T A =, unless otherwise specified. (Continued) INPUT OUTPUT 2 A V = R L = k 6 V IN = mv P-P OVERDRIVE = V INPUT -4-8 OUTPUT (V) TIME (µs) FIGURE 39. POSITIVE OUTPUT OVERLOAD RESPONSE TIME, OUTPUT -6 A V = R L = k -6 V IN = mv P-P -2 OVERDRIVE = V TIME (µs) FIGURE 4. NEGATIVE OUTPUT OVERLOAD RESPONSE TIME, INPUT OUTPUT 6 A V = R 5 L = k V IN = 5mV P-P OVERDRIVE = V OUTPUT TIME (µs) FIGURE 4. POSITIVE OUTPUT OVERLOAD RESPONSE TIME, INPUT A V = -5 R L = k V IN = 5mV P-P -5 OVERDRIVE = V TIME (µs) FIGURE 42. NEGATIVE OUTPUT OVERLOAD RESPONSE TIME, A V = A V = A V = A V =. A V =. A V =.. k k k M M k k k M M FIGURE 43. OUTPUT IMPEDANCE vs FREQUENCY, FIGURE 44. OUTPUT IMPEDANCE vs FREQUENCY, FN7957 Rev 3. Page 5 of 22 May 9, 26

16 I SC (ma) ISL728SEH, ISL728SRH Typical Performance Curves, V CM = V, R L = Open, T A =, unless otherwise specified. (Continued) OVERSHOOT (%) V OUT = mv P-P A V = A V = - A V = OVERSHOOT (%) V OUT = mv P-P A V = A V = - A V = LOAD CAPACITANCE (nf) LOAD CAPACITANCE (nf) FIGURE 45. OVERSHOOT vs CAPACITIVE LOAD, FIGURE 46. OVERSHOOT vs CAPACITIVE LOAD, V OUT (V P-P ) A V = k k k M R L = k I SC -SINK I SC -SOURCE TEMPERATURE ( C) FIGURE 47. I MAX OUTPUT VOLTAGE vs FREQUENCY FIGURE 48. SHORT-CIRCUIT CURRENT vs TEMPERATURE, FN7957 Rev 3. Page 6 of 22 May 9, 26

17 ISL728SEH, ISL728SRH Applications Information Functional Description The ISL728SEH, ISL728SRH are dual, 3.2MHz, single or dual supply, rail-to-rail output amplifiers with a common-mode input voltage range extending to a range of.5v below the V - rail. The input stage is optimized for precision sensing of ground-referenced signals in single-supply applications. The input stage is able to handle large input differential voltages without phase inversion, making this amplifier suitable for high-voltage comparator applications. The bipolar design features high open loop gain and excellent DC input and output temperature stability. This op amp features very low quiescent current of 85µA, and low temperature drift. The devices are fabricated in a new precision 4V complementary bipolar DI process and is immune from latch-up for up to a 36V supply range. Operating Voltage Range The op amps are designed to operate over a single supply range of 3V to 36V or a split supply voltage range of +.8V/-.2V to ±8V. The device is fully characterized at 3V (±5V). Both DC and AC performance remain virtually unchanged over the complete operating voltage range. Parameter variation with operating voltage is shown in the Typical Performance Curves beginning on page 9. The input common-mode voltage to the V + rail (V + -.8V across the full temperature range) may limit amplifier operation when operating from split V + and V - supplies. Figure 4 shows the common-mode input voltage range variation over temperature. Input Stage Performance The ISL728SEH, ISL728SRH PNP input stage has a common-mode input range extending up to.5v below ground at. Full amplifier performance is guaranteed for input voltage down to ground (V - ) across the to +25 C temperature range. For common-mode voltages down to -.5V below ground (V - ), the amplifiers are fully functional, but performance degrades slightly over the full temperature range. This feature provides excellent CMRR, AC performance, and DC accuracy when amplifying low-level, ground-referenced signals. The input stage has a maximum input differential voltage equal to a diode drop greater than the supply voltage and does not contain the back-to-back input protection diodes found on many similar amplifiers. This feature enables the device to function as a precision comparator by maintaining very high input impedance for high-voltage differential input comparator voltages. The high differential input impedance also enables the device to operate reliably in large signal pulse applications, without the need for anti-parallel clamp diodes required on MOSFET and most bipolar input stage op amps. Thus, input signal distortion caused by nonlinear clamps under high slew rate conditions is avoided. In applications in which one or both amplifier input terminals are at risk of exposure to voltages beyond the supply rails, current-limiting resistors may be needed at each input terminal (see Figure 49, R IN+, R IN-) to limit current through the power-supply ESD diodes to 2mA. V IN- V IN+ R IN- R IN+ R G FIGURE 49. INPUT ESD DIODE CURRENT LIMITING Output Drive Capability The bipolar rail-to-rail output stage features low saturation levels that enable an output voltage swing to less than 5mV when the total output load (including feedback resistance) is held below 5µA (Figures 2 and 22). With ±5V supplies, this can be achieved by using feedback resistor values >3kΩ. The output stage is internally current limited. Output current limit over temperature is shown in Figures 23 and 24. The amplifiers can withstand a short-circuit to either rail as long as the power dissipation limits are not exceeded. This applies to only one amplifier at a time for the dual op amp. Continuous operation under these conditions may degrade long-term reliability. The amplifiers perform well when driving capacitive loads (Figures 45 and 46). The unity gain, voltage follower (buffer) configuration provides the highest bandwidth but is also the most sensitive to ringing produced by load capacitance found in BNC cables. Unity gain overshoot is limited to 35% at capacitance values to.33nf. At gains of and higher, the device is capable of driving more than nf without significant overshoot. Output Phase Reversal Output phase reversal is a change of polarity in the amplifier transfer function when the input voltage exceeds the supply voltage. The ISL728SEH, ISL728SRH are immune to output phase reversal out to.5v beyond the rail (V ABS MAX ) limit (see Figure 38 on page 4). Single Channel Usage - + V + V - The ISL728SEH, ISL728SRH are dual op amps. If the application requires only one channel, the user must configure the unused channel to prevent it from oscillating. The unused channel oscillates if the input and output pins are floating. This results in higher-than-expected supply currents and possible noise injection into the channel being used. The proper way to prevent oscillation is to short the output to the inverting input, and ground the positive input (Figure 5). - + FIGURE 5. PREVENTING OSCILLATIONS IN UNUSED CHANNELS R F R L FN7957 Rev 3. Page 7 of 22 May 9, 26

18 ISL728SEH, ISL728SRH Power Dissipation It is possible to exceed the +5 C maximum junction temperatures under certain load and power supply conditions. It is therefore important to calculate the maximum junction temperature (T JMAX ) for all applications to determine if power supply voltages, load conditions, or package type need to be modified to remain in the safe operating area. These parameters are related using Equation : T JMAX = T MAX + JA xpd MAXTOTAL (EQ. ) Where P DMAXTOTAL is the sum of the maximum power dissipation of each amplifier in the package (PD MAX ) T MAX = Maximum ambient temperature Θ JA = Thermal resistance of the package PD MAX for each amplifier can be calculated using Equation 2: V OUTMAX PD MAX = V S I qmax + V S - V OUTMAX (EQ. 2) R L Where PD MAX = Maximum power dissipation of one amplifier V S = Total supply voltage I qmax = Maximum quiescent supply current of one amplifier V OUTMAX = Maximum output voltage swing of the application R L = Load resistance FN7957 Rev 3. Page 8 of 22 May 9, 26

19 ISL728SEH, ISL728SRH Package Characteristics Weight of Packaged Device. 429 grams (Typical) Lid Characteristics Finish: Gold Case Isolation to Any Lead: 2 x 9 Ω (min) Die Characteristics Die Dimensions 565µm x 225µm (62 mils x 84 mils) Thickness: 355µm ±25µm (4 mils ± mil) Interface Materials GLASSIVATION Type: Nitrox Thickness: 5kÅ Metallization Mask Layout TOP METALLIZATION Type: AlCu (99.5%/.5%) Thickness: 3kÅ BACKSIDE FINISH Silicon PROCESS Dielectrically Isolated Complementary Bipolar - PR4 ASSEMBLY RELATED INFORMATION SUBSTRATE POTENTIAL Floating ADDITIONAL INFORMATION WORST CASE CURRENT DENSITY < 2 x 5 A/cm 2 V + OUT_A -IN_A PLACE HOLDER OUT_B -IN_B +IN_A +IN_B V - FN7957 Rev 3. Page 9 of 22 May 9, 26

20 ISL728SEH, ISL728SRH TABLE. DIE LAYOUT X-Y COORDINATES PAD NAME PAD NUMBER X (µm) Y (µm) dx (µm) dy (µm) BOND WIRES PER PAD OUT_A IN_A IN_A V IN_B IN_B OUT_B V NOTE: 7. Origin of coordinates is the centroid of pad 8. FN7957 Rev 3. Page 2 of 22 May 9, 26

21 ISL728SEH, ISL728SRH Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest revision. DATE REVISION CHANGE May 9, 26 FN Added ISL728SRH information to datasheet. Removed Pb-Free Reflow Profile information from Thermal Information section as it is not applicable to hermetic packages. July 24, 24 FN Updated Features on page, Radiation Tolerance bullet as follows: from Radiation Tolerance - SEL/SEB LET TH (V S = ±8V) MeV*cm 2 /mg - High Dose Rate krad(si) - Low Dose Rate krad(si) to Radiation tolerance - High dose rate (5-3rad(Si)/s) krad(si) - Low dose rate (.rad(si)/s) krad(si)* - SEB LET TH (V S = ±8V) MeV cm 2 /mg - SEL Immune (SOI Process) Updated the Ordering Information table on page 3 as follows: - Removed MSL note. - Added SMD ordering note. Replaced the Products verbiage with the About Intersil Verbiage on page 2. August 24, 22 FN Electrical Specification tables (pages 3-6), added specs on overshoot and rise/fall times. 2. Page 3 - Added Abs Max in a non radiation environment Changed ESD HBM from 3kV to 2kV Changed ESD CDM from 2kV to 75V February 6, 22 FN7957. Initial Release About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at You may report errors or suggestions for improving this datasheet by visiting Reliability reports are also available from our website at Copyright Intersil Americas LLC All Rights Reserved.All trademarks and registered trademarks are the property of their respective owners. For additional products, see Intersil products are manufactured, assembled and tested utilizing ISO9 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see FN7957 Rev 3. Page 2 of 22 May 9, 26

22 ISL728SEH, ISL728SRH Ceramic Metal Seal Flatpack Packages (Flatpack) -Hb A e -A-.4 M H A - B Q SEATING AND BASE PLANE L M c S E3 D S PIN NO. ID AREA E E E2 LEAD FINISH BASE METAL b (b) SECTION A-A.36 M H A - B NOTES:. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer s identification shall not be used as a pin one identification mark. Alternately, a tab (dimension k) may be used to identify pin one. 2. If a pin one identification mark is used in addition to a tab, the limits of dimension k do not apply. 3. This dimension allows for off-center lid, meniscus, and glass overrun. 4. Dimensions b and c apply to lead base metal only. Dimension M applies to lead plating and finish thickness. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 5. N is the maximum number of terminal positions. 6. Measure dimension S at all four corners. 7. For bottom-brazed lead packages, no organic or polymeric materials shall be molded to the bottom of the package to cover the leads. 8. Dimension Q shall be measured at the point of exit (beyond the meniscus) of the lead from the body. Dimension Q minimum shall be reduced by.5 inch (.38mm) maximum when solder dip lead finish is applied. 9. Dimensioning and tolerancing per ANSI Y4.5M Controlling dimension: INCH. M E3 (c) L C S S A A D S -D- -C- -B- D K.A MIL-STD-835 CDFP3-F (F-4A, CONFIGURATION B) LEAD CERAMIC METAL SEAL FLATPACK PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A b b c c D E E E E e.5 BSC.27 BSC - k L Q S M N - Rev. 3/7 FN7957 Rev 3. Page 22 of 22 May 9, 26