DATASHEET HA Features. Applications. Ordering Information. 110MHz, High Slew Rate, High Output Current Buffer. FN2921 Rev 12.

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1 DATASHEET HA-52 MHz, High Slew Rate, High Output Current Buffer The HA-52 is a monolithic, wideband, high slew rate, high output current, buffer amplifier. Utilizing the advantages of the Intersil D.I. technologies, the HA-52 current buffer offers V/ s slew rate with MHz of bandwidth. The 2mA output current capability is enhanced by a output impedance. The monolithic HA-52 will replace the hybrid LH2 with corresponding performance increases. These characteristics range from the k input impedance to the increased output voltage swing. Monolithic design technologies have allowed a more precise buffer to be developed with more than an order of magnitude smaller gain error. The HA-52 will provide many present hybrid users with a higher degree of reliability and at the same time increase overall circuit performance. For the military grade product, refer to the HA-52/ datasheet. Features FN292 Rev 2. Voltage gain High input impedance k Low output impedance Very high slew rate V/ s Very wide bandwidth MHz High output current 2mA Pulsed output current mA Monolithic construction Pb-Free available (RoHS Compliant) Applications Line driver Data acquisition MHz buffer Radar cable driver High power current booster High power current source Sample and holds Video products Ordering Information PART NUMBER PART MARKG TEMP. RANGE ( C) PACKAGE PKG. DWG. # HA HA to +25 Pin Metal Can T.C HA4P52-5Z (Note ) HA4P 52-5Z to +5 2 Ld PLCC (Pb-free) N2.5 HA9P52-5Z (Note ) 52 5Z to +5 Ld SOIC (Pb-free) M.5 HA9P52-9Z (Note ) 52 9Z -4 to +5 Ld SOIC (Pb-free) M.5 NOTE:. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and % matte tin plate plus anneal (e termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD- 2. FN292 Rev 2. Page of 2

2 Pinouts HA-52 ( LD SOIC) TOP VIEW HA-52 (2 LD PLCC) TOP VIEW HA-52 ( P METAL CAN) TOP VIEW V 2-2 V 2 + V V 2 + V V NOTE: Case Voltage = Floating V - V - V FN292 Rev 2. Page 2 of 2

3 Absolute Maximum Ratings Voltage Between V+ and V- Terminals V Input Voltage to V - Output Current (Continuous) mA Output Current (5ms On, s Off) mA Operating Conditions Temperature Range HA C to +25 C HA C to +5 C HA C to +5 C Thermal Information Thermal Resistance JA ( C/W) JC ( C/W) Metal Can Package (Notes, 4) PLCC Package (Note ) N/A SOIC Package (Note ) N/A Max Junction Temperature (Hermetic Packages, Note 2) C Max Junction Temperature (Plastic Packages, Note 2) C Max Storage Temperature Range C to +5 C Max Lead Temperature (Soldering s) C (PLCC and SOIC - Lead Tips Only) CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. 2. Maximum power dissipation, including load conditions, must be designed to maintain the maximum junction temperature below +5 C for the can packages, and below +5 C for the plastic packages.. For JA is measured with the component mounted on an evaluation PC board in free air. 4. For JC, the case temp location is the center of the exposed metal pad on the package underside. Electrical Specifications V SUPPLY = 2V to 5V, R S = 5, R L = k C L = pf, Unless Otherwise Specified TEST TEMP HA-52-2 HA-52-5, -9 PARAMETER CONDITIONS ( C) M TYP MAX M TYP MAX UNITS PUT CHARACTERISTICS Offset Voltage mv Full - - mv Average Offset Voltage Drift Full V/ C Bias Current A Full A Input Resistance Full M Input Noise Voltage Hz-MHz V P-P TRANSFER CHARACTERISTICS Voltage Gain R L = V/V (V = V) R L = V/V R L = k V/V R L = k Full V/V -db Bandwidth V = V P-P MHz AC Current Gain A/mA PUT CHARACTERISTICS Output Voltage Swing R L = V R L = k, V S = 5V Full V R L = k, V S = 2V Full V Output Current V = V, R L = ma Output Resistance Full - - Harmonic Distortion V = V RMS, f = khz 25 - < <.5 - % TRANSIENT RESPONSE Full Power Bandwidth (Note 5) MHz Rise Time ns Propagation Delay ns Overshoot % Slew Rate V/ns Settling Time To.% ns Differential Gain R L = % Differential Phase R L = FN292 Rev 2. Page of 2

4 Electrical Specifications V SUPPLY = 2V to 5V, R S = 5, R L = k C L = pf, Unless Otherwise Specified (Continued) TEST TEMP HA-52-2 HA-52-5, -9 PARAMETER CONDITIONS ( C) M TYP MAX M TYP MAX UNITS POWER REQUIREMENTS Supply Current ma Full ma Power Supply Rejection Ratio A V = V Full db NOTE: 5. Slew Rate FPBW = ;V 2 V P =V PEAK Test Circuit and Waveforms R S +5V V 2 + V - V V R L FIGURE. LARGE AND SMALL SIGNAL RESPONSE V V V V R S = 5, R L = SMALL SIGNAL WAVEFORMS R S = 5, R L = k SMALL SIGNAL WAVEFORMS V V V V R S = 5, R L = LARGE SIGNAL WAVEFORMS R S = 5, R L = k LARGE SIGNAL WAVEFORMS FN292 Rev 2. Page 4 of 2

5 Q 5 Q 2 HA-52 Schematic Diagram R 9 R R N Q 9 R 4 R V 2 + R Q 25 Q Q 2 2 Q Q Q 2 Q 9 Q 2 Q Q Q R 5 Q Q 4 R Q 2 R N2 Q 5 Q Q 22 Q 2 Q R Q 24 R Q Q Q Q 4 V 2 - R 2 R R 2 R N V - Application Information Layout Considerations The wide bandwidth of the HA-52 necessitates that high frequency circuit layout procedures be followed. Failure to follow these guidelines can result in marginal performance. Probably the most crucial of the RF/video layout rules is the use of a ground plane. A ground plane provides isolation and minimizes distributed circuit capacitance and inductance which will degrade high frequency performance. Other considerations are proper power supply bypassing and keeping the input and output connections as short as possible which minimizes distributed capacitance and reduces board space. Power Supply Decoupling For optimal device performance, it is recommended that the positive and negative power supplies be bypassed with capacitors to ground. Ceramic capacitors ranging in value from. to. F will minimize high frequency variations in supply voltage, while low frequency bypassing requires larger valued capacitors since the impedance of the capacitor is dependent on frequency. It is also recommended that the bypass capacitors be connected close to the HA-52 (preferably directly to the supply pins). Operation at Reduced Supply Levels The HA-52 can operate at supply voltage levels as low as 5V and lower. Output swing is directly affected as well as slight reductions in slew rate and bandwidth. Short Circuit Protection The output current can be limited by using the following circuit: V+ I MAX = 2mA R LIM V+ V- = = I (CONTUOUS) MAX I MAX Capacitive Loading The HA-52 will drive large capacitive loads without oscillation but peak current limits should not be exceeded. Following the formula I = Cdv/dt implies that the slew rate or the capacitive load must be controlled to keep peak current below the maximum or use the current limiting approach as shown. The HA-52 can become unstable with small capacitive loads (5pF) if certain precautions are not taken. Stability is enhanced by any one of the following: a source resistance in series with the input of 5 to k ; increasing capacitive load to 5pF or greater; decreasing C LOAD to 2pF or less; adding an output resistor of to 5 ; or adding feedback capacitance of 5pF or greater. Adding source resistance generally yields the best results. V - V- R LIM V 2 + V 2 - R LIM FN292 Rev 2. Page 5 of 2

6 .. MAXIMUM POWER DISSIPATION (W) CAN SOIC PLCC QUIESCENT POWER DISSIPATION AT 5V SUPPLIES T JMAX T A P DMAX = JC + CS + SA Where: T JMAX = Maximum Junction Temperature of the Device T A = Ambient JC = Junction to Case Thermal Resistance CS = Case to Heat Sink Thermal Resistance SA = Heat Sink to Ambient Thermal Resistance Graph is based on: T JMAX T A P DMAX = JA FIGURE 2. MAXIMUM POWER DISSIPATION vs TEMPERATURE Typical Application +2V V 2 + R S R M RG -5 V V 5 V - V V 5 V R L 5 V FIGURE. COAXIAL CABLE DRIVER - 5 SYSTEM Typical Performance Curves 9 V S = 5V, R S = 5 9 V S = 5V, R S = 5 VOLTAGE GA (db) GA PHASE PHASE SHIFT VOLTAGE GA (db) GA PHASE PHASE SHIFT - FREQUEY (MHz) - FREQUEY (MHz) FIGURE 4. GA/PHASE vs FREQUEY (R L = k ) FIGURE 5. GA/PHASE vs FREQUEY (R L = 5 ) FN292 Rev 2. Page of 2

7 Typical Performance Curves (Continued) VOLTAGE GA (V/V) V S = 5V V = -V TO +V VOLTAGE GA (V/V) V S = 5V V = TO +V V = TO -V FIGURE. VOLTAGE GA vs TEMPERATURE (R L = ) FIGURE. VOLTAGE GA vs TEMPERATURE (R L = k ) OFFSET VOLTAGE (mv) V S = 5V BIAS CURRENT ( A) V S = 5V FIGURE. OFFSET VOLTAGE vs TEMPERATURE FIGURE 9. BIAS CURRENT vs TEMPERATURE 5 V S = 5V, R LOAD = 9 V S = 5V, I = ma PUT VOLTAGE (V) 4 2 +V -V SUPPLY CURRENT (ma) FIGURE. MAXIMUM PUT VOLTAGE vs TEMPERATURE FIGURE. SUPPLY CURRENT vs TEMPERATURE FN292 Rev 2. Page of 2

8 Typical Performance Curves (Continued) SUPPLY CURRENT (ma) 4 2 I = ma 25 C, 25 C -55 C IMPEDAE ( ) K K V S = 5V Z Z SUPPLY VOLTAGE ( V) FIGURE 2. SUPPLY CURRENT vs SUPPLY VOLTAGE K M M M FREQUEY (Hz) FIGURE. PUT/PUT IMPEDAE vs FREQUEY V MAX, V P-P AT khz T A = 25 C, T A = -55 C T A = 25 C R LOAD = SUPPLY VOLTAGE ( V) PSRR (db) K K M M FREQUEY (Hz) M FIGURE 4. V MAXIMUM vs V SUPPLY FIGURE 5. PSRR vs FREQUEY R L = V S = 5V T A = 25 C SLEW RATE (V/ s) 2 V - V (mv) 5-5 R L = K - R L = SUPPLY VOLTAGE ( V) PUT VOLTAGE (VOLTS) FIGURE. SLEW RATE vs SUPPLY VOLTAGE FIGURE. GA ERROR vs PUT VOLTAGE FN292 Rev 2. Page of 2

9 Die Characteristics SUBSTRATE POTENTIAL (POWERED UP): V - TRANSISTOR COUNT: 2 PROCESS: Bipolar Dielectric Isolation Metallization Mask Layout HA-52 V - (ALT) V - (ALT) V 2 + V 2 - Copyright Intersil Americas LLC 2-2. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see Intersil products are manufactured, assembled and tested utilizing ISO9 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see FN292 Rev 2. Page 9 of 2

10 Metal Can Packages (Can) ØD ØD F Q A REFEREE PLANE Øb A A L L2 L Øb Øb ØD2 NOTES:. (All leads) Øb applies between L and L2. Øb applies between L2 and.5 from the reference plane. Diameter is uncontrolled in L and beyond.5 from the reference plane. 2. Measured from maximum diameter of the product.. is the basic spacing from the centerline of the tab to terminal and is the basic spacing of each lead or lead position (N - places) from looking at the bottom of the package. 4. N is the maximum number of terminal positions. 5. Dimensioning and tolerancing per ANSI Y4.5M Controlling dimension: IH. Øe BASE AND SEATG PLANE BASE METAL SECTION A-A Øb2 2 e LEAD FISH N k k C L T.C MIL-STD-5 MACY-X (A) LEAD METAL CAN PACKAGE IHES MILLIMETERS SYMBOL M MAX M MAX NOTES A Øb Øb Øb ØD ØD ØD e.2 BSC 5. BSC - e. BSC 2.54 BSC - F k k L L L Q o BSC 45 o BSC 45 o BSC 45 o BSC N 4 Rev. 5//94 FN292 Rev 2. Page of 2

11 Plastic Leaded Chip Carrier Packages (PLCC).42 (.).4 (.22) P () IDENTIFIER D D.2 (.5) MAX PLCS.2 (.).2 (.) C L.42 (.).5 (.42).5 (.2) TP E E C L A A. (.).2 (.5).4 (.) C.25 (.4).45 (.4) R D2/E2 D2/E2 VIEW A.2 (.5) M SEATG PLANE N2.5 (JEDEC MS-AA ISSUE A) 2 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE IHES MILLIMETERS SYMBOL M MAX M MAX NOTES A A D D D , 5 E E E , 5 N 2 2 Rev. 2 /9.45 (.4) M VIEW A TYP..25 (.4) M -C- NOTES:. Controlling dimension: IH. Converted millimeter dimensions are not necessarily exact. 2. Dimensions and tolerancing per ANSI Y4.5M-92.. Dimensions D and E do not include mold protrusions. Allowable mold protrusion is. inch (.25mm) per side. Dimensions D and E include mold mismatch and are measured at the extreme material condition at the body parting line. 4. To be measured at seating plane -C- contact point. 5. Centerline to be determined where center leads exit plastic body.. N is the number of terminal positions. FN292 Rev 2. Page of 2

12 Package Outline Drawing M.5 LEAD NARROW BODY SMALL LE PLASTIC PACKAGE Rev 4, /2 DETAIL "A".2 (.5).4 (.) DEX AREA 4. (.5). (.5).2 (.244) 5. (.22).5 (.2).25 (.) x 45 2 TOP VIEW SIDE VIEW B.25 (.).9 (.) 2.2 (.) SEATG PLANE 5. (.9) 4. (.9).5 (.9).5 (.5) 2. (.2).2 (.5) -C-.2 (.5).5(.2).(.).25(.).(.4) (.25) SIDE VIEW A TYPICAL RECOMMENDED LAND PATTERN NOTES:. Dimensioning and tolerancing per ANSI Y4.5M Package length does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed.5mm (. inch) per side.. Package width does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed.25mm (. inch) per side. 4. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 5. Terminal numbers are shown for reference only.. The lead width as measured.mm (.4 inch) or greater above the seating plane, shall not exceed a maximum value of.mm (.24 inch).. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.. This outline conforms to JEDEC publication MS-2-AA ISSUE C. FN292 Rev 2. Page 2 of 2