HA, HA Absolute Maximum Ratings Supply Voltage Between V+ and V Terminals V Differential Input Voltage V

Transcription

1 HA, HA Data Sheet October 6, FN9.9 Dual and Quad, 8MHz, Low Noise Operational Amplifiers Low noise and high performance are key words describing HA and HA. These general purpose amplifiers offer an array of dynamic specifications including a 3V/µs slew rate and 8MHz bandwidth. Complementing these outstanding parameters is a very low noise specification of.3nv/ Hz at khz. Fabricated using the Intersil high frequency DI process, these operational amplifiers also offer excellent input specifications such as a.mv offset voltage and 3nA offset current. Complementing these specifications are 8dB open loop gain and 6dB channel separation. Consuming a very modest amount of power (9mW/ package for duals and mw/package for quads), HA/ also provide ma of output current. This impressive combination of features make this series of amplifiers ideally suited for designs ranging from audio amplifiers and active filters to the most demanding signal conditioning and instrumentation circuits. These operational amplifiers are available in dual or quad form with industry standard pinouts allowing for immediate interchangeability with most other dual and quad operational amplifiers. HA Dual, Comp. HA Quad, Comp. Refer to the /883 data sheet for military product. Ordering Information PART NUMBER TEMP. RANGE ( o C) PACKAGE PKG. DWG. # HA7 to 8 Ld CERDIP F8.3A HA to Ld CERDIP F.3 HA9P9 to 8 6 Ld SOIC M6.3 Features Low Noise nV/ Hz Bandwidth MHz (Compensated) Slew Rate V/µs (Compensated) Low Offset Voltage mV Available in Duals or Quads Applications High Q, Active Filters Audio Amplifiers Instrumentation Amplifiers Integrators Signal Generators For Further Design Ideas, See Application Note AN Pinouts HA (CERDIP) TOP VIEW OUT 8 V+ IN 7 OUT +IN IN V + +IN OUT IN +IN 3 V+ +IN HA (CERDIP) TOP VIEW IN 6 OUT OUT 3 IN +IN V +IN3 9 8 IN3 OUT3 HA (SOIC) TOP VIEW OUT IN +IN V+ +IN IN OUT NC OUT IN + + +IN 3 V +IN3 + + IN3 3 OUT3 8 9 NC CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 888INTERSIL or 3773 Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 3,. All Rights Reserved All other trademarks mentioned are the property of their respective owners.

2 HA, HA Absolute Maximum Ratings Supply Voltage Between V+ and V Terminals V Differential Input Voltage V Input Voltage ±V SUPPLY Output Short Circuit Duration (Note 3) Indefinite Operating Conditions Temperature Range HAX o C to o C HA o C to 8 o C Thermal Information Thermal Resistance (Typical, Note ) θ JA ( o C/W) θ JC ( o C/W) 8 Lead CERDIP Package Lead CERDIP Package SOIC Package N/A Maximum Junction Temperature (Note, Hermetic Package)..7 o C Maximum Junction Temperature (Plastic Package) o C Maximum Storage Temperature Range o C to o C Maximum Lead Temperature (Soldering s) o C (SOIC Lead Tips Only) CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES:. Maximum power dissipation, including output load, must be designed to maintain the maximum junction temperature below 7 o C for hermetic packages, and below o C for plastic packages.. θ JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 3. Any one amplifier may be shorted to ground indefinitely. Electrical Specifications V SUPPLY = ±V, Unless Otherwise Specified PARAMETER TEMP. ( o C) HA HA HA9 MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS INPUT CHARACTERISTICS Offset Voltage mv Full mv Offset Voltage Average Drift Full µv/ o C Bias Current na Full 3 3 na Offset Current na Full na Input Resistance kω Common Mode Range Full ± ± ± V TRANSFER CHARACTERISTICS Large Signal Voltage Gain, (V OUT = ±V, R L = kω) 8 kv/v Full 8 kv/v Common Mode Rejection Ratio (V CM = ±.V) Full db Small Signal Bandwidth, (A V = ) MHz Channel Separation (Note ) db OUTPUT CHARACTERISTICS Output Voltage Swing (R L = kω) Full ± ±3 ± ±3 ± ±3 V (R L = kω) Full ± ± ± ± ± ± V Output Current, (V OUT = ±V) Full ± ± ± ± ±7 ± ma Full Power Bandwidth (Note ) khz Output Resistance Ω STABILITY Minimum Stable Closed Loop Gain Full V/V TRANSIENT RESPONSE (Note 6) FN9.9

3 HA, HA Electrical Specifications V SUPPLY = ±V, Unless Otherwise Specified (Continued) PARAMETER TEMP. ( o C) HA HA HA9 MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS Rise Time ns Overshoot % Slew Rate V/µs Settling Time (Note 7)... µs NOISE CHARACTERISTICS (Note 8) Input Noise Voltage f = Hz nv/ Hz f = khz nv/ Hz Input Noise Current f = Hz... pa/ Hz f = khz pa/ Hz Broadband Noise Voltage f = DC to 3kHz nv RMS POWER SUPPLY CHARACTERISTICS Supply Current (All Amps) ma Power Supply Rejection Ratio, ( V S = ±V) Full db NOTES:. Channel separation value is referred to the input of the amplifier. Input test conditions are: f = khz; V IN = mv PEAK ; R S = kω.. Full power bandwidth is guaranteed by equation: Full power bandwidth = Slew Rate. πv 6. Refer to Test Circuits section of the data sheet. PEAK 7. Settling time is measured to.% of final value for a V input step, A V =. 8. The limits for these parameters are guaranteed based on lab characterization, and reflect lottolot variation. 3 FN9.9

4 HA, HA Test Circuits and Waveforms kω IN kω + OUT IN + kω pf kω pf INPUT +V V V mv INPUT OUTPUT +V OUTPUT V V V Vertical = V/Div., Horizontal = µs/div. (A V = ) Vertical = mv/div., Horizontal = ns/div. (A V = +) FIGURE. LARGE SIGNAL RESPONSE CIRCUIT FIGURE. SMALL SIGNAL RESPONSE CIRCUIT +V kω Ω (NOTE 9) N6 kω +V TO OSCILLOSCOPE kω + V IN V OUT Ω (NOTE 9) kω V pf kω NOTES: 9. A V =.. Feedback and summing resistors should be.% matched.. Clipping diodes are optional, HP88 recommended. FIGURE 3. SETTLING TIME CIRCUIT FN9.9

5 HA, HA Simplified Schematic V+ OUTPUT V +INPUT INPUT Typical Performance Curves V S = ±V, T A = o C V S = ±V, T A = o C NOISE VOLTAGE (nv/ Hz) HIGH TYPICAL LOW NOISE CURRENT (pa/ Hz)... K FREQUENCY (Hz) FIGURE. INPUT NOISE VOLTAGE DENSITY. K FREQUENCY (Hz) FIGURE. INPUT NOISE CURRENT DENSITY FN9.9

6 HA, HA Typical Performance Curves (Continued) V S = ±V, T A = o C, µv/div., s/div., A V = V/V Input Noise =.3µV PP FIGURE 6..Hz TO Hz NOISE V S = ±V, T A = o C, µv/div., s/div., A V = V/V Total Output Noise =.7µV PP FIGURE 7..Hz TO MHz NOISE INPUT OFFSET VOLTAGE (mv)..... V S = ±V T A = o C OFFSET VOLTAGE (mv) SUPPLY VOLTAGE (±V) FIGURE 8. V IO vs TEMPERATURE FIGURE 9. V IO vs V S INPUT OFFSET CURRENT (na) V S = ±V 9 V S = ±V INPUT BIAS CURRENT (na) FIGURE. I IO vs TEMPERATURE FIGURE. I BIAS vs TEMPERATURE 6 FN9.9

7 HA, HA Typical Performance Curves (Continued) V S = ±V, I OUT = T A = o C, I OUT = TOTAL SUPPLY CURRENT (ma) 3 TOTAL SUPPLY CURRENT (ma) SUPPLY VOLTAGE (±V) FIGURE. I CC vs TEMPERATURE (HA) FIGURE 3. I CC vs V S (HA) OPEN LOOP VOLTAGE GAIN ( V/V) V S = ±V, V O = ±V, R L = kω 3 3. o C K K K 6K 8K K LOAD RESISTANCE (Ω) OPEN LOOP VOLTAGE GAIN ( V/V). V O = ±V, V S = ±V. o C o C. FIGURE. A VOL vs TEMPERATURE FIGURE. A VOL vs LOAD RESISTANCE OPEN LOOP GAIN (kv/v) 9 8 T A = o C, R L = kω SUPPLY VOLTAGE (±V) MAX OUTPUT SWING (±V) 3 T A = o C, R L = kω SUPPLY VOLTAGE (±V) FIGURE 6. A VOL vs V S FIGURE 7. V OUT vs V S 7 FN9.9

8 HA, HA Typical Performance Curves (Continued) V S = ±V, T A = o C OUTPUT CURRENT (ma) 3 3 V OUT = +V V OUT = V CMRR (db) TIME (SECONDS) K K FREQUENCY (Hz) K M FIGURE 8. OUTPUT SHORT CIRCUIT CURRENT vs TIME FIGURE 9. CMRR vs FREQUENCY POWER SUPPLY REJECTION (db) 6 8 VOLTAGE GAIN (db) V S = ±V, R L = kω, C L = pf +PSRR o C PSRR PHASE 8 o C 3 PHASE o C GAIN o C GAIN 3 PHASE SHIFT (DEGREES) K K K M K K M M M FREQUENCY (Hz) FREQUENCY (Hz) FIGURE. PSRR vs FREQUENCY FIGURE. UNITY GAIN FREQUENCY RESPONSE VOLTAGE GAIN (db) 8 6 GAIN PHASE V S = ±V, T A = o C, R L = kω, C L = pf 8 K K K M M M FREQUENCY (Hz) 9 3 PHASE SHIFT (DEGREES) OVERSHOOT (%) 6 3 V S = ±V, T A = o C, R L = kω K K LOAD CAPACITANCE (pf) FIGURE. OPEN LOOP GAIN vs FREQUENCY FIGURE 3. SMALL SIGNAL OVERSHOOT vs C LOAD 8 FN9.9

9 HA, HA Typical Performance Curves (Continued). R L = kω, C L = pf, V S = ±V. R L = kω, C L = pf, V S = ±V SLEW RATE (NORMALIZED) RISE TIME (NORMALIZED) FIGURE. SLEW RATE vs TEMPERATURE FIGURE. RISE TIME vs TEMPERATURE Die Characteristics DIE DIMENSIONS: 98. mils x 67.3 mils x 9 mils µm x 7µm x 83µm PASSIVATION: Type: Nitride (Si 3 N ) over Silox (SiO, % Phos.) Silox Thickness: kå ±kå Nitride Thickness: 3.kÅ ±.kå SUBSTRATE POTENTIAL (POWERED UP): METALLIZATION: Unbiased Type: Al, % Cu Thickness: 6kÅ ±kå TRANSISTOR COUNT: 93 PROCESS: Bipolar Dielectric Isolation Metallization Mask Layout HA V +IN IN OUT +IN IN OUT V+ 9 FN9.9

10 HA, HA Die Characteristics DIE DIMENSIONS: 9 mils x 99 mils x 9 mils µm x 3µm x 83µm METALLIZATION: Type: Al, % Cu Thickness: 6kÅ ±kå SUBSTRATE POTENTIAL (POWERED UP): Unbiased TRANSISTOR COUNT: 7 PROCESS: Bipolar Dielectric Isolation PASSIVATION: Type: Nitride (Si 3 N ) over Silox (SiO, % Phos.) Silox Thickness: kå ±kå Nitride Thickness: 3.kÅ ±.kå Metallization Mask Layout HA +IN V+ +IN IN IN OUT OUT OUT3 OUT IN3 IN +IN3 V +IN FN9.9

11 HA, HA Ceramic DualInLine Frit Seal Packages (CERDIP) BASE PLANE SEATING PLANE S b ccc M bbb S b C A B C A B S D A A e D S E L M c ea/ S D S aaa M C A B LEAD FINISH BASE METAL b M (b) SECTION AA D A Q C A Bα ea S c D S (c) F8.3A MILSTD83 GDIPT8 (D, CONFIGURATION A) 8 LEAD CERAMIC DUALINLINE FRIT SEAL PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A..8 b b b b c c D..9 E e. BSC. BSC ea.3 BSC 7.6 BSC NOTES: ea/. BSC 3.8 BSC. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer s identification shall not be used as a pin one identification mark.. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. L Q S α aaa bbb... 9 o..6 o o.8. o Dimensions b and c apply to lead base metal only. Dimension M applies to lead plating and finish thickness. ccc... Corner leads (, N, N/, and N/+) may be configured with a M..38, 3 partial lead paddle. For this configuration dimension b3 replaces dimension b.. This dimension allows for offcenter lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y.M 98.. Controlling dimension: INCH N Rev. /9 FN9.9

12 HA, HA Ceramic DualInLine Frit Seal Packages (CERDIP) BASE PLANE SEATING PLANE S b ccc M bbb S b C A B C A B S D A A e D S E L M c ea/ S D S aaa M C A B LEAD FINISH BASE METAL b M (b) SECTION AA D A Q C A Bα ea S c D S (c) F.3 MILSTD83 GDIPT (D, CONFIGURATION A) LEAD CERAMIC DUALINLINE FRIT SEAL PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A..8 b b b b c c D E e. BSC. BSC ea.3 BSC 7.6 BSC NOTES: ea/. BSC 3.8 BSC. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer s identification shall not be used as a pin one identification mark.. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when L Q S α aaa... 9 o..6 o o.8. o solder dip or tin plate lead finish is applied. bbb Dimensions b and c apply to lead base metal only. Dimension M applies to lead plating and finish thickness. ccc... Corner leads (, N, N/, and N/+) may be configured with a M..38, 3 partial lead paddle. For this configuration dimension b3 replaces N 8 dimension b. Rev. /9. This dimension allows for offcenter lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y.M 98.. Controlling dimension: INCH. FN9.9

13 Small Outline Plastic Packages (SOIC) HA, HA N M6.3 (JEDEC MS3AA ISSUE C) 6 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE INDEX AREA H.(.) M B M INCHES MILLIMETERS E SYMBOL B MIN MAX MIN MAX NOTES A L A B SEATING PLANE C A D A h x o D E C e. BSC.7 BSC µ α e H A C h B.(.) L (.) M C A M B S N NOTES:. Symbols are defined in the MO Series Symbol List in Section. of Publication Number 9.. Dimensioning and tolerancing per ANSI Y.M Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed.mm (.6 inch) per side.. Dimension E does not include interlead flash or protrusions. Interlead α o 8 o o 8 o Rev. /93 flash and protrusions shall not exceed.mm (. inch) per side.. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. L is the length of terminal for soldering to a substrate. 7. N is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width B, as measured.36mm (. inch) or greater above the seating plane, shall not exceed a maximum value of.6mm (. inch). Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9 quality systems. Intersil Corporation s quality certifications can be viewed at Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see 3 FN9.9