HA Features. 100MHz Current Feedback Video Amplifier With Disable. Applications. Pinout. Data Sheet May 21, 2013 FN

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1 HA- Data Sheet May, FN8. MHz Current Feedback Video Amplifier With Disable The HA- is a wide bandwidth, high slew rate amplifier optimized for video applications and gains between and. Manufactured on Intersil s Reduced Feature Complementary Bipolar DI process, this amplifier uses current mode feedback to maintain higher bandwidth at a given gain than conventional voltage feedback amplifiers. Since it is a closed loop device, the HA- offers better gain accuracy and lower distortion than open loop buffers. The HA- features low differential gain and phase and will drive two double terminated 7Ω coax cables to video levels with low distortion. Adding a gain flatness performance of.db makes this amplifier ideal for demanding video applications. The bandwidth and slew rate of the HA- are relatively independent of closed loop gain. The MHz unity gain bandwidth only decreases to 6MHz at a gain of. The HA- used in place of a conventional op amp will yield a significant improvement in the speed power product. To further reduce power, HA- has a disable function which significantly reduces supply current, while forcing the output to a true high impedance state. This allows the outputs of multiple amplifiers to be wire-or d into multiplexer configurations. The device also includes output short circuit protection and output offset voltage adjustment.for multi channel versions of the HA- see the HA dual with disable, HA dual, HA triple and HA quad with disable op amp data sheets. Pinout HA- (PDIP, SOIC) TOP VIEW Features Wide Unity Gain Bandwidth MHz Slew Rate V/µs Output Current ±ma (Min) Drives.V into 7Ω Differential Gain % Differential Phase Low Input Voltage Noise nV/ Hz Low Supply Current ma (Max) Wide Supply Range ±V to ±V Output Enable/Disable High Performance Replacement for EL Pb-Free (RoHS Compliant) Applications Unity Gain Video/Wideband Buffer Video Gain Block Video Distribution Amp/Coax Cable Driver Flash A/D Driver Waveform Generator Output Driver Current to Voltage Converter; D/A Output Buffer Radar Systems Imaging Systems BAL 8 DISABLE IN- IN V+ OUT V- BAL CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures INTERSIL or Copyright Intersil Americas LLC,,-6,. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners.

2 HA- Ordering Information PART NUMBER PART MARKING TEMP. RANGE ( C) PACKAGE (PB-free PKG. DWG. # HA--Z (Note ) HA- -Z to +7 8 Ld PDIP E8. HA9P-Z (Note ) Z to +7 8 Ld SOIC M8. HA9P-ZX96 (Note ) Z to +7 8 Ld SOIC (Tape and Reel) M8. NOTES:. Please refer to TB7 for details on reel specifications.. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and % matte tin plate plus anneal (e termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-. FN8. May,

3 HA- Absolute Maximum Ratings (Note ) Voltage Between V+ and V- Terminals V DC Input Voltage ±V SUPPLY Differential Input Voltage V Output Current Short Circuit Protected Operating Conditions Temperature Range C to +7 C Thermal Information Thermal Resistance (Typical, Note ) θ JA ( C/W) θ JC ( C/W) PDIP Package* N/A SOIC Package N/A Maximum Junction Temperature (Plastic Packages, Note ).. + C Maximum Storage Temperature Range C to + C *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications Pb-Free Reflow Profile see link below CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES:. Maximum power dissipation, including output load, must be designed to maintain junction temperature below + C for plastic packages.. θ JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB79 for details. Electrical Specifications V SUPPLY = ±V, R F = kω, A V = +, R L = Ω, C L pf, Unless Otherwise Specified PARAMETER TEST CONDITIONS TEMP. ( C) MIN TYP MAX UNITS INPUT CHARACTERISTICS Input Offset Voltage (Notes 6, 7) - 8 mv Full - - mv Average Input Offset Voltage Drift Full - - µv/ C V IO Common Mode Rejection Ratio (Note 7) V CM = ±V db Full - - db V IO Power Supply Rejection Ratio (Note 7) ±.V V S ±8V db Full db Non-Inverting Input (+IN) Current (Note 7 ) - 8 µa Full - - µa +IN Common Mode Rejection V CM = ±V - -. µa/v Full - -. µa/v +IN Power Supply Rejection ±.V V S ±8V µa/v Full - -. µa/v Inverting Input (-IN) Current (Note 7) - µa Full - µa -IN Common Mode Rejection V CM = ±V - -. µa/v Full - -. µa/v -IN Power Supply Rejection ±.V V S ±8V - -. µa/v Full - -. µa/v TRANSFER CHARACTERISTICS Transimpedance (Notes, 7) - - V/mA Full - - V/mA Open Loop DC Voltage Gain (Note ) R L = Ω, db V OUT = ±V Full db Open Loop DC Voltage Gain R L = Ω, db V OUT = ±.V Full - - db FN8. May,

4 HA- Electrical Specifications V SUPPLY = ±V, R F = kω, A V = +, R L = Ω, C L pf, Unless Otherwise Specified (Continued) PARAMETER TEST CONDITIONS TEMP. ( C) MIN TYP MAX UNITS OUTPUT CHARACTERISTICS Output Voltage Swing (Note 7) R L = Ω to 8 ± ±.7 - V - to ± ±.8 - V Output Current (Guaranteed by Output Voltage Test) ± ±.7 - ma Full ± ma POWER SUPPLY CHARACTERISTICS Quiescent Supply Current (Note 7) Full - 7. ma Supply Current, Disabled (Note 7) DISABLE = V Full - 7. ma Disable Pin Input Current DISABLE = V Full -.. ma Minimum Pin 8 Current to Disable (Note 7) Full - - µa Maximum Pin 8 Current to Enable (Note 8) Full - - µa AC CHARACTERISTICS (A V = +) Slew Rate (Note 9) V/µs Full 7 - V/µs Full Power Bandwidth (Note ) MHz (Guaranteed by Slew Rate Test) Full MHz Rise Time (Note ) - - ns Fall Time (Note ) - - ns Propagation Delay (Notes, 7) ns -db Bandwidth (Note 7) V OUT = mv - - MHz Settling Time to % V Output Step - - ns Settling Time to.% V Output Step - - ns AC CHARACTERISTICS (A V = +, R F = 8Ω) Slew Rate (Notes 9, ) 9 - V/µs Full V/µs Full Power Bandwidth (Note ) MHz (Guaranteed by Slew Rate Test) Full. - - MHz Rise Time (Note ) ns Fall Time (Note ) ns Propagation Delay (Notes, 7) ns -db Bandwidth V OUT = mv MHz Settling Time to % V Output Step - - ns Settling Time to.% V Output Step ns INTERSIL VALUE ADDED SPECIFICATIONS Input Noise Voltage (Note 7) f = khz -. - nv/ Hz +Input Noise Current (Note 7) f = khz -. - pa/ Hz -Input Noise Current (Note 7) f = khz - - pa/ Hz Input Common Mode Range Full ± ± - V -I BIAS Adjust Range (Note 6) Full ± ± - µa Overshoot (Note 7) % FN8. May,

5 HA- Electrical Specifications V SUPPLY = ±V, R F = kω, A V = +, R L = Ω, C L pf, Unless Otherwise Specified (Continued) PARAMETER TEST CONDITIONS TEMP. ( C) MIN TYP MAX UNITS Output Current, Short Circuit (Note 7) V IN = ±V, V OUT = V Full ± ±6 - ma Output Current, Disabled (Note 7) DISABLE = V, Full - - µa V OUT = ±V Output Disable Time (Notes, 7) - - µs Output Enable Time (Notes, 7) - - ns Supply Voltage Range ± - ± V Output Capacitance, Disabled (Note ) DISABLE = V pf VIDEO CHARACTERISTICS Differential Gain (Notes 6, 7) R L = Ω -. - % Differential Phase (Notes 6, 7) R L = Ω -. - Gain Flatness To MHz -. - db Electrical Specifications V+ = +V, V- = -V, R F = kω, A V = +, R L = Ω, C L pf, Unless Otherwise Specified. Parameters are not tested. The limits are guaranteed based on lab characterizations, and reflect lot-to-lot variation. PARAMETER TEST CONDITIONS TEMP. ( C) MIN TYP MAX UNITS INPUT CHARACTERISTICS Input Offset Voltage (Notes 6, 7) - 8 mv Full - - mv Average Input Offset Voltage Drift Full - - µv/ C V IO Common Mode Rejection Ratio (Notes 7, 8) - - db Full - - db V IO Power Supply Rejection Ratio (Note 7) ±.V V S ±6.V - - db Full - - db Non-Inverting Input (+IN) Current (Note 7) - 8 µa Full - - µa +IN Common Mode Rejection (Note 8) - -. µa/v Full - -. µa/v +IN Power Supply Rejection ±.V V S ±6.V µa/v Full - -. µa/v Inverting Input (-IN) Current (Note 7) - µa Full - µa -IN Common Mode Rejection (Note 8) - -. µa/v Full - -. µa/v -IN Power Supply Rejection ±.V V S ±6.V - -. µa/v Full - -. µa/v TRANSFER CHARACTERISTICS Transimpedance (Notes, 7) - - V/mA Full V/mA Open Loop DC Voltage Gain R L = Ω, db V OUT = ±.V Full db FN8. May,

6 HA- Electrical Specifications V+ = +V, V- = -V, R F = kω, A V = +, R L = Ω, C L pf, Unless Otherwise Specified. Parameters are not tested. The limits are guaranteed based on lab characterizations, and reflect lot-to-lot variation. (Continued) TEMP. PARAMETER TEST CONDITIONS ( C) MIN TYP MAX UNITS Open Loop DC Voltage Gain R L = Ω, - - db V OUT = ±.V Full - - db OUTPUT CHARACTERISTICS Output Voltage Swing (Note 7) to 8 ±. ±. - V - to ±. ±. - V Output Current R L = Ω ±6.6 ± - ma (Guaranteed by Output Voltage Test) Full ±6.6 ± - ma POWER SUPPLY CHARACTERISTICS Quiescent Supply Current (Note 7) Full - 7. ma Supply Current, Disabled (Note 7) DISABLE = V Full - 7. ma Disable Pin Input Current DISABLE = V Full -.. ma Minimum Pin 8 Current to Disable (Note 9) Full - - µa Maximum Pin 8 Current to Enable (Note 8) Full - - µa AC CHARACTERISTICS (A V = +) Slew Rate (Note ) - V/µs Full Power Bandwidth (Note ) 8 - MHz Rise Time (Note ) ns Fall Time (Note ) ns Propagation Delay (Note ) ns Overshoot -. - % -db Bandwidth (Note 7) V OUT = mv - - MHz Settling Time to % V Output Step - - ns Settling Time to.% V Output Step ns AC CHARACTERISTICS (A V = +, R F = 68Ω) Slew Rate (Note ) V/µs Full Power Bandwidth (Note ) MHz Rise Time (Note ) ns Fall Time (Note ) ns Propagation Delay (Note ) ns Overshoot - - % -db Bandwidth (Note 7) V OUT = mv MHz Settling Time to % V Output Step - - ns Settling Time to.% V Output Step - - ns AC CHARACTERISTICS (A V = +, R F = 8Ω) Slew Rate (Note ) 7 - V/µs Full Power Bandwidth (Note ) MHz Rise Time (Note ) ns Fall Time (Note ) ns Propagation Delay (Note ) ns Overshoot % 6 FN8. May,

7 HA- Electrical Specifications V+ = +V, V- = -V, R F = kω, A V = +, R L = Ω, C L pf, Unless Otherwise Specified. Parameters are not tested. The limits are guaranteed based on lab characterizations, and reflect lot-to-lot variation. (Continued) -db Bandwidth (Note 7) V OUT = mv MHz Settling Time to % V Output Step ns Settling Time to.% V Output Step - - ns INTERSIL VALUE ADDED SPECIFICATIONS Input Noise Voltage (Note 7) f = khz -. - nv/ Hz +Input Noise Current (Note 7) f = khz -. - pa/ Hz -Input Noise Current (Note 7) f = khz - - pa/ Hz Input Common Mode Range Full ±.V - V Output Current, Short Circuit V IN = ±.V, V OUT = V Full ± ±6 - ma Output Current, Disabled (Note 7) DISABLE = V, V OUT = ±.V, V IN = V Full - - µa Output Disable Time (Notes 7, ) - - µs Output Enable Time (Notes 7, ) - - ns Supply Voltage Range ± - ± V Output Capacitance, Disabled (Note ) DISABLE = V pf VIDEO CHARACTERISTICS Differential Gain (Notes 6, 7) R L = Ω -. - % Differential Phase (Notes 6, 7) R L = Ω -. - Gain Flatness To MHz -. - db NOTES:. Suggested V OS Adjust Circuit: The inverting input current (-I BIAS ) can be adjusted with an external kω pot between pins and, wiper connected to V+. Since -I BIAS flows through the feedback resistor (R F ), the result is an adjustment in offset voltage. The amount of offset voltage adjustment is determined by the value of R F (ΔV OS = Δ-I BIAS *R F ). 6. R L = Ω, V IN = V. This is the minimum current which must be pulled out of the Disable pin in order to disable the output. The output is considered disabled when -mv V OUT +mv. 7. V IN = V. This is the maximum current that can be pulled out of the Disable pin with the HA- remaining enabled. The HA- is considered disabled when the supply current has decreased by at least.ma. 8. V OUT switches from -V to +V, or from +V to -V. Specification is from the % to 7% points. 9. PARAMETER Slew Rate FPBW = ; V πv PEAK = V. PEAK TEST CONDITIONS TEMP. ( C) MIN TYP MAX UNITS. R L = Ω, V OUT = V. Measured from % to 9% points for rise/fall times; from % points of input and output for propagation delay.. This parameter is not tested. The limits are guaranteed based on lab characterization, and reflect lot-to-lot variation.. V IN = +V, Disable = +V to V. Measured from the % point of Disable to V OUT = V.. V IN = +V, Disable = V to +V. Measured from the % point of Disable to V OUT = V.. V IN = V, Force V OUT from V to ±V, t R = t F = ns.. Measured with a VM7A video tester using a NTC-7 composite VITS. 6. See Typical Performance Curves on page for more information. 7. V CM = ±.V. At - C product is tested at V CM = ±.V because short test duration does not allow self heating. 8. R L = Ω. V IN =.V. This is the minimum current which must be pulled out of the Disable pin in order to disable the output. The output is considered disabled when -mv V OUT +mv. 9. V OUT switches from -V to +V, or from +V to -V. Specification is from the % to 7% points. Slew Rate. FPBW = ; V. πv PEAK =V PEAK. V IN = V, Force V OUT from V to ±.V, t R = t F = ns.. V IN = +V, Disable = +V to V. Measured from the % point of Disable to V OUT = V.. V IN = +V, Disable = V to +V. Measured from the % point of Disable to V OUT = V. 7 FN8. May,

8 HA- Test Circuits and Waveforms + - DUT Ω HP9 NETWORK ANALYZER Ω FIGURE. TEST CIRCUIT FOR TRANSIMPEDANCE MEASUREMENTS V IN + - DUT V OUT V IN + - DUT V OUT Ω R L Ω Ω R F, kω R L Ω R I 68Ω R F, 68Ω FIGURE. SMALL SIGNAL PULSE RESPONSE CIRCUIT FIGURE. LARGE SIGNAL PULSE RESPONSE CIRCUIT V IN V IN V OUT V OUT Vertical Scale: V IN = mv/div., V OUT = mv/div. Horizontal Scale: ns/div. FIGURE. SMALL SIGNAL RESPONSE Vertical Scale: V IN = V/Div., V OUT = V/Div. Horizontal Scale: ns/div. FIGURE. LARGE SIGNAL RESPONSE 8 FN8. May,

9 HA- Schematic Diagram V+ V- R 6K D O Q P Q N R 8 Q N R 6K Q N R 8 Q N R.K Q P R 8 R 6 K R 7 K DIS D R 8.K Q P Q N Q N6 Q P Q N7 R 9 8 Q P7 R 8 Q P8 Q P9 Q P R K Q P Q N8 Q P6 R 8 +IN Q N R 8 R K Q N9 Q N Q P R R 9 Q P R 7 8 R 8 8 R Q N Q P R Q P C.pF -IN Q N Q P C.pF Q N R R 8 R Q N Q N6 R 6 R R 7 Q P6 Q N7 R Q N8 R 6 R 8 Q P7 Q N R K Q P8 Q N9 R 6 Q P9 R 7 QP R 9 9. R Q N R 9 FN8. May,

10 HA- Application Information Optimum Feedback Resistor The plots of inverting and non-inverting frequency response illustrate the performance of the HA- in various closed loop gain configurations. Although the bandwidth dependency on closed loop gain isn t as severe as that of a voltage feedback amplifier, there can be an appreciable decrease in bandwidth at higher gains. This decrease may be minimized by taking advantage of the current feedback amplifier s unique relationship between bandwidth and R F. All current feedback amplifiers require a feedback resistor, even for unity gain applications, and R F, in conjunction with the internal compensation capacitor, sets the dominant pole of the frequency response. Thus, the amplifier s bandwidth is inversely proportional to R F. The HA- design is optimized for a Ω R F at a gain of +. Decreasing R F in a unity gain application decreases stability, resulting in excessive peaking and overshoot. At higher gains the amplifier is more stable, so R F can be decreased in a trade-off of stability for bandwidth. The table below lists recommended R F values for various gains, and the expected bandwidth. GAIN (A CL ) R F (Ω) BANDWIDTH (MHz) PC Board Layout The frequency response of this amplifier depends greatly on the amount of care taken in designing the PC board. The use of low inductance components such as chip resistors and chip capacitors is strongly recommended. If leaded components are used the leads must be kept short especially for the power supply decoupling components and those components connected to the inverting input. Attention must be given to decoupling the power supplies. A large value (µf) tantalum or electrolytic capacitor in parallel with a small value (.µf) chip capacitor works well in most cases. A ground plane is strongly recommended to control noise. Care must also be taken to minimize the capacitance to ground seen by the amplifier s inverting input (-IN). The larger this capacitance, the worse the gain peaking, resulting in pulse overshoot and possible instability. It is recommended that the ground plane be removed under traces connected to -IN, and that connections to -IN be kept as short as possible to minimize the capacitance from this node to ground. Driving Capacitive Loads Capacitive loads will degrade the amplifier s phase margin resulting in frequency response peaking and possible oscillations. In most cases the oscillation can be avoided by placing an isolation resistor (R) in series with the output as shown in Figure 6. V IN R T R I + - V OUT FIGURE 6. PLACEMENT OF THE OUTPUT ISOLATION RESISTOR, R The selection criteria for the isolation resistor is highly dependent on the load, but 7Ω has been determined to be a good starting value. Enable/Disable Function When enabled the amplifier functions as a normal current feedback amplifier with all of the data in the electrical specifications table being valid and applicable. When disabled the amplifier output assumes a true high impedance state and the supply current is reduced significantly. The circuit shown in Figure 7 is a simplified schematic of the enable/disable function. The large value resistors in series with the DISABLE pin makes it appear as a current source to the driver. When the driver pulls this pin low current flows out of the pin and into the driver. This current, which may be as large as μa when external circuit and process variables are at their extremes, is required to insure that point A achieves the proper potential to disable the output. The driver must have the compliance and capability of sinking all of this current. ENABLE/ DISABLE INPUT +V CC R 7 K When V CC is +V the DISABLE pin may be driven with a dedicated TTL gate. The maximum low level output voltage of the TTL gate,.v, has enough compliance to insure that the amplifier will always be disabled even though D will not turn on, and the TTL gate will sink enough current to keep point A at its proper voltage. When V CC is greater than +V the DISABLE pin should be driven with an open collector device that has a breakdown rating greater than V CC. R F R 6 K D R R R 8 Q P C L R Q P8 FIGURE 7. SIMPLIFIED SCHEMATIC OF ENABLE/DISABLE FUNCTION A FN8. May,

11 HA- Referring to Figure 7, it can be seen that R 6 will act as a pull-up resistor to +V CC if the DISABLE pin is left open. In those cases where the enable/disable function is not required on all circuits some circuits can be permanently enabled by letting the DISABLE pin float. If a driver is used to set the enable/disable level, be sure that the driver does not sink more than μa when the DISABLE pin is at a high level. TTL gates, especially CMOS versions, do not violate this criteria so it is permissible to control the enable/disable function with TTL. Typical Applications Two Channel Video Multiplexer Referring to the amplifier U A in Figure 8, R terminates the cable in its characteristic impedance of 7Ω, and R back terminates the cable in its characteristic impedance. The amplifier is set up in a gain configuration of + to yield an overall network gain of + when driving a double terminated cable. The value of R can be changed if a different network gain is desired. R holds the disable pin at ground thus inhibiting the amplifier until the switch, S, is thrown to position. At position the switch pulls the disable pin up to the plus supply rail thereby enabling the amplifier. Since all of the actual signal switching takes place within the amplifier, it s differential gain and phase parameters, which are.% and. respectively, determine the circuit s performance. The other circuit, U B, operates in a similar manner. When the plus supply rail is V the disable pin can be driven by a dedicated TTL gate as discussed earlier. If a multiplexer IC or its equivalent is used to select channels its logic must be break before make. When these conditions are satisfied the HA- is often used as a remote video multiplexer, and the multiplexer may be extended by adding more amplifier ICs. Low Impedance Multiplexer Two common problems surface when you try to multiplex multiple high speed signals into a low impedance source such as an A/D converter. The first problem is the low source impedance which tends to make amplifiers oscillate and causes gain errors. The second problem is the multiplexer which supplies no gain, introduces all kinds of distortion and limits the frequency response. Using op amps which have an enable/disable function, such as the HA-, eliminates the multiplexer problems because the external mux chip is not needed, and the HA- can drive low impedance (large capacitance) loads if a series isolation resistor is used. Referring to Figure 9, both inputs are terminated in their characteristic impedance; 7Ω is typical for video applications. Since the drivers usually are terminated in their characteristic impedance the input gain is., thus the amplifiers, U, are configured in a gain of + to set the circuit gain equal to one. Resistors R and R determine the amplifier gain, and if a different gain is desired R should be changed according to the equation G = ( + R /R ). R sets the frequency response of the amplifier so you should refer to the manufacturers data sheet before changing its value. R, C and D are an asymmetrical charge/discharge time circuit which configures U as a break before make switch to prevent both amplifiers from being active simultaneously. If this design is extended to more channels the drive logic must be designed to be break before make. R is enclosed in the feedback loop of the amplifier so that the large open loop amplifier gain of U will present the load with a small closed loop output impedance while keeping the amplifier stable for all values of load capacitance. The circuit shown in Figure 9 was tested for the full range of capacitor values with no oscillations being observed; thus, problem one has been solved. The frequency and gain characteristics of the circuit are now those of the amplifier and independent of any multiplexing action; thus, problem two has been solved. The multiplexer transition time is approximately μs with the component values shown. VIDEO INPUT # R 7 R U A R 68 R 7 R VIDEO OUTPUT TO 7Ω LOAD +V IN +V +.μf μf VIDEO INPUT # R 6 7 R 8 68 U B R 9 7 R 7 68 R ALL OFF S R +V -V IN -V.μF μf + NOTES:. U is HA-.. All resistors in Ω. 6. S is break before make. 7. Use ground plane. FIGURE 8. TWO CHANNEL HIGH IMPEDANCE MULTIPLEXER FN8. May,

12 HA- INPUT B R A R A 7 R A 68 U A 68 R A 7 INPUT A R B 7 D A N V.μF CHANNEL SWITCH INHIBIT U C U A U B U D R 6 K R A C A.7μF R B D B N8 R B 68 C B.7μF U B R B V.μF R B 7 OUTPUT NOTES: 8. U : HA-. 9. U : CD. FIGURE 8. LOW IMPEDANCE MULTIPLEXER Typical Performance Curves V SUPPLY = ±V, A V = +, R F = kω, R L = Ω, T A = + C, unless otherwise specified. A V = + INPUT NOISE VOLTAGE (nv/ Hz) -INPUT NOISE CURRENT INPUT NOISE VOLTAGE INPUT NOISE CURRENT (pa/ Hz) OFFSET VOLTAGE (mv).... V SUPPLY = ±V V SUPPLY = ±.V V SUPPLY = ±V +INPUT NOISE CURRENT k k k FIGURE 9. INPUT NOISE vs FREQUENCY (AVERAGE OF 8 UNITS FROM LOTS) FIGURE. INPUT OFFSET VOLTAGE vs TEMPERATURE (ABSOLUTE VALUE AVERAGE OF UNITS FROM LOTS) BIAS CURRENT (μa) V SUPPLY = ±V V SUPPLY = ±V V SUPPLY = ±.V BIAS CURRENT (μa).6.. V SUPPLY = ±V V SUPPLY = ±V V SUPPLY = ±.V FIGURE. +INPUT BIAS CURRENT vs TEMPERATURE (AVERAGE OF UNITS FROM LOTS) FIGURE. -INPUT BIAS CURRENT vs TEMPERATURE (ABSOLUTE VALUE AVERAGE OF UNITS FROM LOTS) FN8. May,

13 HA- Typical Performance Curves V SUPPLY = ±V, A V = +, R F = kω, R L = Ω, T A = + C, unless otherwise specified 6 8 OPEN LOOP GAIN (MΩ) V SUPPLY = ±V V SUPPLY = ±V V SUPPLY = ±.V SUPPLY CURRENT (ma) 7 6 C C - C SUPPLY VOLTAGE (±V) FIGURE. TRANSIMPEDANCE vs TEMPERATURE (AVERAGE OF UNITS FROM LOTS) FIGURE. SUPPLY CURRENT vs SUPPLY VOLTAGE (AVERAGE OF UNITS FROM LOTS) SUPPLY CURRENT (ma) 7 6 DISABLE = V - C C C SUPPLY CURRENT (ma) V SUPPLY = ±.V V SUPPLY = ±V V SUPPLY = ±V 7 9 SUPPLY VOLTAGE (±V) 7 9 DISABLE INPUT VOLTAGE (V) FIGURE. DISABLE SUPPLY CURRENT vs SUPPLY VOLTAGE (AVERAGE OF UNITS FROM LOTS) FIGURE 6. SUPPLY CURRENT vs DISABLE INPUT VOLTAGE. FEEDTHROUGH (db) DISABLE = V V IN = V P-P R F = 7Ω OUTPUT LEAKAGE CURRENT (μa). -. V OUT = +V V OUT = -V -8 M M 6M 8M M M M 6M 8M M FIGURE 7. DISABLE MODE FEEDTHROUGH vs FREQUENCY FIGURE 8. DISABLED OUTPUT LEAKAGE vs TEMPERATURE (AVERAGE OF UNITS FROM LOTS) FN8. May,

14 HA- Typical Performance Curves V SUPPLY = ±V, A V = +, R F = kω, R L = Ω, T A = + C, unless otherwise specified ENABLE TIME (μs) ENABLE TIME DISABLE TIME OUTPUT VOLTAGE (V) FIGURE 9. ENABLE/DISABLE TIME vs OUTPUT VOLTAGE (AVERAGE OF 9 UNITS FROM LOTS) DISABLE TIME (μs) NORMALIZED GAIN (db) A V = + V OUT =.V P-P C L = pf A V = + A V = +6-7 M 8M 7M 96M M A V = + FIGURE. NON-INVERTING GAIN vs FREQUENCY NORMALIZED GAIN (db) V OUT =.V P-P C L = pf R F = 7Ω - A V = A V = A V = - A V = M 8M 7M 96M M FIGURE. INVERTING FREQUENCY RESPONSE NON-INVERTING PHASE ( ) A V = A V = - A V = -6 A V = A V = + -9 A V = A V = A V = + -7 M 8M 7M 96M M FIGURE. PHASE vs FREQUENCY INVERTING PHASE ( ) -db BANDWIDTH (MHz) C L = pf V OUT =.V P-P -db BANDWIDTH GAIN PEAKING GAIN PEAKING (db) -db BANDWIDTH (MHz) 9 9 C L = pf V OUT =.V P-P -db BANDWIDTH GAIN PEAKING GAIN PEAKING (db) LOAD RESISTANCE (Ω) k.k.k FEEDBACK RESISTOR (Ω) FIGURE. BANDWIDTH AND GAIN PEAKING vs LOAD RESISTANCE FIGURE. BANDWIDTH AND GAIN PEAKING vs FEEDBACK RESISTANCE FN8. May,

15 HA- Typical Performance Curves V SUPPLY = ±V, A V = +, R F = kω, R L = Ω, T A = + C, unless otherwise specified C L = pf, A V = + V OUT =.V P-P 8 7 C L = pf, A V = + V OUT =.V P-P -db BANDWIDTH (MHz) db BANDWIDTH GAIN PEAKING GAIN PEAKING (db) -db BANDWIDTH (MHz) 6 GAIN PEAKING = db k.k FEEDBACK RESISTOR (Ω) 6 8 FEEDBACK RESISTOR (Ω) FIGURE. BANDWIDTH AND GAIN PEAKING vs FEEDBACK RESISTANCE FIGURE 6. BANDWIDTH vs FEEDBACK RESISTANCE 7 - A V = + REJECTION RATIO (db) CMRR PSRR REJECTION RATIO (db) CMRR -PSRR +PSRR FIGURE 7. REJECTION RATIOS vs TEMPERATURE (AVERAGE OF UNITS FROM LOTS) -9 k k M M FIGURE 8. REJECTION RATIOS vs FREQUENCY OUTPUT SWING OVERHEAD (±V).... (±V SUPPLY ) - (±V OUT ) V SUPPLY = ±V V SUPPLY = ±V V SUPPLY = ±.V OUTPUT VOLTAGE SWING (V P-P ) V SUPPLY = ±V V SUPPLY = ±V V SUPPLY = ±.V k LOAD RESISTANCE (Ω) k FIGURE 9. OUTPUT SWING OVERHEAD vs TEMPERATURE (AVERAGE OF UNITS FROM LOTS) FIGURE. OUTPUT VOLTAGE SWING vs LOAD RESISTANCE FN8. May,

16 HA- Typical Performance Curves V SUPPLY = ±V, A V = +, R F = kω, R L = Ω, T A = + C, unless otherwise specified 7. SHORT CIRCUIT CURRENT (ma) ISC -ISC PROPAGATION DELAY (ns) R LOAD = Ω V OUT = V P-P FIGURE. SHORT CIRCUIT CURRENT LIMIT vs TEMPERATURE FIGURE. PROPAGATION DELAY vs TEMPERATURE (AVERAGE OF 8 UNITS FROM LOTS) PROPAGATION DELAY (ns) R LOAD = Ω V OUT = V P-P A V = + (R F = 8Ω) A V = + A V = + OVERSHOOT (%) V OUT = mv P-P, C L = pf V SUPPLY = ±V A V = + A V = + V SUPPLY = ±V A V = + A V = SUPPLY VOLTAGE (±V) 6 LOAD RESISTANCE (Ω) 8 FIGURE. PROPAGATION DELAY vs SUPPLY VOLTAGE (AVERAGE OF 8 UNITS FROM LOTS) FIGURE. SMALL SIGNAL OVERSHOOT vs LOAD RESISTANCE DISTORTION (dbc) V O = V P-P C L = pf HD HD RD ORDER IMD (GENERATOR) RD ORDER IMD HD (GEN) DIFFERENTIAL GAIN (%) FREQUENCY =.8MHz R LOAD = 7Ω R LOAD = Ω R LOAD = K HD (GEN) M M. 7 9 SUPPLY VOLTAGE (±V) FIGURE. DISTORTION vs FREQUENCY FIGURE 6. DIFFERENTIAL GAIN vs SUPPLY VOLTAGE (AVERAGE OF 8 UNITS FROM LOTS) 6 FN8. May,

17 HA- Typical Performance Curves V SUPPLY = ±V, A V = +, R F = kω, R L = Ω, T A = + C, unless otherwise specified.7 FREQUENCY =.8MHz DIFFERENTIAL PHASE ( ) R LOAD = 7Ω R LOAD = Ω SLEW RATE (V/μs) 8 V OUT = V P-P -SLEW RATE +SLEW RATE. R LOAD = K 7 9 SUPPLY VOLTAGE (±V) FIGURE 7. DIFFERENTIAL PHASE vs SUPPLY VOLTAGE (AVERAGE OF 8 UNITS FROM LOTS) FIGURE 8. SLEW RATE vs TEMPERATURE (AVERAGE OF UNITS FROM LOTS) Typical Performance Curves V SUPPLY = ±V, A V = +, R F = kω, R L = Ω, T A = C, Unless Otherwise Specified NORMALIZED GAIN (db) A V + A V A V M M M M FIGURE 9. NON-INVERTING FREQUENCY RESPONSE NORMALIZED GAIN (db) A V = - A V = - A V = - M M M M FIGURE. INVERTING FREQUENCY RESPONSE NON-INVERTING PHASE ( ) A V + A V - A V + A V - M M M M INVERTING PHASE ( ) -db BANDWIDTH (MHz) V OUT =.V P-P C L = pf A V = + -db BANDWIDTH GAIN PEAKING 7 9 FEEDBACK RESISTOR (Ω) GAIN PEAKING (db) FIGURE. PHASE RESPONSE AS A FUNCTION OF FREQUENCY FIGURE. BANDWIDTH AND GAIN PEAKING vs FEEDBACK RESISTANCE 7 FN8. May,

18 HA- Typical Performance Curves V SUPPLY = ±V, A V = +, R F = kω, R L = Ω, T A = C, Unless Otherwise Specified (Continued) -db BANDWIDTH (MHz) 9 9 -db BANDWIDTH GAIN PEAKING FEEDBACK RESISTOR (Ω) V OUT =.V P-P C L = pf A V = + FIGURE. BANDWIDTH AND GAIN PEAKING vs FEEDBACK RESISTANCE GAIN PEAKING (db) -db BANDWIDTH (MHz) -db BANDWIDTH 9 V OUT =.V GAIN PEAKING P-P C L = pf A V = LOAD RESISTOR (Ω) FIGURE. BANDWIDTH AND GAIN PEAKING vs LOAD RESISTANCE 6 GAIN PEAKING (db) -db BANDWIDTH (MHz) 8 6 V OUT =.V P-P C L = pf A V = + REJECTION RATIO (db) A V = + CMRR NEGATIVE PSRR FEEDBACK RESISTOR (Ω) FIGURE. BANDWIDTH vs FEEDBACK RESISTANCE -8 POSITIVE PSRR.M.M.M M M M FIGURE 6. REJECTION RATIOS vs FREQUENCY PROPAGATION DELAY (ns) R L = Ω V OUT =.V P-P A V = + SLEW RATE (V/μs) V OUT = V P-P + SLEW RATE - SLEW RATE FIGURE 7. PROPAGATION DELAY vs TEMPERATURE FIGURE 8. SLEW RATE vs TEMPERATURE 8 FN8. May,

19 HA- Typical Performance Curves V SUPPLY = ±V, A V = +, R F = kω, R L = Ω, T A = C, Unless Otherwise Specified (Continued) NORMALIZED GAIN (db) V OUT =.V P-P C L = pf A V = +, R F = kω -. A V =, R F = 8Ω -. M M M M M M A V = +, R F = 68Ω A V = +, R F = kω NORMALIZED GAIN (db).8.6. V OUT =.V P-P C L = pf R F = 7Ω. A V = A V = A V = - -. A V = - -. M M M M M M FIGURE 9. NON-INVERTING GAIN FLATNESS vs FREQUENCY FIGURE. INVERTING GAIN FLATNESS vs FREQUENCY VOLTAGE NOISE (nv/ Hz) 8 6 A V =, R F = 8Ω -INPUT NOISE CURRENT +INPUT NOISE CURRENT +INPUT NOISE VOLTAGE 8 6 CURRENT NOISE (pa/ Hz) REJECTION RATIO (db) CMRR +PSRR -PSRR.k.k k k k FIGURE. INPUT NOISE CHARACTERISTICS FIGURE. REJECTION RATIO vs TEMPERATURE. 8 ENABLE 8 6 OUTPUT SWING (V).8 ENABLE TIME (ns) DISABLE ENABLE 8 6 DISABLE TIME (μs) DISABLE OUTPUT VOLTAGE (V) FIGURE. OUTPUT SWING vs TEMPERATURE FIGURE. ENABLE/DISABLE TIME vs OUTPUT VOLTAGE 9 FN8. May,

20 HA- Typical Performance Curves V SUPPLY = ±V, A V = +, R F = kω, R L = Ω, T A = C, Unless Otherwise Specified (Continued) FEEDTHROUGH (db) DISABLE = V V IN = V P-P R F = 7Ω.M M M M FIGURE. DISABLE FEEDTHROUGH vs FREQUENCY TRANSIMPEDANCE (MΩ)... R L = Ω M.M.M M M M FIGURE 6. TRANSIMPEDANCE vs FREQUENCY PHASE ANGLE ( ) TRANSIMPEDANCE (MΩ) R L = Ω M.M.M M M M FIGURE 7. TRANSIMPEDENCE vs FREQUENCY PHASE ANGLE ( ) For additional products, see Intersil products are manufactured, assembled and tested utilizing ISO9 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see FN8. May,

21 HA- Die Characteristics DIE DIMENSIONS: 6μm x μm x 8μm METALLIZATION: Type: Aluminum, % Copper Thickness: 6kÅ ±kå SUBSTRATE POTENTIAL (Powered Up): V- PASSIVATION: Type: Nitride over Silox Silox Thickness: kå ±kå Nitride Thickness:.kÅ ±kå TRANSISTOR COUNT: 6 PROCESS: High Frequency Bipolar Dielectric Isolation Metallization Mask Layout HA- BAL DISABLE V+ IN OUT IN+ V- BAL FN8. May,

22 HA- Dual-In-Line Plastic Packages (PDIP) INDEX AREA BASE PLANE SEATING PLANE D B -C- -A- N N/ B D e D E -B- A. (.) M C A A L B S NOTES:. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control.. Dimensioning and tolerancing per ANSI Y.M-98.. Symbols are defined in the MO Series Symbol List in Section. of Publication No. 9.. Dimensions A, A and L are measured with the package seated in JEDEC seating plane gauge GS-.. D, D, and E dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed. inch (.mm). 6. E and e A are measured with the leads constrained to be perpendicular to datum -C-. 7. e B and e C are measured at the lead tips with the leads unconstrained. e C must be zero or greater. 8. B maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed. inch (.mm). 9. N is the maximum number of terminal positions.. Corner leads (, N, N/ and N/ + ) for E8., E6., E8., E8., E.6 will have a B dimension of. -. inch (.76 -.mm). A e C E C L e A C e B E8. (JEDEC MS--BA ISSUE D) 8 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A A B B , C D D E E e. BSC. BSC - e A. BSC 7.6 BSC 6 e B L N Rev. /9 FN8. May,

23 HA- Package Outline Drawing M8. 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE Rev, / DETAIL "A".7 (.). (.6) INDEX AREA. (.7).8 (.) 6. (.).8 (.8). (.). (.) x TOP VIEW 8. (.).9 (.8) SIDE VIEW B. (.87) SEATING PLANE 8. (.97).8 (.89).7 (.69). (.) 7.6 (.).7 (.) 6 -C-.7 (.).(.).(.).(.).(.).(.) SIDE VIEW A TYPICAL RECOMMENDED LAND PATTERN NOTES:. Dimensioning and tolerancing per ANSI Y.M-99.. Package length does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed.mm (.6 inch) per side.. Package width does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed.mm (. inch) per side.. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area.. Terminal numbers are shown for reference only. 6. The lead width as measured.6mm (. inch) or greater above the seating plane, shall not exceed a maximum value of.6mm (. inch). 7. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 8. This outline conforms to JEDEC publication MS--AA ISSUE C. FN8. May,