DATASHEET ICL7611, ICL7612. Features. Applications. Pinouts. 1.4MHz, Low Power CMOS Operational Amplifiers. FN2919 Rev 9.

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1 DATASHEET ICL711, ICL71 1.MHz, Low Power CMOS Operational Amplifiers The ICL71X series is a family of CMOS operational amplifiers. These devices provide the designer with high performance operation at low supply voltages and selectable quiescent currents, and are an ideal design tool when ultra low input current and low power dissipation are desired. The basic amplifier will operate at supply voltages ranging from 1V to V, and may be operated from a single Lithium cell. A unique quiescent current programming pin allows setting of standby current to 1mA, A, or A, with no external components. This results in power consumption as low as W. The output swing ranges to within a few millivolts of the supply voltages. Of particular significance is the extremely low (1pA) input current, input noise current of.1pa/ Hz, and 1 input impedance. These features optimize performance in very high source impedance applications. The inputs are internally protected. Outputs are fully protected against short circuits to ground or to either supply. AC performance is excellent, with a slew rate of 1.V/ s, and unity gain bandwidth of Hz at. Features FN919 Rev 9. Wide Operating Voltage Range V to V High Input Impedance Programmable Power Consumption..... Low as W Input Current Lower Than BIFETs pA (Typ) Output Voltage Swing V and V Input Common Mode Voltage Range Greater Than Supply Rails (ICL71) PbFree Plus Anneal Available (RoHS Compliant) Applications Portable Instruments Telephone Headsets Hearing Aid/Microphone Amplifiers Meter Amplifiers Medical Instruments High Impedance Buffers Because of the low power dissipation, junction temperature rise and drift are quite low. Applications utilizing these features may include stable instruments, extended life designs, or high density packages. Pinouts ICL711, ICL71 ( LD PDIP, LD SOIC) TOP VIEW BAL 1 I Q SET IN IN 3 7 V OUT V 5 BAL FN919 Rev 9. Page 1 of 13

2 Ordering Information PART NUMBER PART MARKING TEMP. RANGE ( C) PACKAGE PKG. DWG. # ICL711DCBA 711 DCBA to 7 Ld SOIC (15 mil) M.15 ICL711DCBAZ (Note) 711 DCBAZ to 7 Ld SOIC (15 mil) (Pbfree) M.15 ICL711DCBAT 711 DCBA to 7 Ld SOIC (15 mil) Tape and Reel M.15 ICL711DCBAZT (Note) 711 DCBAZ to 7 Ld SOIC (15 mil) Tape and Reel (Pbfree) M.15 ICL711DCPA 711 DCPA to 7 Ld PDIP E.3 ICL711DCPAZ (Note) 711 DCPAZ to 7 Ld PDIP* (Pbfree) E.3 ICL71BCPA 71 BCPA to 7 Ld PDIP E.3 ICL71BCPAZ 71 BCPAZ to 7 Ld PDIP* (Pbfree) E.3 ICL71DCBA 71 DCBA to 7 Ld SOIC (15 mil) M.15 ICL71DCBAT 71 DCBA to 7 Ld SOIC (15 mil) Tape and Reel M.15 ICL71DCBAZ (Note) 71 DCBAZ to 7 Ld SOIC (15 mil) (Pbfree) M.15 ICL71DCBAZT (Note) 71 DCBAZ to 7 Ld SOIC (15 mil) Tape and Reel (Pbfree) M.15 ICL71DCPA 71 DCPA to 7 Ld PDIP E.3 ICL71DCPAZ (Note) 71 DCPAZ to 7 Ld PDIP* (Pbfree) E.3 *Pbfree PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. NOTE: Intersil Pbfree plus anneal products employ special Pbfree material sets; molding compounds/die attach materials and % matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pbfree soldering operations. Intersil Pbfree products are MSL classified at Pbfree peak reflow temperatures that meet or exceed the Pbfree requirements of IPC/JEDEC J STD. FN919 Rev 9. Page of 13

3 Absolute Maximum Ratings Supply Voltage V to V V Input Voltage V.3 to V.3V Differential Input Voltage (Note 1) [(V.3) (V.3)]V Duration of Output Short Circuit (Note ) Unlimited Operating Conditions Temperature Range ICL71XC C to 7 C Thermal Information Thermal Resistance (Typical, Note 3) JA ( C/W) PDIP Package* SOIC Package Maximum Junction Temperature (Plastic Package) C Maximum Storage Temperature Range C to 15 C Pbfree reflow profile see link below *Pbfree PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Long term offset voltage stability will be degraded if large input differential voltages are applied for long periods of time.. The outputs may be shorted to ground or to either supply, for V SUPPLY V. Care must be taken to insure that the dissipation rating is not exceeded. 3. JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications V SUPPLY = 5V, Unless Otherwise Specified. PARAMETER SYMBOL TEST CONDITIONS TEMP ( C) ICL71B ICL711D, ICL71D MIN TYP MAX MIN TYP MAX UNITS Input Offset Voltage V OS R S k mv Full 7 mv Temperature Coefficient of V OS V OS / T R S k 15 5 V/ C Input Offset Current I OS pa Full 3 3 pa Input Bias Current I BIAS pa Full pa Common Mode Voltage Range (ICL711 Only) V CMR I Q = A 5. V I Q = A 5. V V Extended Common Mode Voltage Range (ICL71 Only) V CMR I Q = A V I Q = A 5 5.3, , 5.1 V 5 5.3,.5 5.3,.5 V Output Voltage Swing V OUT I Q = A, R L = V Full.. V I Q = A, R L = k V Full.. V, R L = k V Full.3.3 V Large Signal Voltage Gain A VOL V O =.V, R L =, I Q = A V O =.V, R L =k, I Q = A V O =.V, R L = k, 5 db Full db 5 db Full db db Full 7 7 db FN919 Rev 9. Page 3 of 13

4 Electrical Specifications PARAMETER Unity Gain Bandwidth GBW I Q = A 5.. MHz I Q = A 5.. MHz MHz Input Resistance R IN Common Mode Rejection Ratio CMRR R S k I Q = A db R S k I Q = A db R S k db Power Supply Rejection Ratio (V SUPPLY = V to V) PSRR R S k I Q = A db R S k 5 db I Q = A R S k db Input Referred Noise Voltage e N R S =, f = 1kHz 5 nv/ Hz Input Referred Noise Current i N R S =, f = 1kHz pa/ Hz Supply Current (No Signal, No Load) I SUPPLY I Q SET = 5V, Low Bias ma I Q SET = V, ma Medium Bias I Q SET = 5V, High Bias ma Channel Separation V O1 /V O A V = db Slew Rate SR I Q = A, R L = V/ s (A V = 1, C L = pf, V IN = V PP ) I Q = A, R L =k V/ s, R L = k V/ s Rise Time (V IN = 5mV, C L = pf) Overshoot Factor (V IN = 5mV, C L = pf) V SUPPLY = 5V, Unless Otherwise Specified. (Continued) SYMBOL TEST CONDITIONS TEMP ( C) ICL71B ICL711D, ICL71D MIN TYP MAX MIN TYP MAX t r I Q = A, R L = 5 s I Q = A, 5 s R L = k, R L = k s OS I Q = A, R L = % I Q = A, 5 % R L = k, R L = k 5 % UNITS Electrical Specifications V SUPPLY = 1V, I Q = A, Unless Otherwise Specified. PARAMETER SYMBOL TEST CONDITIONS TEMP ( C) ICL71B MIN TYP MAX UNITS Input Offset Voltage V OS R S k 5 5 mv Full 7 mv Temperature Coefficient of V OS V OS / T R S k 15 V/ C Input Offset Current I OS pa Full 3 pa Input Bias Current I BIAS pa Full 5 pa Extended Common Mode Voltage Range V CMR 5. to 1.1 V FN919 Rev 9. Page of 13

5 Electrical Specifications V SUPPLY = 1V, I Q = A, Unless Otherwise Specified. (Continued) PARAMETER SYMBOL TEST CONDITIONS TEMP ( C) ICL71B MIN TYP MAX UNITS Output Voltage Swing V OUT R L = 5.9 V Full.9 V Large Signal Voltage Gain A VOL V O =.1V, R L = 5 9 db Full db Unity Gain Bandwidth GBW 5. MHz Input Resistance R IN 5 1 Common Mode Rejection Ratio CMRR R S k 5 db Power Supply Rejection Ratio PSRR R S k 5 db Input Referred Noise Voltage e N R S =, f = 1kHz 5 nv/ Hz Input Referred Noise Current i N R S =, f = 1kHz 5.1 pa/ Hz Supply Current I SUPPLY No Signal, No Load 5 15 A Slew Rate SR A V = 1, C L = pf, V IN =.V PP, R L = 5.1 V/ s Rise Time t r V IN = 5mV, C L = pf R L = 5 s Overshoot Factor OS V IN = 5mV, C L = pf, R L = 5 5 % Schematic Diagram INPUT STAGE I Q SETTING STAGE OUTPUT STAGE V BAL 3k 3k 9k BAL k Q P5 Q P Q P7 Q P.3V Q P1 Q P1 Q P3 Q P V Q P9 INPUT V V Q N1 Q N C FF = 9pF C C = 33pF OUTPUT INPUT Q N7 V Q N Q N5 Q N Q N9 Q N.3V Q N11 Q N3 Q N V V I Q SET FN919 Rev 9. Page 5 of 13

6 Application Information Static Protection All devices are static protected by the use of input diodes. However, strong static fields should be avoided, as it is possible for the strong fields to cause degraded diode junction characteristics, which may result in increased input leakage currents. Latchup Avoidance Junctionisolated CMOS circuits employ configurations which produce a parasitic layer (PNPN) structure. The layer structure has characteristics similar to an SCR, and under certain circumstances may be triggered into a low impedance state resulting in excessive supply current. To avoid this condition, no voltage greater than.3v beyond the supply rails may be applied to any pin. In general, the op amp supplies must be established simultaneously with, or before any input signals are applied. If this is not possible, the drive circuits must limit input current flow to ma to prevent latchup. Choosing the Proper I Q The ICL711 and ICL71 have a similar I Q setup scheme, which allows the amplifier to be set to nominal quiescent currents of A, A or 1mA. These current settings change only very slightly over the entire supply voltage range. The ICL711 and ICL71 have an external I Q control terminal, permitting user selection of quiescent current. To set the I Q connect the I Q terminal as follows: I Q = A I Q pin to V I Q = A I Q pin to ground. If this is not possible, any voltage from V. to V. can be used. I Q pin to V NOTE: The output current available is a function of the quiescent current setting. For maximum peaktopeak output voltage swings into low impedance loads, IQ of 1mA should be selected. Output Stage and Load Driving Considerations Each amplifiers quiescent current flows primarily in the output stage. This is approximately 7% of the I Q settings. This allows output swings to almost the supply rails for output loads of, k, and k, using the output stage in a highly linear class A mode. In this mode, crossover distortion is avoided and the voltage gain is maximized. However, the output stage can also be operated in Class AB for higher output currents. (See graphs under Typical Operating Characteristics). During the transition from Class A to Class B operation, the output transfer characteristic is nonlinear and the voltage gain decreases. Input Offset Nulling Offset nulling may be achieved by connecting a 5k pot between the BAL terminals with the wiper connected to V. At quiescent currents of 1mA and A the nulling range provided is adequate for all V OS selections; however with I Q = A, nulling may not be possible with higher values of V OS. Frequency Compensation The ICL711 and ICL71 are internally compensated, and are stable for closed loop gains as low as unity with capacitive loads up to pf. Extended Common Mode Input Range The ICL71 incorporates additional processing which allows the input CMVR to exceed each power supply rail by.1v for applications where V SUPP 1.5V. For those applications where V SUPP 1.5V the input CMVR is limited in the positive direction, but may exceed the negative supply rail by.1v in the negative direction (e.g., for V SUPPLY = 1V, the input CMVR would be.v to 1.1V). Operation At V SUPPLY = 1V Operation at V SUPPLY = 1V is guaranteed at I Q = A for A and B grades only. Output swings to within a few millivolts of the supply rails are achievable for R L. Guaranteed input CMVR is.v minimum and typically.9v to.7v at V SUPPLY = 1V. For applications where greater common mode range is desirable, refer to the description of ICL71 above. Typical Applications The user is cautioned that, due to extremely high input impedances, care must be exercised in layout, construction, board cleanliness, and supply filtering to avoid hum and noise pickup. Note that in no case is I Q shown. The value of I Q must be chosen by the designer with regard to frequency response and power dissipation. V IN V IN k ICL71 R L k FIGURE 1. SIMPLE FOLLOWER (NOTE ) 5 5 ICL71 VOUT VOUT TO CMOS OR LPTTL LOGIC NOTE:. By using the ICL71 in this application, the circuit will follow rail to rail inputs. FIGURE. LEVEL DETECTOR (NOTE ) FN919 Rev 9. Page of 13

7 1 F ICL711 V OUT ICL711 ICL711 V V DUTY CYCLE k WAVEFORM GENERATOR NOTE: Low leakage currents allow integration times up to several hours. FIGURE 3. PHOTOCURRENT INTEGRATOR NOTE: Since the output range swings exactly from rail to rail, frequency and duty cycle are virtually independent of power supply variations. FIGURE. PRECISE TRIANGLE/SQUARE WAVE GENERATOR V OH V.5 F V IN k.m ICL711 F 1.k = 5% SCALE ADJUST k k TO SUCCEED ING INPUT STAGE V OL V V OUT I Q T A = 15 C V COMMON ICL711 V FIGURE 5. AVERAGING AC TO DC CONVERTER FOR A/D CONVERTERS SUCH AS ICL7, ICL77, ICL79, ICL711, ICL7117 FIGURE. BURNIN AND LIFE TEST CIRCUIT V IN BAL V OUT BAL 5k V FIGURE 7. V OS NULL CIRCUIT FN919 Rev 9. Page 7 of 13

8 . F. F. F INPUT 3k 1k.1 F ICL711 3k k k. F 51k.1 F ICL711 OUTPUT 3k (NOTE 5) FIGURE. FIFTH ORDER CHEBYCHEV MULTIPLE FEEDBACK LOW PASS FILTER (NOTE 5) NOTES: 5. Note that small capacitors (5pF to 5pF) may be needed for stability in some cases.. The low bias currents permit high resistance and low capacitance values to be used to achieve low frequency cutoff. f C = Hz, A VCL =, Passband ripple =.1dB. Typical Performance Curves SUPPLY CURRENT ( A) k 1k T A = 5 C NO LOAD NO SIGNAL I Q = A I Q = A 1mA SUPPLY CURRENT ( A) 3 V V = V NO LOAD NO SIGNAL I Q = A I Q = A SUPPLY VOLTAGE (V) FIGURE 9. SUPPLY CURRENT PER AMPLIFIER vs SUPPLY VOLTAGE FREEAIR TEMPERATURE ( C) FIGURE. SUPPLY CURRENT PER AMPLIFIER vs FREEAIR TEMPERATURE INPUT BIAS CURRENT (pa) 1. V S = 5V DIFFERENTIAL VOLTAGE GAIN (kv/v) V SUPP = V V OUT = V R L = k I Q = A R L = k R L = I Q = A FREEAIR TEMPERATURE ( C) FREEAIR TEMPERATURE ( C) FIGURE 11. INPUT BIAS CURRENT vs TEMPERATURE FIGURE 1. LARGE SIGNAL DIFFERENTIAL VOLTAGE GAIN vs FREEAIR TEMPERATURE FN919 Rev 9. Page of 13

9 Typical Performance Curves (Continued) DIFFERENTIAL VOLTAGE GAIN (V/V) 7 5 T A = 5 C V SUPP = 15V I Q = A 3 5 PHASE SHIFT () I Q = A k k k FREQUENCY (Hz) FIGURE 13. LARGE SIGNAL FREQUENCY RESPONSE PHASE SHIFT ( ) COMMON MODE REJECTION RATIO (db) V SUPP = V I Q = A I Q = A FREEAIR TEMPERATURE ( C) FIGURE 1. COMMON MODE REJECTION RATIO vs FREEAIR TEMPERATURE SUPPLY VOLTAGE REJECTION RATIO (db) V SUPP = V I Q = A I Q = A FREEAIR TEMPERATURE ( C) EQUIVALENT INPUT NOISE VOLTAGE (nv/ Hz) 5 3 T A = 5 C 3V V SUPP 1V 1k k k FREQUENCY (Hz) FIGURE 15. POWER SUPPLY REJECTION RATIO vs FREEAIR TEMPERATURE FIGURE 1. EQUIVALENT INPUT NOISE VOLTAGE vs FREQUENCY MAXIMUM OUTPUT VOLTAGE (V PP ) V SUPP = V V SUPP = 5V T A = 5 C I Q = A I Q = A V SUPP = V 1k k k M FREQUENCY (Hz) MAXIMUM OUTPUT VOLTAGE (V PP ) V SUPP = V T A = 55 C T A = 5 C T A = 15 C k k M FREQUENCY (Hz) FIGURE 17. OUTPUT VOLTAGE vs FREQUENCY FIGURE 1. OUTPUT VOLTAGE vs FREQUENCY FN919 Rev 9. Page 9 of 13

10 Typical Performance Curves (Continued) MAXIMUM OUTPUT VOLTAGE (V PP ) T A = 5 C R L = k R L = k MAXIMUM OUTPUT VOLTAGE (V PP ) 1 R L = k V SUPP = V R L = k R L = k SUPPLY VOLTAGE (V) FIGURE 19. OUTPUT VOLTAGE vs SUPPLY VOLTAGE FREEAIR TEMPERATURE ( C) FIGURE. OUTPUT VOLTAGE vs FREEAIR TEMPERATURE MAXIMUM OUTPUT SOURCE CURRENT (ma) SUPPLY VOLTAGE (V) MAXIMUM OUTPUT SINK CURRENT (ma) I Q = A I Q = A SUPPLY VOLTAGE (V) FIGURE 1. OUTPUT SOURCE CURRENT vs SUPPLY VOLTAGE FIGURE. OUTPUT SINK CURRENT vs SUPPLY VOLTAGE MAXIMUM OUTPUT VOLTAGE (V PP ) T A = 5 C V V = V INPUT AND OUTPUT VOLTAGE (V) T A = 5 C, V SUPP = V R L = k, C L = pf OUTPUT INPUT.1 1. LOAD RESISTANCE (k ) 1 TIME ( s) FIGURE 3. OUTPUT VOLTAGE vs LOAD RESISTANCE FIGURE. VOLTAGE FOLLOWER LARGE SIGNAL PULSE RESPONSE () FN919 Rev 9. Page of 13

11 Typical Performance Curves (Continued) INPUT AND OUTPUT VOLTAGE (V) T A = 5 C, V SUPP = V R L = k, C L = pf OUTPUT INPUT INPUT AND OUTPUT VOLTAGE (V) T A = 5 C, V SUPP = V R L =, C L = pf OUTPUT INPUT 1 TIME ( s) 1 TIME ( s) FIGURE 5. VOLTAGE FOLLOWER LARGE SIGNAL PULSE RESPONSE (I Q = A) FIGURE. VOLTAGE FOLLOWER LARGE SIGNAL PULSE RESPONSE (I Q = A) FN919 Rev 9. Page 11 of 13

12 Small Outline Plastic Packages (SOIC) N INDEX AREA 1 3 e D B.5(.) M C A M E B A C SEATING PLANE A B S H.5(.) M B A1.(.) L M h x 5 NOTES: 1. Symbols are defined in the MO Series Symbol List in Section. of Publication Number 95.. Dimensioning and tolerancing per ANSI Y1.5M Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed.15mm (. inch) per side.. Dimension E does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed.5mm (. inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area.. L is the length of terminal for soldering to a substrate. 7. N is the number of terminal positions.. Terminal numbers are shown for reference only. 9. The lead width B, as measured.3mm (.1 inch) or greater above the seating plane, shall not exceed a maximum value of.1mm (. inch).. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. C M.15 (JEDEC MS1AA ISSUE C) LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A B C D E e.5 BSC 1.7 BSC H h L N 7 Rev. 1 /5 FN919 Rev 9. Page 1 of 13

13 DualInLine Plastic Packages (PDIP) INDEX AREA BASE PLANE SEATING PLANE D1 B1 C A N 1 3 N/ B D e D1 E1 B A 1. (.5) M C A A L B S NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control.. Dimensioning and tolerancing per ANSI Y1.5M Symbols are defined in the MO Series Symbol List in Section. of Publication No Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed. inch (.5mm).. E and e A are measured with the leads constrained to be perpendicular to datum C. 7. e B and e C are measured at the lead tips with the leads unconstrained. e C must be zero or greater.. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed. inch (.5mm). 9. N is the maximum number of terminal positions.. Corner leads (1, N, N/ and N/ 1) for E.3, E1.3, E1.3, E.3, E. will have a B1 dimension of.3.5 inch (.7 1.1mm). A e C E C L e A C e B E.3 (JEDEC MS1BA ISSUE D) LEAD DUALINLINE PLASTIC PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A A B B , C D D E E e. BSC.5 BSC e A.3 BSC 7. BSC e B L N 9 Rev. 1/93 Copyright Intersil Americas LLC 7. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see Intersil products are manufactured, assembled and tested utilizing ISO91 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see FN919 Rev 9. Page 13 of 13