HA MHz Video Buffer. Description. Features. Applications. Ordering Information. Pinouts. April 1997

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1 SEMICONDUCTOR HA-533 April MHz Video Buffer Features Differential Phase Error Degrees Differential Gain Error % High Slew Rate /µs Wide Bandwidth (Small Signal) MHz Wide Power Bandwidth DC to 7.5MHz Fast Rise Time ns High Output Drive ± With Ω Load Wide Power Supply Range ±5V to ±6V Replace Costly Hybrids Applications Video Buffer High Frequency Buffer Isolation Buffer High Speed Line Driver Impedance Matching Current Boosters High Speed A/D Input Buffers Related Literature - AN548, Designer s Guide for HA-533 Description The HA-533 is a unity gain monolithic IC designed for any application requiring a fast, wideband buffer. Featuring a bandwidth of 25MHz and outstanding differential phase/ gain characteristics, this high performance voltage follower is an excellent choice for video circuit design. Other features, which include a minimum slew rate of /µs and high output drive capability, make the HA-533 applicable for line driver and high speed data conversion circuits. The high performance of this product is a result of the Harris Dielectric Isolation process. A major feature of this process is that it produces both PNP and NPN high frequency transistors which makes wide bandwidth designs, such as the HA-533, practical. Alternative process methods typically produce a lower AC performance. Ordering Information PART NUMBER (BRAND) TEMP. RANGE ( o C) PACKAGE PKG. NO. HA to 25 2 Pin Metal Can T2.C HA to 75 2 Pin Metal Can T2.C HA to 75 8 Ld PDIP E8.3 HA4P533-5 to 75 2 Ld PLCC N2.35 HA9P533-5 (H5335) to 6 (Note 3) 8 Ld PSOP M8.5A Pinouts HA-533 (PDIP, PSOP) TOP VIEW HA-533 (PLCC) TOP VIEW HA-533 (METAL CAN) TOP VIEW OUT SUB- STRATE 4 5 OUT IN IN CASE OUT 9 SUB- STRATE 4 +IN CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright Harris Corporation 997 File Number

2 HA-533 Absolute Maximum Ratings Voltage Between and Pins DC Input Voltage to Output Current (Peak) (5ms On/ Second Off) ±2mA ESD Rating Human Body Model (Per MIL-STD-883 Method 35.7).. 2 Operating Conditions Temperature Ranges HA o C to 25 o C HA (Note 3) o C to 75 o C HA9P533-5 (Notes, 3) o C to 6 o C Thermal Information Thermal Resistance (Typical, Note 2) θ JA ( o C/W) θ JC ( o C/W) Metal Can Package PDIP Package N/A PSOP Package (Note 4) N/A PLCC Package N/A Maximum Junction Temperature (Note ) o C Maximum Junction Temperature (Plastic Packages) o C Maximum Storage Temperature Range o C to 5 o C Maximum Lead Temperature (Soldering s) o C (PSOP and PLCC - Lead Tips Only) CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES:. Maximum power dissipation, including load conditions, must be designed to maintain the maximum junction temperature below 75 o C for the metal can package, and below 5 o C for the plastic packages (See Figure 5.). 2. θ JA is measured with the component mounted on an evaluation PC board in free air. 3. Maximum operating temperature in the PSOP package is limited to 6 o C, for V SUPPLY = ±2V to prevent the junction temperature from exceeding 5 o C. The maximum operating temperature may have to be derated further, depending on the output load condition. The operating temperature may be increased if the HA9P533 is operated at lower V SUPPLY. For example, the quiescent operating temperature may be increased to 75 o C by operating at V SUPPLY ±9.7V. See Figure 5 for more information. 4. Direct attach of the PSOP copper slug to copper area on the PCB can reduce the θ JA value to < o C/W. Consult the Harris Application Group for more information. Electrical Specifications V SUPPLY = ±2V, R S = 5Ω, R L = Ω, C L = pf, Unless Otherwise Specified TEST TEMP. HA HA PARAMETER CONDITIONS ( o C) MIN TYP MAX MIN TYP MAX UNITS INPUT CHARACTERISTICS Offset Voltage mv Full mv Average Offset Voltage Drift Full µv/ o C Bias Current µa Full µa Input Resistance MΩ Input Capacitance pf Input Noise Voltage Hz to MHz µv P-P TRANSFER CHARACTERISTICS Voltage Gain R L = Ω V/V R L = kω V/V R L = Ω Full V/V -3dB Bandwidth MHz OUTPUT CHARACTERISTICS Output Voltage Swing R L = Ω Full ±8 ± - ±8 ± - V R L = kω, V S = ±5V Full ± ±2 - ± ±2 - V Output Current 25 ±8 ± - ±8 ± - ma Output Resistance Ω Full Power Bandwidth V OUT = V RMS, R L = kω MHz Full Power Bandwidth (Note 5) MHz TRANSIENT RESPONSE Rise Time V OUT = 5mV ns Propagation Delay ns Overshoot % Slew Rate (Note 5) V/ns Settling Time to.% ns 2

3 HA-533 Electrical Specifications V SUPPLY = ±2V, R S = 5Ω, R L = Ω, C L = pf, Unless Otherwise Specified (Continued) PARAMETER TEST CONDITIONS TEMP. ( o C) HA HA MIN TYP MAX MIN TYP MAX Differential Phase Error (Note 6) Degree Differential Gain Error (Note 6) % POWER SUPPLY CHARACTERISTICS Supply Current ma Full ma Power Supply Rejection Ratio Full db Harmonic Distortion = V RMS at khz 25 - <. - - <. - % NOTES: 5. V SUPPLY = ±5V, V OUT = ±, R L = kω. 6. Differential gain and phase error are nonlinear signal distortions found in video systems and are defined as follows: Differential gain error is defined as the change in amplitude at the color subcarrier frequency as the picture signal is varied from blanking to white level. Differential phase error is defined as the change in the phase of the color subcarrier as the picture signal is varied from blanking to white level. R L = 3Ω. UNITS Test Circuits and Waveforms +5V.µF +2V.µF IN OUT IN OUT R L Ω.µF.µF -5V FIGURE. SLEW RATE AND SETTLING TIME -2V FIGURE 2. TRANSIENT RESPONSE INPUT 9% OUTPUT V % ERROR BAND INPUT 9% OUTPUT % 5mV OVERSHOOT t SLEW RATE = V/ t FIGURE 3. SETTLING TIME ±mv FROM FINAL VALUE NOTE: Measured on both positive and negative transitions. FIGURE 4. RISE TIME V OUT V OUT T A = 25 o C, R S = 5Ω, R L = Ω T A = 25 o C, R S = 5Ω, R L = kω + RESPONSE + RESPONSE 3

4 HA-533 Test Circuits and Waveforms (Continued) 5mV 5mV V OUT Schematic Diagram T A = 25 o C, R S = 5Ω, R L = Ω PULSE RESPONSE R 5 R 4 R 2 R 2 Q 5 Q Q 6 Q Q 6 Q 2 Q R 9 Q 9 Q 7 R R 6 Q 3 R 8 Q 4 Q 8 V OUT R Q 7 Q 3 Q 5 Q 9 Q 2 Q 8 Q 4 R R 3 R 3 Application Information Layout Considerations The wide bandwidth of the HA-533 necessitates that high frequency circuit layout procedures be followed. Failure to follow these guidelines can result in marginal performance. Probably the most crucial of the RF/video layout rules is the use of a ground plane. A ground plane provides isolation and minimizes distributed circuit capacitance and inductance which will degrade high frequency performance. This ground plane shielding can also incorporate the metal case of the HA-533 since pin #2 is internally tied to the package. This feature allows the user to make metal to metal contact between the ground plane and the package, which extends shielding, provides additional heat sinking and eliminates the use of a socket, IC sockets contribute inter-lead capacitance which limits device bandwidth and should be avoided. For the PDIP, pin 6 can be tied to either supply, grounded, or simply not used. But to optimize device performance and improve isolation, it is recommended that this pin be grounded. Other considerations are proper power supply bypassing and keeping the input and output connections as short as possible which minimizes distributed capacitance and reduces board space. Power Supply Decoupling For optimum device performance, it is recommended that the positive and negative power supplies be bypassed with capacitors to ground. Ceramic capacitors ranging in value from.µf to.µf will minimize high frequency variations in supply voltage. Solid tantalum capacitors µf or larger will optimize low frequency performance. It is also recommended that the bypass capacitors be connected close to the HA-533 (preferably directly to the supply pins). 4

5 HA-533 MAXIMUM TOTAL POWER DISSIPATION (W) PDIP PLCC CAN QUIESCENT P D =.72W AT V S = ±2V, I CC = 3mA PSOP TEMPERATURE ( o C) Graph is based on: T JMAX T A P DMAX = θ JA Where: T JMAX = Maximum Junction Temperature of the Device T A = Ambient Temperature θ JA = Junction to Ambient Thermal Resistance FIGURE 5. FREE AIR POWER DISSIPATION Typical Applications (Also see Application Note AN548) R S +2V.µF 2 5 R M 5Ω RG -58 5Ω R L VIDEO SIGNAL INPUT HA-2539 R + 6Ω - R 2 5Ω 9Ω VIDEO HA-533 OUTPUT 75Ω 75Ω.µF -2V Ω FIGURE 6. VIDEO COAXIAL LINE DRIVER 5Ω SYSTEM FIGURE 7. VIDEO GAIN BLOCK V OUT V OUT T A = 25 o C, R S = 5Ω, R M = R L = 5Ω T A = 25 o C, R S = 5Ω, R M = R L = 5Ω R L V O = = R L + R M -- V 2 IN R L V O = = R L + R M -- V 2 IN POSITIVE PULSE RESPONSE NEGATIVE PULSE RESPONSE 5

6 HA-533 Typical Performance Curves 4 OFFSET VOLTAGE (mv) V S = ±2V V S = ±5V V S = ± INPUT BIAS CURRENT (µa) 3 2 V S = ±2V V S = ± V S = ±5V V S = ±5V V S = ±5V TEMPERATURE ( o C) FIGURE 8. INPUT OFFSET VOLTAGE vs TEMPERATURE TEMPERATURE ( o C) FIGURE 9. INPUT BIAS CURRENT vs TEMPERATURE 3 3 V S = ±5V, = ± V S = ±5V SUPPLY CURRENT (ma) 2 V S = ±2V V S = ± V S = ±5V SLEW RATE (V/µs) 2 FALL (R L = kω) FALL (R L = Ω) RISE (R L = kω) RISE (R L = Ω) TEMPERATURE ( o C) FIGURE. SUPPLY CURRENT vs TEMPERATURE TEMPERATURE ( o C) FIGURE. SLEW RATE vs TEMPERATURE SLEW RATE (V/µs) V S = ±5V, R L = kω T A = 25 o C, = ± RISE FALL SLEW RATE (V/µs) RISE FALL V S = ±5V, R L = Ω T A = 25 o C, = ± CAPACITAE (pf) 5, CAPACITAE (pf) 5, FIGURE 2. SLEW RATE vs LOAD CAPACITAE FIGURE 3. SLEW RATE vs LOAD CAPACITAE 6

7 HA-533 Typical Performance Curves (Continued) 8 6 V S = ±5V, T A = 25 o C R L = kω 9 7 V S = ±5V, T A = 25 o C R L = 5Ω OUTPUT INPUT V OS (mv) R L = kω R L = kω OUTPUT INPUT V OS (mv) R L = Ω R L = Ω -6 R L = kω INPUT VOLTAGE (V) FIGURE 4. GAIN ERROR vs INPUT VOLTAGE -7 R L = 5Ω INPUT VOLTAGE (V) FIGURE 5. GAIN ERROR vs INPUT VOLTAGE 6 4 V S = ±5V, V O = ± 8 V S = ±5, T A = 25 o C OUTPUT INPUT V OS (mv) R L = kω - V OUT (mv) V OUT = SINKING CURRENT V OUT = - V OUT = + V OUT = SOURCING CURRENT TEMPERATURE ( o C) I OUT (ma) 2 FIGURE 6. GAIN ERROR vs TEMPERATURE FIGURE 7. - V OUT vs I OUT 8 35 Y 2 Y 2,Y 2 PHASE ANGLE (DEGREES) Y 22 Y Y 2 MAGNITUDE (S) Y Y 2 Y Y 2 Y 22 Y FREQUEY (Hz) FREQUEY (Hz) 9 FIGURE 8. Y - PARAMETERS PHASE vs FREQUEY FIGURE 9. Y - PARAMETER MAGNITUDE vs FREQUEY 7

8 HA-533 Typical Performance Curves (Continued) POWER SUPPLY REJECTION RATIO (db) V S = ±2V, T A = 25 o C TOTAL HARMONIC DISTORTION (%) V S = ±2V, R L = Ω = V RMS K K K M M FREQUEY (Hz) FIGURE 2. POWER SUPPLY REJECTION RATIO vs FREQUEY K K K FREQUEY (Hz) FIGURE 2. TOTAL HARMONIC DISTORTION vs FREQUEY TOTAL HARMONIC DISTORTION (%)... V S = ±2V R L = ±V Ω = ±2V, R L = Ω f = khz PEAK TO PEAK OUTPUT VOLTAGE (V) T A = 25 o C V S = ±5V V S = ±5V V S = ±2V V S = ± 2 3 INPUT VOLTAGE (RMS) FIGURE 22. TOTAL HARMONIC DISTORTION vs INPUT VOLTAGE K LOAD RESISTAE (Ω) FIGURE 23. OUTPUT VOLTAGE SWING vs LOAD RESISTAE OUTPUT VOLTAGE (V RMS ) NO HEAT SINK IN FREE AIR K K M M FREQUEY (Hz) V S = ±5V, R L = Ω M G OUTPUT VOLTAGE (V RMS ) V S = ±5V, R L = kω NO HEAT SINK 4. IN FREE AIR K K M M M G FREQUEY (Hz) FIGURE 24. OUTPUT SWING vs FREQUEY (NOTE) FIGURE 25. OUTPUT SWING vs FREQUEY (NOTE) NOTE: This curve was obtained by noting the output voltage necessary to produce an observable distortion for a given frequency. If higher distortion is acceptable, then a higher output voltage for a given frequency can be obtained. However, operating the HA-533 with increased distortion (to the right of curve shown), will also be accompanied by an increase in supply current. The resulting increase in chip temperature must be considered and heat sinking will be necessary to prevent thermal runaway. This characteristic is the result of the output transistor operation. If the signal amplitude or signal frequency or both are increased beyond the curve shown, the NPN, PNP output transistors will approach a condition of being simultaneously on. Under this condition, thermal runaway can occur. Die Characteristics 8

9 HA-533 DIE DIMENSIONS: 5 mils x 67 mils x 9 mils 3µm x 7µm x 483µm METALLIZATION: Type: Al, % Cu Thickness: 6kÅ ±2kÅ PASSIVATION: Type: Nitride (Si 3 N 4 ) over Silox (SiO 2, 5% Phos.) Silox Thickness: 2kÅ ±2kÅ Nitride Thickness: 3.5kÅ ±.5kÅ SUBSTRATE POTENTIAL (Powered Up): Unbiased TRANSISTOR COUNT: 2 PROCESS: Bipolar Dielectric Isolation Metallization Mask Layout HA-533 IN OUT 9

10 HA-533 Dual-In-Line Plastic Packages (PDIP) INDEX AREA BASE PLANE SEATING PLANE D B N 2 3 N/2 B D e D -C- -A- NOTES:. Controlling Dimensions: IH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y4.5M Symbols are defined in the MO Series Symbol List in Section 2.2 of Publication No Dimensions A, A and L are measured with the package seated in JEDEC seating plane gauge GS D, D, and E dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed. inch (.25mm). 6. E and e A are measured with the leads constrained to be perpendicular to datum -C-. 7. e B and e C are measured at the lead tips with the leads unconstrained. e C must be zero or greater. 8. B maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed. inch (.25mm). 9. N is the maximum number of terminal positions.. Corner leads (, N, N/2 and N/2 + ) for E8.3, E6.3, E8.3, E28.3, E42.6 will have a B dimension of inch ( mm). E -B- A. (.25) M C A A2 L B S A e C E C L e A e B C E8.3 (JEDEC MS--BA ISSUE D) 8 LEAD DUAL-IN-LINE PLASTIC PACKAGE IHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A A B B , C D D E E e. BSC 2.54 BSC - e A.3 BSC 7.62 BSC 6 e B L N Rev. 2/93

11 .42 (.7).48 (.22) PIN () IDENTIFIER.2 (.5) MAX 3 PLCS C L D D.26 (.66).32 (.8).42 (.7).56 (.42).5 (.27) TP E E C L A A.3 (.33).2 (.53).4 (.) C.25 (.64).45 (.4) R D2/E2 D2/E2 VIEW A SEATING PLANE HA-533 Plastic Leaded Chip Carrier Packages (PLCC).2 (.5) MIN N2.35 (JEDEC MS-8AA ISSUE A) 2 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE IHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A D D D , 5 E E E , 5 N Rev. 3/95 -C-.25 (.64).45 (.4) MIN MIN VIEW A TYP. NOTES:. Controlling dimension: IH. Converted millimeter dimensions are not necessarily exact. 2. Dimensions and tolerancing per ANSI Y4.5M Dimensions D and E do not include mold protrusions. Allowable mold protrusion is. inch (.25mm) per side. 4. To be measured at seating plane -C- contact point. 5. Centerline to be determined where center leads exit plastic body. 6. N is the number of terminal positions.

12 HA-533 Power Small Outline Plastic Packages (PSOP) N INDEX AREA 2 3 N e D B.25(.) M C A BOTTOM VIEW 2 3 D E M E -B- -A- -C- POWER SOP PACKAGE (HEAT SLUG SURFACE IS ELECTRICALLY FLOATING) SEATING PLANE A B S H.25(.) M B A α.(.4) L M h x 45 o C M8.5A 8 LEAD POWER SMALL OUTLINE PLASTIC PACKAGE IHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A B C D D E E e.5 BSC.27 BSC - H h L N α o 8 o o 8 o - Rev. /96 NOTES:. Symbols are defined in the MO Series Symbol List in Section 2.2 of Publication Number Dimensioning and tolerancing per ANSI Y4.5M Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed.5mm (.6 inch) per side. 4. Dimension E does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed.25mm (. inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. L is the length of terminal for soldering to a substrate. 7. N is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width B, as measured.36mm (.4 inch) or greater above the seating plane, shall not exceed a maximum value of.6mm (.24 inch). Exposed copper heat slug flush with bottom surface of package. All other dimensions conform to JEDEC MS-2 Issue C.. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 2

13 HA-533 Metal Can Packages (Can) ØD ØD A F L Øb REFEREE PLANE A A BASE METAL NOTES:. The reference, base, and seating planes are the same for this variation. 2. Measured from maximum diameter of the product. 3. N is the maximum number of terminal positions. 4. Dimensioning and tolerancing per ANSI Y4.5M Controlling dimension: IH. e SECTION A-A LEAD FINISH Øb2 2 N k e k T2.C 2 LEAD METAL CAN PACKAGE IHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A Øb Øb ØD ØD e.4 BSC.6 BSC - e. BSC 2.54 BSC - F k k L N Rev. 5/8/94 All Harris Semiconductor products are manufactured, assembled and tested under ISO9 quality systems certification. Harris Semiconductor products are sold by description only. Harris Semiconductor reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Harris is believed to be accurate and reliable. However, no responsibility is assumed by Harris or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Harris or its subsidiaries. Sales Office Headquarters NORTH AMERICA Harris Semiconductor P. O. Box 883, Mail Stop 53-2 Melbourne, FL 3292 TEL: (47) FAX: (47) For general information regarding Harris Semiconductor and its products, call -8-4-HARRIS EUROPE Harris Semiconductor Mercure Center, Rue de la Fusee 3 Brussels, Belgium TEL: (32) FAX: (32) ASIA Harris Semiconductor PTE Ltd. No. Tannery Road Cencon, #9- Singapore 334 TEL: (65) FAX: (65) SEMICONDUCTOR 3