HI-201HS. High Speed Quad SPST CMOS Analog Switch

Transcription

1 SEMICONDUCTOR HI-HS December 99 Features Fast Switching Times, N = ns, FF = ns Low ON Resistance of Ω Pin Compatible with Standard HI- Wide Analog Voltage Range (±V Supplies) of ±V Low Charge Injection (±V Supplies) pc TTL Compatible Symmetrical Switching Analog Current Range of 8mA Applications High Speed Multiplexing High Frequency Analog Switching Sample and Hold Circuits Digital Filters Operational Amplifier Gain Switching Networks Integrator Reset Circuits Functional Diagram TTL LOGIC V+ LEVEL SHIFTER AND DRIVER LOGIC GATE SWITCH CELL SOURCE DRAIN SWITCH ON OFF GATE OUTPUT High Speed Quad SPST CMOS Analog Switch Description The HI-HS is a monolithic CMOS Analog Switch featuring very fast switching speeds and low ON resistance. The integrated circuit consists of four independently selectable SPST switches and is pin compatible with the industry standard HI- switch. Fabricated using silicon-gate technology and the Harris Dielectric Isolation process, this TTL compatible device offers improved performance over previously available CMOS analog switches. Featuring maximum switching times of ns, low ON resistance of Ω maximum, and a wide analog signal range, the HI-HS is designed for any application where improved switching performance, particularly switching speed, is required. (A more detailed discussion on the design and application of the HI-HS can be found in Application Note.) Ordering Information PART NUMBER TEMP. RANGE PACKAGE HI-HS- o C to +7 o C Lead Ceramic DIP HI-HS- - o C to +8 o C Lead Plastic DIP HI-HS- - o C to + o C Lead Ceramic DIP HI-HS- - o C to +8 o C Lead Ceramic DIP HIPHS- o C to +7 o C Lead PLCC HI-HS- o C to +7 o C Lead Plastic DIP HI-HS-7 o C to +7 o C Lead Ceramic DIP HI-HS/88 - o C to + o C Lead LCC HI9PHS- o C to +7 o C Lead SOIC (W) HI9PHS-9 - o C to +8 o C Lead SOIC (W) HI-HS/88 - o C to + o C Lead Ceramic DIP HI-HS -8 - o C to + o C Lead Ceramic DIP Pinouts HI-HS (CDIP, PDIP, SOIC) TOP VIEW HIHS (LCC) TOP VIEW HIHS (PLCC) TOP VIEW A OUT IN IN OUT A A OUT IN V+ NC IN OUT A IN IN OUT A A OUT OUT A A OUT 8 7 IN V+ IN IN IN OUT A A OUT 9 8 IN 7 V+ 7 8 IN 9 OUT A A OUT CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures. Copyright Harris Corporation File Number

2 HI-HS Schematic Diagrams TTL/CMOS REFERENCE CIRCUIT SWITCH CELL V CC P MP MP MP MP V+ Q QN QN D V R R QN C8 QP QN QN V R ANALOG IN MP MN MN MP MN ANALOG OUT C9 D.V MP QP QP Q V EE MN MN MN DIGITAL BUFFER AND LEVEL SHIFTER MN MP MP QN QN8 MP MP8 QN9 MP MP7 I Q I X I X I X QN7 V R I X MP MP MP9 MP MP MP QN VA C QP R V R I Q QP QN QP QN R R QN C MN V EE V CC MP MN MP Q Q I X IX I X CFF QP7 QP QP8 QP9 MN QP MN MN MN MN7 MN9 MN8 MN MN MN MN MN REPEAT FOR EACH LEVEL SHIFTER 9-8

3 Absolute Maximum Ratings Supply Voltage (Between Pins and ) V Digital Input Voltage (Pins, 8, 9, ) (V+) +V, () -V Analog Input Voltage (One Switch) (V+) +.V Pins,,, 7,,,, () -.V Peak Current (S or D) (Pulse at ms, % Duty Cycle Max.) ma Continuous Current Any Terminal (Except S or D) ma Storage Temperature o C to + o C Lead Temperature (Soldering s) o C Specifications HI-HS Thermal Information Thermal Resistance θ JA θ JC Ceramic DIP o C/W o C/W Plastic DIP o C/W - PLCC o C/W - SOIC o C/W - Operating Temperature HI-HS-, o C to + o C HI-HS o C to +8 o C HI-HS-, o C to +7 o C HI-HS o C to +8 o C Junction Temperature Ceramic Package o C Plastic Package o C CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Electrical Specifications Supplies = +V, -V; V AH (Logic Level High) =.V, V AL (Logic Level Low) = +.8V, = V, Unless Otherwise Specified PARAMETER TEST CONDITIONS TEMP HI-HS-/-8 HI-HS-/-/-9/-7 MIN TYP MAX MIN TYP MAX UNITS SWITCHING CHARACTERISTICS N, Switch On Time (Note ) + o C - - ns FF, Switch Off Time (Note ) + o C - - ns, Switch Off Time (Note ) + o C ns Output Settling Time.% + o C ns Off Isolation (Note ) + o C db Crosstalk (Note ) + o C db Charge Injection (Note ) + o C pc C S(OFF), Input Switch Capacitance + o C pf C D(OFF), + o C pf Output Switch Capacitance C D(ON), + o C pf C A, Digital Input Capacitance + o C pf C DS(OFF), Drain-To-Source Capacitance + o C pf DIGITAL CHARACTERISTICS V AL, Input Low Threshold Full V V AH, Input High Threshold + o C V Full V I AL, Input Leakage Current (Low) + o C µa Full µa I AH, Input Leakage Current (High) V AH =.V + o C µa Full µa ANALOG SWITCH CHARACTERISTICS V S, Analog Signal Range Full V R ON, On Resistance (Note ) + o C - - Ω Full Ω R ON Match + o C % 9-8

4 Specifications HI-HS Electrical Specifications Supplies = +V, -V; V AH (Logic Level High) =.V, V AL (Logic Level Low) = +.8V, = V, Unless Otherwise Specified (Continued) PARAMETER TEST CONDITIONS TEMP HI-HS-/-8 HI-HS-/-/-9/-7 MIN TYP MAX MIN TYP MAX UNITS I S(OFF), Off Input Leakage Current + o C na Full na I D(OFF), Off Output Leakage Current + o C na Full na I D(ON), On Leakage Current + o C na POWER SUPPLY CHARACTERISTICS (Note 7) Full na P D, Power Dissipation + o C mw Full mw I+, Current (Pin ) + o C ma Full ma I-, Current (Pin ) + o C ma Full ma NOTES:. Absolute maximum ratings are limiting values, applied individually, beyond which the serviceability of the circuit may be impaired. Functional operability under any of these conditions is not necessarily implied.. V OUT = ±V, I OUT = ma.. R L = kω, C L = pf, V IN = +V, V A = +V. (See Switching Waveforms).. V A = V, R L = kω, C L = pf, V IN = V RMS, f = khz.. V A = V, R L = kω, V IN = V RMS, f = khz.. C L = pf, V IN = V, R IN = V, Q = C L x V O. 7. V A = V or V A = for all switches. Switching Waveforms V DIGITAL AH =.V % V AL = V % FF N 9% 9% SWITCH OUTPUT V % TOP: TTL Input (V/Div.) BOTTOM: Output (V/Div.) HORIZONTAL: ns/div. FIGURE A. FIGURE B. FIGURE. SWITCH N AND FF TIMES 9-8

5 HI-HS Typical Performance Curves 8 7 V+ = +V, = -V 8 7 T A = + o C V+ = +8V, = -8V ON RESISTANCE (Ω) + o C + o C - o C ON RESISTANCE (Ω) V+ = +V, = -V V+ = +V, = -V V+ = +V, = -V ANALOG (V) FIGURE. ON RESISTANCE vs ANALOG SIGNAL LEVEL AND TEMPERATURE ANALOG (V) FIGURE. ON RESISTANCE vs ANALOG SIGNAL LEVEL AND POWER SUPPLY VOLTAGE.. LEAKAGE CURRENT (na)... LEAKAGE CURRENT (na) TEMPERATURE ( o C). 7 TEMPERATURE ( o C) FIGURE. I S(OFF) OR I D(OFF) vs TEMPERATURE FIGURE. I D(ON) vs TEMPERATURE SUPPLY CURRENT (ma) 7 V+ = +V, = -V I+ I TEMPERATURE ( o C) 8 LEAKAGE CURRENT (pa) V+ = +V, = -V I SOFF V D = V I DOFF V S = V -8 I DON I SOFF /I DOFF ANALOG (V) 8 FIGURE. SUPPLY CURRENT vs TEMPERATURE FIGURE 7. LEAKAGE CURRENT vs ANALOG VOLTAGE Theoretically, leakage current will continue to decrease below + o C. But due to environmental conditions, leakage measurements below this temperature are not representative of actual switch performance. 9-8

6 HI-HS Typical Performance Curves (Continued) LEAKAGE CURRENT (µa) V AL = V, V AH = V, V AH = V I AH I AH I AL TEMPERATURE ( o C) LEAKAGE CURRENT (na) V+ = +V, = -V, T A = + o C I SOFF V D = V I DOFF V S = V ANALOG (V) FIGURE 8. DIGITAL LEAKAGE CURRENT vs TEMPERATURE FIGURE 9. LEAKAGE CURRENT vs ANALOG VOLTAGE SWITCHING TIME (ns) FF N - TEMPERATURE ( o C) 8 V+ = +V = -V R L = kω C L = pf SWITCHING TIME (ns) R L = K, C L = pf, T A = + o C FF N ± ± ±7 ±8 ±9 ± ± ± ± ± ± POSITIVE AND NEGATIVE SUPPLY (V) FIGURE. SWITCHING TIME vs TEMPERATURE FIGURE. SWITCHING TIME vs POSITIVE AND NEGATIVE SUPPLY VOLTAGE = -V, R L = kω C L = pf, T A = + o C V+ = +V, R L = kω C L = pf, T A = + o C SWITCHING TIME (ns) 7 SWITCHING TIME (ns) FF FF N N POSITIVE SUPPLY (V) NEGATIVE SUPPLY (V) FIGURE. SWITCHING TIME vs POSITIVE SUPPLY VOLTAGE FIGURE. SWITCHING TIME vs NEGATIVE SUPPLY VOLTAGE Theoretically, leakage current will continue to decrease below + o C. But due to environmental conditions, leakage measurements below this temperature are not representative of actual switch performance. 9-87

7 HI-HS Typical Performance Curves (Continued) SWITCHING TIME (ns) N V + = +V, = -V, R L = kω C L = pf, V AL = V, T A = + o C FF LOGIC THRESHOLD (V) DIGITAL AMPLITUDE (V) ± ± ±7 ±8 ±9 ± ± ± ± ± ± POWER SUPPLY VOLTAGE (V) FIGURE. SWITCHING TIME vs LOGIC AMPLITUDE FIGURE. SWITCHING THRESHOLD vs POSITIVE AND NEGATIVE SUPPLY VOLTAGES CHARGE INJECTION (pc) - - IN OUT V O V A Q O = C L x V O C L Q OUT - - V+ = +V, = -V C L = pf, R IN = Ω ANALOG (V) FIGURE. CHARGE INJECTION vs ANALOG CAPACITANCE (pf) C DON C DOFF OR C SOFF C DSOFF ANALOG (V) FIGURE 7. CAPACITANCE vs ANALOG V+ = +V, = -V V IN = V RMS, V A = V V+ = +V, = -V V IN = V RMS, V A = V OFF ISOLATION (db) 8 V IN IN OUT V O R L = kω R L = Ω R L = kω CROSSTALK (db) 8 V IN IN OUT V O R L = kω V O R L = kω K OFF ISOLATION = LOG V IN V O K M FREQUENCY (Hz) M K CROSSTALK = LOG V O V O K M FREQUENCY (Hz) M FIGURE 8. OFF ISOLATION vs FREQUENCY FIGURE 9. CROSSTALK vs FREQUENCY 9-88

8 HI-HS Test Circuit V+ = +V SWITCH V IN = +V SWITCH OUTPUT V O V A R L kω C L pf LOGIC HI-HS = -V V O = V IN R L R L + R ON CL INCLUDES C FIXTURE + C PROBE FIGURE. SWITCHING TEST CIRCUIT (N, FF, ) Switching Characteristics Typical delay, N, FF, settling time and switching transients in this circuit. If R L or C L is increased, there will be corresponding increases in rise and/or fall RC times.. V+ = +V OUT V O N V A R L kω C L pf LOGIC HI-HS = -V FIGURE A. LOGIC LOGIC (V) FIGURE B. FIGURE. SWITCHING CHARACTERISTICS vs VOLTAGE 9-89

9 HI-HS Switching Characteristics (Continued) A. V IN = +V B. V IN = +V C. V IN = V D. V IN = -V - - E. V IN = -V FIGURE. V O - OUTPUT SWITCHING WAVEFORMS 9-9

10 HI-HS Application Information Logic Compatibility The HI-HS is TTL compatible. Its logic inputs (Pins, 8, 9, ) are designed to react to digital inputs which exceed a fixed, internally generated TTL switching threshold. The HI-HS can also be driven with CMOS logic (V), although the switch performance with CMOS logic will be inferior to that with TTL logic (V). The logic input design of the HI-HS is largely responsible for its fast switching speed. It is a design which features a unique input stage consisting of complementary vertical PNP and NPN bipolar transistors. This design differs from that of the standard HI- product where the logic inputs are MOS transistors. Although the new logic design enhances the switching speed performance, it also increases the logic input leakage currents. Therefore, the HI-HS will exhibit larger digital input leakage currents in comparison to the standard HI- product. Charge Injection Charge injection is the charge transferred, through the internal gate-to-channel capacitances, from the digital logic input to the analog output. To optimize charge injection performance for the HI-HS, it is advisable to provide a TTL logic input with fast rise and fall times. If the power supplies are reduced from ±V, charge injection will become increasingly dependent upon the digital input frequency. Increased logic input frequency will result in larger output error due to charge injection. Power Supply Considerations The electrical characteristics specified in this data sheet are guaranteed for power supplies ±V S = ±V. Power supply voltages less than ±V will result in reduced switch performance. The following information is intended as a design aid only. POWER SUPPLY VOLTAGES SWITCH PERFORMANCE ± < ±V S ±V Minimal Variation ±V S < ±V Parametric variation becomes increasingly large (increased ON resistance, longer switching times). ±V S < ±V Not Recommended. ±V S > ±V Not Recommended. Single Supply The switch operation of the HI-HS is dependent upon an internally generated switching threshold voltage optimized for ±V power supplies. The HI-HS does not provide the necessary internal switching threshold in a single supply system. Therefore, if single supply operation is required, the HI- series of switches is recommended. The HI- series will remain operational to a minimum +V single supply. Switch performance will degrade as power supply voltage is reduced from optimum levels (±V). So it is recommended that a single supply design be thoroughly evaluated to ensure that the switch will meet the requirements of the application. For Further Information See Application Notes,,,, and

11 HI-HS Die Characteristics DIE DIMENSIONS: µm x 8µm x 8µm ± µm METALLIZATION: Type: CuAl Thickness: kå ± kå GLASSIVATION: Type: Nitride Over Silox Nitride Thickness:.kÅ ± kå Silox Thickness: kå ± kå WORST CASE CURRENT DENSITY: 9. x A/cm Metallization Mask Layout HI-HS A A OUT OUT IN IN V+ IN IN OUT OUT A A 9-9