TEMP. PKG. -IN 1 16 S/H CONTROL PART NUMBER RANGE

Transcription

1 DATASHEET 7ns, Low Distortion, Precision Sample and Hold Amplifier FN59 Rev 5. The combines the advantages of two sample/ hold architectures to create a new generation of monolithic sample/hold. High amplitude, high frequency signals can be sampled with very low distortion being introduced. The combination of exceptionally fast acquisition time and specified/characterized hold mode distortion is an industry first. Additionally, the AC performance is only minimally affected by additional hold capacitance. To achieve this level of performance, the benefits of an integrating output stage have been combined with the advantages of a buffered hold capacitor. To the user this translates to a front-end stage that has high bandwidth due to charging only a small capacitive load and an output stage with constant pedestal error which can be nulled out using the offset adjust pins. Since the performance penalty for additional hold capacitance is low, the designer can further minimize pedestal error and droop rate without sacrificing speed. Low distortion, fast acquisition, and low droop rate are the result, making the the obvious choice for high speed, high accuracy sampling systems. Ordering Information Features Fast Acquisition Time (.%) ns Fast Hold Mode Settling Time (.%) ns Low Distortion (Hold Mode) dBc (V IN = khz, f S = 45kHz, 5V P-P ) Bandwidth Minimally Affected By External C H Fully Differential Analog Inputs Built-In 35pF Hold Capacitor Applications High Bandwidth Precision Data Acquisition Systems Inertial Navigation and Guidance Systems Ultrasonics SONAR RADAR Pinout (SOIC) TOP VIEW PART NUMBER TEMP. RANGE ( o C) PACKAGE PKG. DWG. # -IN +IN 6 5 SUPPLY GND HA9P534-5 to 75 6 Ld SOIC M6.3 OFFSET ADJ. 3 4 NC Functional Diagram ADJUST OFFSET C HOLD EXTERNAL (OPTIONAL) OFFSET ADJ. NC V- SIG. GND NC EXTERNAL HOLD CAP. NC NC OUTPUT 9 V+ 3 4 C HOLD pf -IN +IN C COMP 5pF OUT S/H V+ V- SUPPLY GND SIGNAL GND FN59 Rev 5. Page of

2 Absolute Maximum Ratings Voltage Between V+ and V- Terminals V Differential Input Voltage V Digital Input Voltage V, -6V Output Current, Continuous ma Temperature Range o C to 75 o C Supply Voltage Range (Typical) V to V Thermal Information Thermal Resistance (Typical, Note ) JA ( o C/W) JC ( o C/W) SOIC Package N/A Maximum Junction Temperature (Plastic Package, Note )..5 o C Maximum Storage Temperature Range o C to 5 o C Maximum Lead Temperature (Soldering s) o C (Lead Tips Only) CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES:. Maximum power dissipation must be designed to maintain the junction temperature below 5 o C for the plastic packages.. JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications V SUPPLY = ±5.V; C H = Internal = 35pF; Digital Input: V IL = +.V (Sample), V IH = +.V (Hold). Non- Inverting Unity Gain Configuration (Output tied to -Input), R L = k, C L = 6pF, Unless Otherwise Specified PARAMETER TEST CONDITIONS TEMP. ( o C) MIN TYP MAX UNITS INPUT CHARACTERISTICS Input Voltage Range Full V Input Resistance (Note 3) M Input Capacitance pf Input Offset Voltage mv Full mv Offset Voltage Temperature Coefficient Full V/ o C Bias Current na Full na Offset Current na Full na Common Mode Range Full V CMRR V, Note db Full db TRANSFER CHARACTERISTICS Gain DC db Gain Bandwidth Product C H External = pf Full - - MHz C H External = pf Full MHz C H External = pf Full MHz TRANSIENT RESPONSE Rise Time mv Step 5-3 ns Overshoot mv Step % Slew Rate V Step V/ s DIGITAL INPUT CHARACTERISTICS Input Voltage V IH Full. - - V V IL Full - -. V Input Current V IL = V Full A V IH = 5V Full A FN59 Rev 5. Page of

3 Electrical Specifications OUTPUT CHARACTERISTICS V SUPPLY = ±5.V; C H = Internal = 35pF; Digital Input: V IL = +.V (Sample), V IH = +.V (Hold). Non- Inverting Unity Gain Configuration (Output tied to -Input), R L = k, C L = 6pF, Unless Otherwise Specified PARAMETER TEST CONDITIONS TEMP. ( o C) MIN TYP MAX UNITS Output Voltage Full V Output Current Full ma Full Power Bandwidth (Note 5) Full MHz Output Resistance Hold Mode Full Total Output Noise DC to MHz Sample Mode V RMS Hold Mode V RMS DISTORTION CHARACTERISTICS SAMPLE MODE Signal to Noise Ratio (RMS Signal to RMS Noise) V IN = khz, V P-P Full db Total Harmonic Distortion V IN = khz, 5V P-P Full dbc V IN = khz, V P-P Full dbc V IN = khz, V P-P Full dbc V IN = 5kHz, 5V P-P Full dbc Intermodulation Distortion HOLD MODE (5% Duty Cycle S/H) V IN = V P-P, f = khz, f = khz Full dbc Signal to Noise Ratio (RMS Signal to RMS Noise) f S = 45kHz V IN = khz, 5V P-P db V IN = khz, V P-P db Total Harmonic Distortion f S = 45kHz V IN = khz, 5V P-P dbc V IN = khz, V P-P dbc V IN = khz, V P-P dbc f S = 45kHz V IN = khz, 5V P-P dbc V IN = khz, V P-P dbc V IN = khz, V P-P dbc f S = f IN (Nyquist) V IN = khz, 5V P-P dbc V IN = 5kHz, 5V P-P dbc V IN = khz, 5V P-P dbc Intermodulation Distortion f S = 45kHz SAMPLE AND HOLD CHARACTERISTICS V IN = V P-P (f = khz, f = khz) dbc Acquisition Time V Step to.% ns Full ns V Step to.% ns Droop Rate C H = Internal V/ s Full V/ s Hold Step Error V IL = V, V IH = 4.V, t R = 5ns mv FN59 Rev 5. Page 3 of

4 Electrical Specifications Hold Mode Settling Time To mv Full - 3 ns Hold Mode Feedthrough V P-P, khz, Sine Full db EADT (Effective Aperture Delay Time) ns Aperture Uncertainty ns POWER SUPPLY CHARACTERISTICS V SUPPLY = ±5.V; C H = Internal = 35pF; Digital Input: V IL = +.V (Sample), V IH = +.V (Hold). Non- Inverting Unity Gain Configuration (Output tied to -Input), R L = k, C L = 6pF, Unless Otherwise Specified PARAMETER TEST CONDITIONS TEMP. ( o C) MIN TYP MAX UNITS Positive Supply Current Full ma Negative Supply Current Full ma PSRR % Delta Full 75 - db NOTES: 3. Derived from Computer Simulation only, not tested. 4. +CMRR is measured from V to +V, -CMRR is measured from V to -V. 5. Based on the calculation FPBW = Slew Rate/ V PEAK (V PEAK = V). FN59 Rev 5. Page 4 of

5 Test Circuits and Waveforms S/H INPUT -INPUT OUTPUT +INPUT 6 NC V O (C H = 35pF = INTERNAL) FIGURE. HOLD STEP ERROR AND DROOP RATE HOLD (+4.V) SAMPLE (V) HOLD (+4.V) SAMPLE (V) V O V O V O t V P NOTE: NOTES: 6. Observe the hold step voltage V P. 7. Observe the voltage droop, V O / t.. Measure the slope of the output during hold, V O / t. 9. Droop can be positive or negative - usually to one rail or the other not to GND. FIGURE. HOLD STEP ERROR FIGURE 3. DROOP RATE TEST V+ V- V P-P khz SINE WAVE INPUT V IN ANALOG MUX OR SWITCH A IN 6 -IN +IN S/H 9 6 SUPPLY GND 5 7 REF COM OUT V OUT NOTE:. Feedthrough in V db = OUT log where: V IN V OUT = V P-P, Hold Mode, V IN = V P-P TO SUPPLY COMMON TO SIGNAL GND FIGURE 4. HOLD MODE FEEDTHROUGH ATTENUATION FN59 Rev 5. Page 5 of

6 Application Information The has the uncommitted differential inputs of an op amp, allowing the Sample and Hold function to be combined with many conventional op amp circuits. See the Intersil Application Note AN57 for a collection of circuit ideas. Layout A printed circuit board with ground plane is recommended for best performance. Bypass capacitors (. F to. F, ceramic) should be provided from each power supply terminal to the Supply Ground terminal on pin 5. The ideal ground connections are pin 7 (SIG. GND) directly to the system Signal Ground, and pin 5 (Supply Ground) directly to the system Supply Common. Hold Capacitor The includes a 35pF MOS hold capacitor, sufficient for most high speed applications (the Electrical Specifications section is based on this internal capacitor). Additional capacitance may be added between pins and. This external hold capacitance will reduce droop rate at the expense of acquisition time, and provide other trade-offs as shown in the Performance Curves. The hold capacitor C H should have high insulation resistance and low dielectric absorption, to minimize droop errors. Teflon, polystyrene and polypropylene dielectric capacitor types offer good performance over the specified operating temperature range. The hold capacitor terminal (pin ) remains at virtual ground potential. Any PC connection to this terminal should be kept short and guarded by the ground plane, since nearby signal lines or power supply voltages will introduce errors due to drift current. Typical Application Figure 5 shows the connected as a unity gain noninverting amplifier - its most widely used configuration. As an input device for a fast successive - approximation A/D converter, it offers very high throughput rate for a monolithic IC sample/hold amplifier. Also, the s hold step error is adjustable to zero using the Offset Adjust potentiometer, to deliver a -bit accurate output from the converter. The output circuit does not include short circuit protection, and consequently its output impedance remains low at high frequencies. Thus, the step changes in load current which occur during an A/D conversion are absorbed at the S/H output with minimum voltage error. A momentary short circuit to ground is permissible, but the output is not designed to tolerate a short of indefinite duration. -5V +5V OFFSET ADJUST 5mV 5k C H HI-774 pf V IN 5pF 3 INPUT S H CONVERT 5 9 R/C ANALOG COMMON DIGITAL OUTPUT SYSTEM POWER GROUND SYSTEM SIGNAL GROUND NOTE: Pin Numbers Refer to DIP Package Only. FIGURE 5. TYPICAL CONNECTIONS; NONINVERTING UNITY GAIN MODE FN59 Rev 5. Page 6 of

7 Typical Performance Curves T A = 5 o C, V S = 5V, Unless Otherwise Specified S/H 4V V S/H 4V V V pf 47pF V OUT V V OUT pf pf FIGURE 6. T ACQ POS TO + STEP FIGURE 7. T ACQ vs ADDITIONAL C H DROOP RATE ( V/ s) o C o C 5 o C EXTERNAL HOLD CAPACITANCE (pf) ACQUISITION TIME TO mv (ns) EXTERNAL HOLD CAPACITANCE (pf) FIGURE. DROOP RATE vs HOLD CAPACITANCE FIGURE 9. ACQUISITION TIME (.%) vs HOLD CAPACITANCE HOLD STEP ERROR (mv) C H = INTERNAL TEMPERATURE = 5 o C 5 5 T RISE (ns) FIGURE. HOLD STEP ERROR vs T RISE V IH = 3V V IH = 4V HOLD STEP ERROR (mv) V IH = 4V C H = 47pF TEMPERATURE ( o C) FIGURE. HOLD STEP ERROR vs TEMPERATURE FN59 Rev 5. Page 7 of

8 Typical Performance Curves T A = 5 o C, V S = 5V, Unless Otherwise Specified (Continued) HOLD STEP ERROR (mv) T RISE = 5ns T A = 5 o C V IH = 4V 4 6 EXTERNAL HOLD CAPACITANCE (pf) FIGURE. HOLD STEP ERROR vs HOLD CAPACITANCE HOLD STEP ERROR (mv) V IH = 4V, C H = INTERNAL t R = 5ns, ns, ns 5ns ns ns TEMPERATURE ( o C) FIGURE 3. HOLD STEP ERROR vs TEMPERATURE MAGNITUDE (db) 4 A V = +, 5V AND V SUPPLIES (NOTE) PHASE MAGNITUDE PHASE ANGLE (DEGREES) MAGNITUDE (db) 4 C H = pf C H = 47pF C H = pf C H = pf C H = 47pF C H = pf MAGNITUDE PHASE A V = PHASE ANGLE (DEGREES) K K K M M NOTE: 5V and V supplies trace the same line within the width of the line, therefore only one line is shown. FIGURE 4. CLOSED LOOP PHASE/GAIN K K K M M FIGURE 5. CLOSED LOOP PHASE/GAIN - -4 f SAMPLE 45kHz V OUT = 5V P-P HA-53 SAMPLE AND HOLD MODES - -4 HA-53 SAMPLE AND HOLD MODES THD (dbc) -6 HOLD MODE THD (dbc) -6 HOLD MODE - - SAMPLE MODE K K 3K 4K 5K FREQUENCY (Hz) - - SAMPLE MODE 5 V OUTP-P at khz, f 45kHz FIGURE 6. THD vs FREQUENCY FIGURE 7. THD vs V OUT FN59 Rev 5. Page of

9 Die Characteristics DIE DIMENSIONS: 4mils x 39mils x 9mils METALLIZATION: Type: Al, % Cu Thickness: 6kÅ kå PASSIVATION: Type: Nitride (Si 3 N 4 ) over Silox (SiO, 5% Phos) Silox Thickness: kå.kå Nitride Thickness: 3.5kÅ.5kÅ SUBSTRATE POTENTIAL (POWERED UP): V- TRANSISTOR COUNT: 96 Metallization Mask Layout () EXTERNAL HOLD CAP SUPPLY (5) GND S/H (6) -IN () (9) +V SUPPLY () OUTPUT () OUTPUT +IN () (7) SIG GND OFFSET ADJ (3) OFFSET ADJ (4) -V SUPPLY (6) FN59 Rev 5. Page 9 of

10 Small Outline Plastic Packages (SOIC) N INDEX AREA 3 e D B.5(.) M C A M E -B- -A- -C- SEATING PLANE A B S H A.(.4) NOTES:. Symbols are defined in the MO Series Symbol List in Section. of Publication Number 95.. Dimensioning and tolerancing per ANSI Y4.5M Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed.5mm (.6 inch) per side. 4. Dimension E does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed.5mm (. inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. L is the length of terminal for soldering to a substrate. 7. N is the number of terminal positions.. Terminal numbers are shown for reference only. 9. The lead width B, as measured.36mm (.4 inch) or greater above the seating plane, shall not exceed a maximum value of.6mm (.4 inch). Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. µ.5(.) M B L M h x 45 o C M6.3 (JEDEC MS-3-AA ISSUE C) 6 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A B C D E e.5 BSC.7 BSC - H h L N o o o o - Rev. /93 Copyright Intersil Americas LLC 3. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see Intersil products are manufactured, assembled and tested utilizing ISO9 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see FN59 Rev 5. Page of