DATASHEET HA Features. Applications. Ordering Information. Pinout. 400MHz, Fast Settling Operational Amplifier. FN2897 Rev.5.

Transcription

1 DATASHEET MHz, Fast Settling Operational Amplifier The Intersil is a wideband, very high slew rate, monolithic operational amplifier featuring superior speed and bandwidth characteristics. Bipolar construction coupled with dielectric isolation allows this truly differential device to deliver outstanding performance in circuits where closed loop gain is or greater. Additionally, the has a drive capability of V into a 1k load. Other desirable characteristics include low input voltage noise, low offset voltage, and fast settling time. A V/ s slew rate ensures high performance in video and pulse amplification circuits, while the MHz gainbandwidth product is ideally suited for wideband signal amplification. A settling time of ns also makes the an excellent selection for high speed Data Acquisition Systems. Refer to Application Note AN51 and Application Note AN556 for more information on High Speed Op Amp applications. For a lower power version of this product, please see the HA-25 datasheet. Features FN297 Rev.5. Very High Slew Rate V/ s Fast Settling Time ns Wide Gain Bandwidth (A V ) MHz Power Bandwidth MHz Low Offset Voltage mv Input Voltage Noise nV/ Hz Output Voltage Swing V Monolithic Bipolar Construction Applications Pulse and Video Amplifiers Wideband Amplifiers High Speed Sample-Hold Circuits Fast, Precise D/A Converters Ordering Information Pinout (CERDIP) TOP VIEW PART NUMBER TEMP. RANGE ( o C) PACKAGE PKG. DWG. # HA to 75 1 Ld CERDIP F IN +IN OUTPUT FN297 Rev.5. Page 1 of

2 Absolute Maximum Ratings Voltage Between and Terminals V Differential Input Voltage V Output Current mA RMS Continuous, 5mA PEAK Operating Conditions Temperature Range o C to 75 o C Thermal Information Thermal Resistance (Typical, Note 2) JA ( o C/W) JC ( o C/W) CERDIP Package Maximum Internal Power Dissipation (Note 1) Maximum Junction Temperature (Ceramic Package) o C Maximum Storage Temperature Range o C to 15 o C Maximum Lead Temperature (Soldering s) o C CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. 1. Maximum power dissipation with load conditions must be designed to maintain the maximum junction temperature below 175 o C for the ceramic package, and below 15 o C for the plastic package. By using Application Note AN556 on Safe Operating Area Equations, along with the thermal resistances, proper load conditions can be determined. Heat sinking is recommended above 75 o C. 2. JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications V SUPPLY = 15V, R L = 1k, C L < pf, Unless Otherwise Specified PARAMETER TEMP ( o C) MIN TYP MAX UNITS INPUT CHARACTERISTICS Offset Voltage mv Full - 13 mv Average Offset Voltage Drift Full - - V/ o C Bias Current 25-5 A Full A Offset Current A Full - - A Input Resistance k Input Capacitance pf Common Mode Range Full - - V Input Noise Current (f = 1kHz, R SOURCE = ) pa/ Hz Input Noise Voltage (f = 1kHz, R SOURCE = ) nv/ Hz TRANSFER CHARACTERISTICS Large Signal Voltage Gain (Note 3) kv/v Full kv/v Common-Mode Rejection Ratio (Note ) Full db Minimum Stable Gain V/V Gain Bandwidth Product (Notes 5, 6) MHz OUTPUT CHARACTERISTICS Output Voltage Swing (Notes 3, ) Full - - V Output Current (Note 3) 25 - ma Output Resistance Full Power Bandwidth (Notes 3, 7) MHz TRANSIENT RESPONSE (Note ) Rise Time ns Overshoot % Slew Rate V/ s Settling Time: V Step to.1% ns FN297 Rev.5. Page 2 of

3 Electrical Specifications V SUPPLY = 15V, R L = 1k, C L < pf, Unless Otherwise Specified (Continued) PARAMETER TEMP ( o C) MIN TYP MAX UNITS POWER REQUIREMENTS Supply Current Full - 25 ma Power Supply Rejection Ratio (Note 9) Full db 3. R L = 1k, V O = V.. V CM = V. 5. V O = 9mV. 6. A V =. Slew Rate 7. Full power bandwidth guaranteed based on slew rate measurement using: FPBW = V. Refer to Test Circuits section of the data sheet. PEAK 9. V SUPPLY = +5V, -15V and +15V, -5V.. Guaranteed range for output voltage is V. Functional operation outside of this range is not guaranteed. Test Circuits and Waveforms V IN V OUT 11. A V = +.. C L pf. FIGURE 1. LARGE AND SMALL SIGNAL RESPONSE TEST CIRCUIT A B Vertical Scale: A =.5V/Div., B = 5.V/Div. Horizontal Scale: 5ns/Div. LARGE SIGNAL RESPONSE Vertical Scale: Input = mv/div.; Output = 5mV/Div. Horizontal Scale: ns/div. SMALL SIGNAL RESPONSE INPUT 5 SETTLE POINT F 1 F.1 F 1 F 2k 5k OUTPUT PROBE MONITOR 13. A V = Load Capacitance should be less than pf. Turn on time delay typically ns. 15. It is recommended that resistors be carbon composition and the feedback and summing network ratios be matched to.1%. 16. SETTLE POINT (Summing Node) capacitance should be less than pf. For optimum settling time results, it is recommended that the test circuit be constructed directly onto the device pins. A Tektronix 56 Sampling Oscilloscope with S-3A sampling heads is recommended as a settle point monitor. FIGURE 2. SETTLING TIME TEST CIRCUIT FN297 Rev.5. Page 3 of

4 Schematic Diagram R 23 R 1 R 2 Q P1 Q P2 R 3 R Q P22 Q P19 R 13 R 2 Q P17 R5 Q P5 Q P6 Q P25 R 22 Q N2 C 1 C 2 R C2 Q N1 Q N7 Q N9 + INPUT R 6 R 7 Q P R 1 OUTPUT Q P23 QN21 R R 9 Q N R 19 - INPUT Q P3 Q P Q P11 R 21 Z 1 Q N25 Q N R 25 R Q N Q N15 R 16 Q N13 D Z1 Q N1 Q N16 D Z2 R 11 R Q N29 R 1 R 15 R 17 Typical Applications - + 2K 2K OFFSET ADJUST C 1 (NOTE 1) 1K 1K R 5 (NOTE 19) - + K C F (NOTE 17).1 F R 3 K R 1 K R 2 K SIGNAL OUT NOTE: With one and two low capacitance switching diodes, signals exceeding MHz can be separated. This circuit is most useful for full wave rectification, AM detectors or sync generation. FIGURE 3. WIDEBAND SIGNAL SPLITTER Refer to Application Note AN51 For Further Application Information. 17. Used for experimental purposes. C F 3pF. 1. C 1 is optional (.1 F.1 F ceramic). 19. R 5 is optional and can be utilized to reduce input signal amplitude and/or balance input conditions. R 5 = 5 to 1k. FIGURE. BOOTSTRAPPING FOR MORE OUTPUT CURRENT AND VOLTAGE SWING FN297 Rev.5. Page of R K

5 Typical Performance Curves CLOSED LOOP GAIN (db) K K K 1M M M FREQUEY (Hz) FIGURE 5. CLOSED LOOP FREQUEY RESPONSE OUTPUT VOLTAGE SWING (V P-P ) V S = 15V V S = V V S = 5V 1K K K 1M M M FREQUEY (Hz) FIGURE 6. OUTPUT VOLTAGE SWING vs FREQUEY OUTPUT VOLTAGE SWING (V P-P ) K 1.2K NORMALIZED PARAMETERS REFERRED TO VALUES AT 25 o C BANDWIDTH 1..9 SLEW RATE RESISTAE ( ) TEMPERATURE ( o C) FIGURE 7. OUTPUT VOLTAGE SWING vs LOAD RESISTAE FIGURE. NORMALIZED AC PARAMETERS vs TEMPERATURE OUTPUT VOLTAGE STEP (V) mv mv 16 SETTLING TIME (ns) 1mV 1mV SUPPLY CURRENT (ma) TEMPERATURE ( o C) V S = 15V V S = 5V FIGURE 9. SETTLING TIME FOR VARIOUS OUTPUT STEP VOLTAGES FIGURE. POWER SUPPLY CURRENT vs TEMPERATURE FN297 Rev.5. Page 5 of

6 Typical Performance Curves (Continued) INPUT BIAS CURRENT ( A) OFFSET VOLTAGE BIAS CURRENT V IO OFFSET VOLTAGE (mv) NOISE VOLTAGE (nv/ Hz) R SOURCE =, V S = 15 CURRENT NOISE VOLTAGE NOISE 5 3 NOISE CURRENT (pa/ Hz) TEMPERATURE ( o C) FIGURE 11. INPUT OFFSET VOLTAGE AND BIAS CURRENT vs TEMPERATURE 1K K K FREQUEY (Hz) FIGURE. INPUT NOISE VOLTAGE AND NOISE CURRENT vs FREQUEY + V +3 V + V + V V - V - V -3 V CMRR (db) 6 V S = 15, R L = 1K - V Vertical Scale: mv/div. Horizontal Scale: 5ms/Div. FIGURE 13. BROADBAND NOISE (.1Hz TO 1MHz) 1K K K 1M M FREQUEY (Hz) FIGURE 1. COMMON MODE REJECTION RATIO vs FREQUEY PSRR (db) 6 POSITIVE SUPPLY NEGATIVE SUPPLY 1K K K 1M M FREQUEY (Hz) FIGURE 15. POWER SUPPLY REJECTION RATIO vs FREQUEY OPEN LOOP GAIN (db) 5 GAIN 6 PHASE K K K 1M M M FREQUEY (Hz) FIGURE 16. OPEN LOOP GAIN/PHASE vs FREQUEY PHASE (DEGREES) FN297 Rev.5. Page 6 of

7 Die Characteristics DIE DIMENSIONS: 62 mils x 76 mils x 19 mils 1575 mx 193 m x 3 m METALLIZATION: Type: Al, 1% Cu Thickness: 16kÅ 2kÅ PASSIVATION: SUBSTRATE POTENTIAL (Powered Up): TRANSISTOR COUNT: 3 PROCESS: Bipolar Dielectric Isolation Type: Nitride (Si 3 N ) over Silox (SiO 2, 5% Phos.) Silox Thickness: kå 2kÅ Nitride Thickness: 3.5kÅ 1.5kÅ Metallization Mask Layout OUTPUT -IN +IN - IN + IN FN297 Rev.5. Page 7 of

8 Ceramic Dual-In-Line Frit Seal Packages (CERDIP) BASE PLANE SEATING PLANE S1 b2 ccc M bbb S b C A - B Q -C- A -B- C A - B S D A A e D S -D- -A- 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer s identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness.. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners.. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y1.5M Controlling dimension: IH. E L M c1 ea/2 S D S aaa M C A - B LEAD FINISH BASE METAL b1 M (b) SECTION A-A S ea c D S (c) F1.3 MIL-STD-135 GDIP1-T1 (D-1, CONFIGURATION A) 1 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE IHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A b b b b c c D E e. BSC 2.5 BSC - ea.3 BSC 7.62 BSC - ea/2.15 BSC 3.1 BSC - L Q S o 5 o 9 o 5 o - aaa bbb ccc M , 3 N 1 1 Rev. /9 Copyright Intersil Americas LLC All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see Intersil products are manufactured, assembled and tested utilizing ISO91 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see FN297 Rev.5. Page of