DATASHEET CA3054. Features. Applications. Ordering Information. Pinout. Dual Independent Differential Amp for Low Power Applications from DC to 120MHz

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1 DATASHEET CA5 Dual Independent Differential Amp for Low Power Applications from DC to MHz FN88 Rev.. Jan, 7 The CA5 consists of two independent differential amplifiers with associated constant current transistors on a common monolithic substrate. The six NPN transistors which comprise the amplifiers are general purpose devices which exhibit low /f noise and a value of f T in excess of MHz. These feature make the CA5 useful from DC to MHz. Bias and load resistors have been omitted to provide maximum application flexibility. The monolithic construction of the CA5 provides close electrical and thermal matching of the amplifiers. This feature makes these devices particularly useful in dual channel applications where matched performance of the two channels is required. Ordering Information PART NUMBER (BRAND) CA5M9 (5) CA5MZ (CA5MZ) CA5MZ9 (CA5MZ) TEMP. RANGE ( C) PACKAGE to 85 Ld SOIC Tape and Reel to 85 Ld SOIC (Pb-free) to 85 Ld SOIC Tape and Reel (Pb-free) PKG. DWG. # M.5 M.5 M.5 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and % matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-. Features Two Differential Amplifiers on a Common Substrate Independently Accessible Inputs and Outputs Maximum Input Offset Voltage mV Temperature Range C to 85 C Pb-Free Plus Anneal Available (RoHS Compliant) Applications Dual Sense Amplifiers Dual Schmitt Triggers Multifunction Combinations - RF/Mixer/Oscillator; Converter/IF IF Amplifiers (Differential and/or Cascode) Product Detectors Doubly Balanced Modulators and Demodulators Balanced Quadrature Detectors Cascade Limiters Synchronous Detectors Pairs of Balanced Mixers Synthesizer Mixers Balanced (Push-Pull) Cascode Amplifiers Pinout CA5 (SOIC) TOP VIEW Q Q Q SUBSTRATE 5 Q NC 7 Q 5 Q 9 8 FN88 Rev.. Page of 8 Jan, 7

2 CA5 Absolute Maximum Ratings Thermal Information Collector-to-Emitter Voltage, V CEO V Collector-to-Base Voltage, V CBO V Collector-to-Substrate Voltage, V CIO (Note ) V Emitter-to-Base Voltage, V EBO V Collector Current, I C mA Operating Conditions Temperature Range C to 85 C Thermal Resistance (Typical, Note ) JA ( C/W) SOIC Package Maximum Junction Temperature (Die) C Maximum Junction Temperature (Plastic Package) C Maximum Storage Temperature Range C to 5 C Maximum Lead Temperature (Soldering s) C (Lead Tips Only) Maximum Power Dissipation (Any One Transistor) mw CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES:. The collector of each transistor of the CA5 is isolated from the substrate by an integral diode. The substrate must be connected to a voltage which is more negative than any collector voltage in order to maintain isolation between transistors and provide for normal transistor action. The substrate should be maintained at signal (AC) ground by means of a suitable grounding capacitor, to avoid undesired coupling between transistors.. JA is measured with the component mounted on an evaluation PC board in free air. Maximum Voltage Ratings The following chart gives the range of voltages which can be applied to the terminals listed vertically with respect to the terminals listed horizontally. For example, the voltage range of the vertical Terminal with respect to Terminal is +5V to -5V. Current Ratings Maximum (NOTE ) TERM NO (NOTE ) TERM NO. I IN ma I OUT ma, - Note +5, -5 Note +5, -5 Note Note Note Note Note Note Note 5. Note Note Note +, Note Note Note Note Note Note +, 5. +, Note +, Note Note Note Note Note Note +, 5. Note +5, -5 Note Note Note Note Note Note Note 5. +, -5 Note Note Note Note Note Note Note 5. Note Note Note Note Note Note Note. 5, - Note +5, -5 Note +5, -5 Note 5. 7 Note Note Note Note +, , Note Note +, Note +5, -5 Note , -5 Note 5. Note. 5 5 Ref. Substrate NOTES:. Voltages are not normally applied between these terminals. Voltages appearing between these terminals will be safe if the specified limits between all other terminals are not exceeded.. Terminal No. of CA5 is not used. Electrical Specifications PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT DC CHARACTERISTICS For Each Differential Amplifier Input Offset Voltage (Figure 8) V IO, I E(Q) = I E(Q) = ma mv Input Offset Current (Figure 9) I IO, I E(Q) = I E(Q) = ma -. A Input Bias Current (Figure 5) I I, I E(Q) = I E(Q) = ma - A Quiescent Operating Current Ratio (Figure 5) I C(Q) I or C(Q) I C(Q5) I C(Q), I E(Q) = I E(Q) = ma -.98 to. - - Temperature Coefficient Magnitude of Input Offset Voltage (Figure 7) V IO T, I E(Q) = I E(Q) = ma -. - V/ C FN88 Rev.. Page of 8 Jan, 7

3 CA5 Electrical Specifications (Continued) PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT FOR EACH TRANSISTOR DC Forward Base-to-Emitter Voltage V BE I C = 5 A -..7 V (Figure 8) I C = ma V I C = ma V I C = ma V Temperature Coefficient of Base-to-Emitter Voltage (Figure ) V BE T, I C = ma V/ C Collector Cutoff Current (Figure ) I CBO V CB = V, I E = -. na Collector-to-Emitter Breakdown Voltage V (BR)CEO I C = ma, I B = 5 - V Collector-to-Base Breakdown Voltage V (BR)CBO I C = A, I E = - V Collector-to-Substrate Breakdown Voltage V (BR)CIO I C = A, I CI = - V Emitter-to-Base Breakdown Voltage V (BR)EBO I E = A, I C = V DYNAMIC CHARACTERISTICS Common Mode Rejection Ratio for each Amplifier (Figures, ) CMRR V CC = V,, V X = -.V, f = khz - - db AGC Range, One Stage (Figures, ) AGC V CC = V,, V X = -.V, f = khz db Voltage Gain, Single Stage Double-Ended Output (Figures, ) A V CC = V,, V X = -.V, f = khz - - db AGC Range, Two Stage (Figures, ) AGC V CC = V,, V X = -.V, f = khz db Voltage Gain, Two Stage Double-Ended Output (Figures, ) A V CC = V,, V X = -.V, f = khz - - db Low Frequency, Small Signal Equivalent Circuit Characteristics (For Single Transistor) Forward Current Transfer Ratio (Figure ) h FE f = khz, V CE = V, I C = ma Short Circuit Input Impedance (Figure ) h IE f = khz, V CE = V, I C = ma k Open Circuit Output Impedance (Figure ) Open Circuit Reverse Voltage Transfer Ratio (Figure ) h OE f = khz, V CE = V, I C = ma S h RE f = khz, V CE = V, I C = ma -.8 x /f Noise Figure for Single Transistor NF f = khz, V CE = V db Gain Bandwidth Product for Single Transistor (Figure ) f T V CE = V, I C = ma MHz Admittance Characteristics; Differential Circuit Configuration (For Each Amplifier) Forward Transfer Admittance (Figure 5) Y, f = MHz Each Collector I C.5mA j Input Admittance (Figure ) Y, f = MHz Each Collector I C.5mA Output Admittance (Figure 7) Y, f = MHz Each Collector I C.5mA Reverse Transfer Admittance (Figure 8) Y, f = MHz Each Collector I C.5mA -. + j j j FN88 Rev.. Page of 8 Jan, 7

4 CA5 Electrical Specifications (Continued) PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Admittance Characteristics; Cascode Circuit Configuration (For Each Amplifier) Forward Transfer Admittance (Figure 9) Y, f = MHz Total Stage I C.5 ma j Input Admittance (Figure ) Y, f = MHz Total Stage I C.5 ma j Output Admittance (Figure ) Y, f = MHz Total Stage I C.5 ma Reverse Transfer Admittance (Figure ) Y, f = MHz Total Stage I C.5 ma - + j j.5 - S Noise Figure NF f = MHz db Test Circuits V X V CC = +V V X V CC = +V. F. F V IN =.V RMS SIGNAL SOURCE F 9.5k ICUT 7 8 V OUT V IN = mv RMS SIGNAL SOURCE F 9 ICUT 7 8 V OUT.5k.5k. F V CC = +V. F V CC = +V FIGURE. COMMON MODE REJECTION RATIO TEST SETUP FIGURE. SINGLE STAGE VOLTAGE GAIN TEST SETUP F V CC = +V. F V IN = mv RMS SIGNAL SOURCE F V X 9 7 ICUT 8.5k V OUT.5k. F F V CC = +V FIGURE. TWO STAGE VOLTAGE GAIN TEST SETUP FN88 Rev.. Page of 8 Jan, 7

5 CA5 Typical Performance Curves COLLECTOR CUTOFF CURRENT (na) I E = V CB = 5V V CB = V V CB = 5V TEMPERATURE ( C) (NOTE) NOTE: For CA5 use data from C to 85 C only. FIGURE. COLLECTOR-TO-BASE CUTOFF CURRENT vs TEMPERATURE FOR EACH TRANSISTOR INPUT BIAS CURRENT ( A).... COLLECTOR CURRENT (ma) FIGURE 5. INPUT BIAS CURRENT vs COLLECTOR CURRENT FOR EACH TRANSISTOR BASE-TO-EMITTER VOLTAGE (V) I E = ma I E = ma I E =.5mA OFFSET VOLTAGE (mv) I E = ma I E = ma I E =.ma TEMPERATURE ( C) (NOTE) NOTE: For CA5 use data from C to 85 C only. FIGURE. BASE-TO-EMITTER VOLTAGE FOR EACH TRANSISTOR vs TEMPERATURE TEMPERATURE ( C) (NOTE) NOTE: For CA5 use data from C to 85 C only. FIGURE 7. OFFSET VOLTAGE vs TEMPERATURE FOR DIFFERENTIAL PAIRS BASE-TO-EMITTER VOLTAGE (V) V BE V IO = V BE - V BE.... EMITTER CURRENT (ma) FIGURE 8. STATIC BASE-TO-EMITTER VOLTAGE AND INPUT OFFSET VOLTAGE FOR DIFFERENTIAL PAIRS vs EMITTER CURRENT INPUT OFFSET VOLTAGE Q AND Q (mv) INPUT OFFSET CURRENT ( A) COLLECTOR CURRENT (ma) FIGURE 9. INPUT OFFSET CURRENT FOR MATCHED DIFFERENTIAL PAIRS vs COLLECTOR CURRENT FN88 Rev.. Page 5 of 8 Jan, 7

6 CA5 Typical Performance Curves (Continued) COMMON MODE REJECTION RATIO (db) 9 8 V CC = V f = khz BIAS VOLTAGE ON TERMINAL (V) FIGURE. COMMON MODE REJECTION RATIO CHARACTERISTIC SINGLE STAGE VOLTAGE GAIN (db) V CC = V f = khz SIGNAL INPUT = mv RMS BIAS VOLTAGE ON TERMINAL (V) FIGURE. SINGLE STAGE VOLTAGE GAIN CHARACTERISTIC TWO STAGE VOLTAGE GAIN (db) V CC = V f = khz SIGNAL INPUT = mv RMS NORMALIZED h PARAMETERS. f = khz h IE h RE h FE = h IE =.5k h RE =.88 x - h OE = 5. S AT ma h OE h FE h RE BIAS VOLTAGE ON TERMINALS AND (V) -7 h IE.... COLLECTOR CURRENT (ma) FIGURE. TWO STAGE VOLTAGE GAIN CHARACTERISTIC FIGURE. FORWARD CURRENT TRANSFER RATIO (h FE ), SHORT CIRCUIT INPUT IMPEDANCE (h IE ), OPEN CIRCUIT OUTPUT IMPEDANCE (h OE ), AND OPEN CIRCUIT REVERSE VOLTAGE TRANSFER RATIO (h RE ) vs COLLECTOR CURRENT FOR EACH TRANSISTOR GAIN BANDWIDTH PRODUCT (MHz) COLLECTOR CURRENT (ma) FIGURE. GAIN BANDWIDTH PRODUCT (f T ) vs COLLECTOR CURRENT FORWARD TRANSFER SUSCEPTANCE OR CONDUCTANCE (ms) - DIFFERENTIAL CONFIGURATION I C (EACH TRANSISTOR).5mA b g -.. FIGURE 5. FORWARD TRANSFER ADMITTANCE (Y ) vs FREQUENCY FN88 Rev.. Page of 8 Jan, 7

7 CA5 Typical Performance Curves (Continued) INPUT SUSCEPTANCE OR CONDUCTANCE (ms) 5 DIFFERENTIAL CONFIGURATION I C (EACH TRANSISTOR).5mA b g OUTPUT CONDUCTANCE (ms) DIFFERENTIAL CONFIGURATION I C (EACH TRANSISTOR).5mA b g OUTPUT SUSCEPTANCE (ms).. FIGURE. INPUT ADMITTANCE (Y ) FIGURE 7. OUTPUT ADMITTANCE (Y ) vs FREQUENCY REVERSE TRANSFER CONDUCTANCE (ms)... DIFFERENTIAL CONFIGURATION 8 I C (EACH TRANSISTOR).5mA -g b g.... REVERSE TRANSFER SUSCEPTANCE ( S) FORWARD TRANSFER CONDUCTANCE OR SUSCEPTANCE (ms) - CASCODE CONFIGURATION I C (STAGE).5mA g b -. FIGURE 8. REVERSE TRANSFER ADMITTANCE (Y ) vs FREQUENCY FIGURE 9. FORWARD TRANSFER ADMITTANCE (Y ) vs FREQUENCY INPUT CONDUCTANCE OR SUSCEPTANCE (ms) 5 CASCODE CONFIGURATION I C (STAGE).5mA g b. OUTPUT CONDUCTANCE (ms x - ) g CASCODE CONFIGURATION I C (STAGE).5mA b. OUTPUT SUSCEPTANCE (ms) FIGURE. INPUT ADMITTANCE (Y ) vs FREQUENCY FIGURE. OUTPUT ADMITTANCE (Y ) vs FREQUENCY FN88 Rev.. Page 7 of 8 Jan, 7

8 CA5 Typical Performance Curves (Continued) REVERSE TRANSFER CONDUCTANCE OR SUSCEPTANCE ( S).. CASCODE CONFIGURATION I C (STAGE).5mA.. FIGURE. REVERSE TRANSFER ADMITTANCE (Y ) vs FREQUENCY g -b Copyright Intersil Americas LLC -5. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see Intersil products are manufactured, assembled and tested utilizing ISO9 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see FN88 Rev.. Page 8 of 8 Jan, 7