DATASHEET HI-201HS. Features. Applications. Ordering Information. Pinout (Switches Shown For Logic 1 Input) High Speed, Quad SPST, CMOS Analog Switch

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1 DATASHEET HI-21HS High Speed, Quad SPST, CMOS Analog Switch The HI-21HS is a monolithic CMOS Analog Switch featuring very fast switching speeds and low ON resistance. The integrated circuit consists of four independently selectable SPST switches and is pin compatible with the industry standard HI-21 switch. Fabricated using silicon-gate technology and the Intersil Dielectric Isolation process, this TTL compatible device offers improved performance over previously available CMOS analog switches. Featuring maximum switching times of 5ns, low ON resistance of 5 maximum, and a wide analog signal range, the HI-21HS is designed for any application where improved switching performance, particularly switching speed, is required. (A more detailed discussion on the design and application of the HI-21HS can be found in Application Note AN543.) Ordering Information PART NUMBER TEMP. RANGE ( o C) PACKAGE PKG. NO. HI1-21HS-2-55 to Ld CERDIP F16.3 HI1-21HS-4-25 to Ld CERDIP F16.3 HI1-21HS-5 to Ld CERDIP F16.3 HI3-21HS-5 to Ld PDIP E16.3 HI9P21HS-5 to Ld SOIC M16.3 HI9P21HS-9-4 to Ld SOIC M16.3 Features FN3123 Rev 4. September 24 Fast Switching Times - t ON ns - t OFF ns Low ON Resistance Pin Compatible with Standard HI-21 Wide Analog Voltage Range ( 15V Supplies) V Low Charge Injection ( 15V Supplies) pC TTL Compatible Symmetrical Switching Analog Current Range mA Applications High Speed Multiplexing High Frequency Analog Switching Sample and Hold Circuits Digital Filters Operational Amplifier Gain Switching Networks Integrator Reset Circuits Pinout (Switches Shown For Logic 1 Input) HI-21HS (CERDIP, PDIP, SOIC) TOP VIEW A A 2 OUT OUT2 IN IN2 V V+ GND 5 12 NC IN IN3 OUT4 7 1 OUT3 A A 3 FN3123 Rev 4. Page 1 of 12 September 24

2 HI-21HS Functional Diagram V+ LOGIC TRUTH TABLE SWITCH TTL LOGIC INPUT LEVEL SHIFTER AND DRIVER GATE SWITCH CELL SOURCE DRAIN GATE INPUT 1 ON OFF OUTPUT V- Schematic Diagrams TTL/CMOS REFERENCE CIRCUIT SWITCH CELL V+ P41 MP42 MP43 MP44 MP45 V+ Q QN41 QN42 D41 5V R42 R41 QN43 C48 QP44 QN44 QN45 V R1 ANALOG IN MP32 MN33 MN31 MP33 MN32 ANALOG OUT C49 D42 5.6V MP31 QP42 QP41 Q V- MN42 MN44 MN45 V- FN3123 Rev 4. Page 2 of 12 September 24

3 HI-21HS Schematic Diagrams (Continued) DIGITAL INPUT BUFFER AND LEVEL SHIFTER M N46 M P51 M P52 M P4 M P8 Q N6 Q N8 I Q I X3 I X4 I X1 Q N7 VR1 IX2 Q N9 M P3 M P7 M P5 M P6 M P9 M P1 M P11 M P12 Q N1 C 1 R 1 I Q M N11 V EE M N12 Q VA Q P1 Q P4 Q N4 Q N5 Q N2 V R1 Q P5 R 3 R 2 C 2 V CC M P13 M P14 Q I X1 IX2 I X3 C FF Q P7 Q P6 Q P9 M N3 Q P2 M N5 M N4 M N6 M N7 M N9 M N8 M N1 M N13 M N14 Q P8 M N51 M N52 REPEAT FOR EACH LEVEL SHIFTER FN3123 Rev 4. Page 3 of 12 September 24

4 HI-21HS Absolute Maximum Ratings Supply Voltage (V+ to V-) V Digital Input Voltage (V+) +4V to (V-) -4V Analog Input Voltage (One Switch) (V+) +2.V to (V-) -2.V Peak Current, S or D (Pulse 1ms, 1% Duty Cycle Max).... 5mA Continuous Current Any Terminal (Except S or D) mA Operating Conditions Temperature Ranges HI-21HS o C to 125 o C HI-21HS o C to 85 o C HI-21HS o C to 75 o C HI-21HS o C to 85 o C Thermal Information Thermal Resistance (Typical, Note 1) JA ( o C/W) JC ( o C/W) CERDIP Package PDIP Package N/A SOIC Package N/A Maximum Junction Temperature Ceramic Package o C Plastic Package o C Maximum Storage Temperature o C to 15 o C Maximum Lead Temperature (Soldering 1s) o C (SOIC - Lead Tips Only) CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications Supplies = +15V, -15V; V AH (Logic Level High) = 2.4V, V AL (Logic Level Low) = +.8V, GND = V, Unless Otherwise Specified PARAMETER TEST CONDITIONS TEMP ( o C) -2-4, -5, -9 MIN TYP MAX MIN TYP MAX UNITS DYNAMIC CHARACTERISTICS Switch ON Time, t ON (Note 3) ns Switch OFF Time, t OFF1 (Note 3) ns Switch OFF Time, t OFF2 (Note 3) ns Output Settling Time To.1% ns Charge Injection, Q (Note 6) pc OFF Isolation (Note 4) db Crosstalk (Note 5) db Input Switch Capacitance, C S(OFF) pf Output Switch Capacitance C D(OFF) pf C D(ON) pf Digital Input Capacitance, C A pf Drain-To-Source Capacitance, C DS(OFF) pf DIGITAL INPUT CHARACTERISTICS Input Low Threshold, V AL Full V Input High Threshold, V AH V Full V Input Leakage Current (Low), I AL A Full A Input Leakage Current (High), I AH V AH = 4.V A Full A ANALOG SWITCH CHARACTERISTICS Analog Signal Range, V S Full V ON Resistance, r ON (Note 2) Full FN3123 Rev 4. Page 4 of 12 September 24

5 HI-21HS Electrical Specifications Supplies = +15V, -15V; V AH (Logic Level High) = 2.4V, V AL (Logic Level Low) = +.8V, GND = V, Unless Otherwise Specified (Continued) PARAMETER TEST CONDITIONS TEMP ( o C) -2-4, -5, -9 MIN TYP MAX MIN TYP MAX UNITS r ON Match % OFF Input Leakage Current, I S(OFF) na Full na OFF Output Leakage Current, I D(OFF) na Full na ON Leakage Current, I D(ON) na Full na POWER SUPPLY CHARACTERISTICS (Note 7) Power Dissipation, P D mw Full mw Current, I+ (Pin 13) ma Full ma Current, I- (Pin 4) ma Full ma NOTES: 2. V OUT = 1V, I OUT = 1mA. 3. R L = 1k, C L = 35pF, V IN = +1V, V A = +3V. (See Figure 1). 4. V A = 3V, R L = 1k, C L = 1pF, V IN = 3V RMS, f = 1kHz. 5. V A = 3V, R L = 1k, V IN = 3V RMS, f = 1kHz. 6. C L = 1nF, V IN = V, Q = C L x V O. 7. V A = 3V or V A = for all switches. Test Circuits and Waveforms V DIGITAL AH = 3.V INPUT 5% V AL = V 5% t OFF1 t ON 9% 9% SWITCH OUTPUT V t OFF2 1% TOP: Logic Input (2V/Div.) BOTTOM: Output (5V/Div.) HORIZONTAL: 1ns/Div. FIGURE 1A. MEASUREMENT POINTS FIGURE 1B. WAVEFORMS FN3123 Rev 4. Page 5 of 12 September 24

6 HI-21HS Test Circuits and Waveforms (Continued) V+ = +15V SWITCH INPUT V IN = +1V SWITCH OUTPUT V O V A 1 R L 1k C L 35pF LOGIC INPUT 5 4 V- = -15V V O = V IN R L R L + r ON GND C L INCLUDES C FIXTURE + C PROBE FIGURE 1C. TEST CIRCUIT FIGURE 1. SWITCH t ON AND t OFF LOGIC INPUT (V) t t O O FIGURE 2A. LOGIC INPUT WAVEFORM FIGURE 2B. V IN = +1V t O t O FIGURE 2C. V IN = +5V FIGURE 2D. V IN = V FN3123 Rev 4. Page 6 of 12 September 24

7 HI-21HS Test Circuits and Waveforms (Continued) t O t O FIGURE 2E. V IN = -5V FIGURE 2F. V IN = -1V FIGURE 2. SWITCHING WAVEFORMS FOR VARIOUS ANALOG INPUT VOLTAGES Application Information Logic Compatibility The HI-21HS is TTL compatible. Its logic inputs (pins 1, 8, 9, and 16) are designed to react to digital inputs which exceed a fixed, internally generated TTL switching threshold. The HI-21HS can also be driven with CMOS logic (V-15V), although the switch performance with CMOS logic will be inferior to that with TTL logic (V-5V). The logic input design of the HI-21HS is largely responsible for its fast switching speed. It is a design which features a unique input stage consisting of complementary vertical PNP and NPN bipolar transistors. This design differs from that of the standard HI-21 product where the logic inputs are MOS transistors. Although the new logic design enhances the switching speed performance, it also increases the logic input leakage currents. Therefore, the HI-21HS will exhibit larger digital input leakage currents in comparison to the standard HI-21 product. Charge Injection Charge injection is the charge transferred, through the internal gate-to-channel capacitances, from the digital logic input to the analog output. To optimize charge injection performance for the HI-21HS, it is advisable to provide a TTL logic input with fast rise and fall times. If the power supplies are reduced from 15V, charge injection will become increasingly dependent upon the digital input frequency. Increased logic input frequency will result in larger output error due to charge injection. Power Supply Considerations The electrical characteristics specified in this data sheet are guaranteed for power supplies V S = 15V. Power supply voltages less than 15V will result in reduced switch performance. The following information is intended as a design aid only. POWER SUPPLY VOLTAGES 12 V S 15V V S < 12V V S < 1V V S > 16V SWITCH PERFORMANCE Minimal Variation Parametric variation becomes increasingly large (increased ON resistance, longer switching times). Not Recommended. Not Recommended. Single Supply The switch operation of the HI-21HS is dependent upon an internally generated switching threshold voltage optimized for 15V power supplies. The HI-21HS does not provide the necessary internal switching threshold in a single supply system. Therefore, if single supply operation is required, the HI-3 series of switches is recommended. The HI-3 series will remain operational to a minimum +5V single supply. Switch performance will degrade as power supply voltage is reduced from optimum levels ( 15V). So it is recommended that a single supply design be thoroughly evaluated to ensure that the switch will meet the requirements of the application. For further information see Application Notes AN52, AN521, AN531, AN532, AN543 and AN557. FN3123 Rev 4. Page 7 of 12 September 24

8 HI-21HS Typical Performance Curves T A = 25 o C V+ = +8V, V- = -8V ON RESISTANCE ( ) o C 25 o C -55 o C ON RESISTANCE ( ) V+ = +1V, V- = -1V V+ = +12V, V- = -12V ANALOG INPUT (V) ANALOG INPUT (V) FIGURE 3. ON RESISTANCE vs ANALOG SIGNAL LEVEL FIGURE 4. ON RESISTANCE vs ANALOG SIGNAL LEVEL LEAKAGE CURRENT (na) LEAKAGE CURRENT (na) TEMPERATURE ( o C) TEMPERATURE ( o C) FIGURE 5. I S(OFF) OR I D(OFF) vs TEMPERATURE FIGURE 6. I D(ON) vs TEMPERATURE Theoretically, leakage current will continue to decrease below 25 o C. But due to environmental conditions, leakage measurements below this temperature are not representative of actual switch performance. SUPPLY CURRENT (ma) I+ 4 I TEMPERATURE ( o C) LEAKAGE CURRENT (pa) I S(OFF) V D = V I D(OFF) V S = V -8 I DON I S(OFF) /I D(OFF) ANALOG INPUT (V) FIGURE 7. SUPPLY CURRENT vs TEMPERATURE FIGURE 8. LEAKAGE CURRENT vs ANALOG INPUT VOLTAGE FN3123 Rev 4. Page 8 of 12 September 24

9 HI-21HS Typical Performance Curves (Continued) LEAKAGE CURRENT ( A) V AL = V, V AH2 = 3V, V AH1 = 5V I AH I AH I AL TEMPERATURE ( o C) LEAKAGE CURRENT (na) 1 9, T A = 25 o C 8 I 7 S(OFF) V D = V 6 I D(OFF) V S = V ANALOG INPUT (V) FIGURE 9. DIGITAL INPUT LEAKAGE CURRENT vs TEMPERATURE FIGURE 1. LEAKAGE CURRENT vs ANALOG INPUT VOLTAGE Theoretically, leakage current will continue to decrease below 25 o C. But due to environmental conditions, leakage measurements below this temperature are not representative of actual switch performance. SWITCHING TIME (ns) t OFF2 t OFF1 t ON TEMPERATURE ( o C) 85 V+ = +15V V- = -15V R L = 1k C L = 35pF SWITCHING TIME (ns) 35 R L = 1k, C L = 35pF, T A = 25 o C t OFF t OFF1 t ON SUPPLY VOLTAGE ( V) FIGURE 11. SWITCHING TIME vs TEMPERATURE FIGURE 12. SWITCHING TIME vs SUPPLY VOLTAGE 35 3 V- = -15V, R L = 1k C L = 35pF, T A = 25 o C 35 3 V+ = +15V, R L = 1k C L = 35pF, T A = 25 o C SWITCHING TIME (ns) t OFF2 t OFF1 SWITCHING TIME (ns) t ON t OFF2 t OFF1 t ON POSITIVE SUPPLY (V) NEGATIVE SUPPLY (V) FIGURE 13. SWITCHING TIME vs POSITIVE SUPPLY VOLTAGE FIGURE 14. SWITCHING TIME vs NEGATIVE SUPPLY VOLTAGE FN3123 Rev 4. Page 9 of 12 September 24

10 HI-21HS Typical Performance Curves (Continued) SWITCHING TIME (ns) 35 V + = +15V, V- = -15V, R L = 1k 3 C L = 35pF, V AL = V, T A = 25 o C 25 2 t OFF t 5 OFF1 t ON DIGITAL INPUT VOLTAGE (V) INPUT LOGIC THRESHOLD (V) SUPPLY VOLTAGE ( V) FIGURE 15. SWITCHING TIME vs INPUT LOGIC VOLTAGE FIGURE 16. INPUT SWITCHING THRESHOLD vs SUPPLY VOLTAGE CHARGE INJECTION (pc) IN OUT V O V A Q = C L x V O C L -3-4 C L = 1nF ANALOG INPUT (V) Q CAPACITANCE (pf) 4 35 C D(ON) C D(OFF) OR C S(OFF) 1 5 C DS(OFF) ANALOG INPUT (V) FIGURE 17. CHARGE INJECTION vs ANALOG VOLTAGE FIGURE 18. CAPACITANCE vs ANALOG VOLTAGE V IN = 3V RMS, V A = 3V V IN = 3V RMS, V A = 3V OFF ISOLATION (db) IN OUT V O V IN R L OFF ISOLATION = 2 Log 1K 1K R L = 1 R L = 1k V IN V O 1M FREQUENCY (Hz) 1M CROSSTALK (db) 1 8 IN OUT V O1 6 V IN R L = 1k 4 V O2 R L = 1k 2 V O2 CROSSTALK = 2 Log V O1 1K 1K 1M FREQUENCY (Hz) 1M FIGURE 19. OFF ISOLATION vs FREQUENCY FIGURE 2. CROSSTALK vs FREQUENCY FN3123 Rev 4. Page 1 of 12 September 24

11 HI-21HS Die Characteristics DIE DIMENSIONS 244 m x 286 m x 485 m METALLIZATION Type: CuAl Thickness: 16kÅ 2kÅ PASSIVATION Type: Nitride Over Silox Nitride Thickness: 3.5kÅ 1kÅ Silox Thickness: 12kÅ 2kÅ WORST CASE CURRENT DENSITY 9.5 x 1 4 A/cm 2 Copyright Intersil Americas LLC 24. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see Intersil products are manufactured, assembled and tested utilizing ISO91 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see FN3123 Rev 4. Page 11 of 12 September 24

12 HI-21HS Metallization Mask Layout HI-21HS A1 A2 OUT1 OUT2 IN1 IN2 V- V+ GND IN4 IN3 OUT4 OUT3 A4 A3 FN3123 Rev 4. Page 12 of 12 September 24

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