DATASHEET HI-524. Features. Applications. Functional Diagram. Ordering Information. Pinout. 4-Channel Wideband and Video Multiplexer

Transcription

1 DATASHEET HI Channel Wideband and Video Multiplexer The HI-524 is a 4-Channel CMOS analog multiplexer designed to process single-ended signals with bandwidths up to 10MHz. The chip includes a 1 of 4 decoder for channel selection and an enable input to inhibit all channels (chip select). Three CMOS transmission gates are used in each channel, as compared to the single gate in more conventional CMOS multiplexers. This provides a double barrier to the unwanted coupling of signals from each input to the output. In addition, Dielectric Isolation (DI) processing helps to insure the Crosstalk is less than -60dB at 10MHz. The HI-524 is designed to operate into a wideband buffer amplifier such as the Intersil HA The multiplexer chip includes two ON switches in series, for use as a feedback element with the amplifier. This feedback resistance matches and tracks the channel ON resistance, to minimize the amplifier V OS and its variation with temperature. Features FN3148 Rev 3.00 Crosstalk (10MHz) < -60dB Fast Access Time ns Fast Settling Time ns TTL Compatible Applications Wideband Switching Radar TV Video ECM Functional Diagram The HI-524 is well suited to the rapid switching of video and other wideband signals in telemetry, instrumentation, radar and video systems. Ordering Information PART NUMBER Pinout TEMP. RANGE ( o C) PACKAGE PKG. NO. HI to Ld CERDIP F18.3 HI-524 (CERDIP) TOP VIEW FB (IN) FB () PUT +V SUPPLY A FB (IN) V FB () 9 10 A 0 1 OF 4 DECODER 1-15V SUP +15V A 0 A 1 TRUTH TABLE A 1 A 0 ON CHANNEL X X L None L L H 1 (Note) L H H 2 H L H 3 H H H 4 NOTE: Channel 1 is shown selected in the Functional Diagram. FN3148 Rev 3.00 Page 1 of 6

2 Absolute Maximum Ratings V+ to V V Digital Input Voltage (V, V A ) V to +6V Analog Signal (V IN, V ) (V-) -2V to (V+) +2V Either Supply to Ground V Operating Conditions Temperature Range HI o C to 75 o C Thermal Information Thermal Resistance (Typical, Note 1) JA ( o C/W) JC ( o C/W) CERDIP Package Maximum Junction Temperature Ceramic Package o C Maximum Storage Temperature o C to 150 o C Maximum Lead Temperature (Soldering, 10s) o C CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications Supplies = +15V, -15V; V AH (Logic Level High) = 2.4V, V AL (Logic Level Low) = 0.5V; V = 2.4V, Unless Otherwise Specified PARAMETER TEST CONDITIONS TEMP ( o C) -5 MIN TYP MAX UNITS DYNAMIC CHARACTERISTICS Access Time, t A Note ns Break-Before-Make Delay, t OP Note ns Enable Delay (ON), t ON () R L = ns Enable Delay (OFF), t OFF () R L = ns Settling Time (Note 5) To 0.1% ns To 0.01% ns Crosstalk Note db Channel Input Capacitance, C S(OFF) pf Channel Output Capacitance, C D(OFF) pf Digital Input Capacitance, C A pf DIGITAL INPUT SPECIFICATIONS Input Low Threshold (TTL), V AL Full V Input High Threshold (TTL), V AH Full V Input Leakage Current (High), I AH Full A Input Leakage Current (Low), I AL Full A ANALOG CHANNEL SPECIFICATIONS Analog Signal Range, V ln Full V On Resistance, r ON Note Full k Off Input Leakage Current, I S (OFF) Note na Full na Off Output Leakage Current, I D (OFF) Note na Full na On Channel Leakage Current, I D (ON) Note na Full na -3dB Bandwidth Note MHz FN3148 Rev 3.00 Page 2 of 6

3 Electrical Specifications Supplies = +15V, -15V; V AH (Logic Level High) = 2.4V, V AL (Logic Level Low) = 0.5V; V = 2.4V, Unless Otherwise Specified (Continued) PARAMETER TEST CONDITIONS TEMP ( o C) -5 MIN TYP MAX UNITS POWER SUPPLY CHARACTERISTICS Power Dissipation, P D Full mw Current, I+ Note 7 Full ma Current, I- Note 7 Full ma NOTES: 2. V ln = 0V; l = 100A (See Test Circuit section). 3. V O = 10V; V IN = 10V. (See Test Circuit section). 4. MUX output is buffered with HA-5033 amplifier. 5. 6V Step, 3V to 3V, See Test Circuit section. 6. V IN = 10MHz, 3V P-P on one channel, with any other channel selected. (Worst case is channel 3 selected with input on channel 4.) MUX output is buffered with HA-2541 as shown in Applications section. Terminate all channels with Supply currents vary less than 0.5mA for switching rates from DC to 2MHz. Test Circuits and Waveforms T A = 25 o C, V SUPPLY = 15V, V AH = 2.4V, V AL = 0.8V, Unless Otherwise Specified I 100A V 2 IN V IN ron = V 2 100A FIGURE 1A. TEST CIRCUIT 1, o C 1,000 V IN = 0V r ON () o C r ON () o C V IN (V) SUPPLY VOLTAGE (V) FIGURE 1B. ON RESISTANCE vs ANALOG INPUT VOLTAGE FIGURE 1C. ON RESISTANCE vs SUPPLY VOLTAGE FIGURE 1. ON RESISTANCE FN3148 Rev 3.00 Page 3 of 6

4 Test Circuits and Waveforms T A = 25 o C, V SUPPLY = 15V, V AH = 2.4V, V AL = 0.8V, Unless Otherwise Specified (Continued) LEAKAGE CURRT (na) 1.0 I S(OFF) I D(ON) I D(OFF) 0.8V A I D(OFF) 10V TEMPERATURE ( o C) FIGURE 2A. LEAKAGE CURRT vs TEMPERATURE FIGURE 2B. I D(OFF) TEST CIRCUIT (NOTE 8) 10V A I S(OFF) 0.8V A 0 A 1 A I D(ON) 10V 10V 10V 10V +2.4V FIGURE 2C. I S(OFF) TEST CIRCUIT (NOTE 8) FIGURE 2D. I D(ON) TEST CIRCUIT (NOTE 8) FIGURE 2. LEAKAGE CURRTS HA-524 3V HA pF (NOTE 10) PUT 75 +3V 1.6V ADDRESS DRIVE (V A ) V AH = 2.4V V AL = 0.8V ACCESS TIME, t A 3V SETTLING TIME, t S A 0 A 1 5V HA-2541 PUT 10% -3V V A % OF FULL SCALE (OR 0.01%) FIGURE 3A. TEST CIRCUIT FIGURE 3B. MEASUREMT POINTS FIGURE 3. SETTLING TIME, ACCESS TIME, BREAK-BEFORE-MAKE DELAY (NOTE 9) NOTES: 8. Two measurements per channel: 10V and 10V. (Two measurements per device for I D(OFF) 10V and 10V.) 9. The Break-Before-Make test requires inputs 1 and 4 at the same voltage. 10. Capacitor value may be selected to optimize AC performance. FN3148 Rev 3.00 Page 4 of 6

5 Test Circuits and Waveforms T A = 25 o C, V SUPPLY = 15V, V AH = 2.4V, V AL = 0.8V, Unless Otherwise Specified (Continued) V A INPUT 5V/DIV. S 1 ON S 4 ON 1V/DIV. PUT 50ns/DIV. FIGURE 4. ACCESS TIME WAVEFORMS Application Information Often it is desirable to buffer the Hl-524 output, to avoid loading errors due to the channel ON resistance: CH HA-524 Note that the on-chip feedback element between pins 16 and 18 includes two switches in series, to simulate a channel resistance. These switches open for V = Low. This allows two or more Hl-524s to operate into one HA-2541, with their feedback elements connected in parallel. Thus, only the selected multiplexer provides feedback, and the amplifier remains stable. CH2 75 CH HA pF(NOTE) BUFFERED PUT All Hl-524 pins labeled SlG (pins 3, 4, 6, 13, 15) should be externally connected to signal ground for best crosstalk performance. Bypass capacitors (0.1F to 1F) are recommended from each HI-524 supply pin to power ground (pins 1 and 17 to pin 8). Locate the buffer amplifier near the Hl-524 so the two capacitors may bypass both devices. 5 CH4 75 NOTE: Capacitor value may be selected to optimize AC performance. FIGURE 5. If an analog input 1V or greater is present when supplies are off, a low resistance is seen from that input to a supply line. (For example, the resistance is approximately 160 for an input of -3V.) Current flow may be blocked by a diode in each supply line, or limited by a resistor in series with each channel. The best solution, of course, is to arrange that no digital or analog inputs are present when the power supplies are off. The buffer amplifier should offer sufficient bandwidth and slew rate to avoid degradation of the anticipated signals. For video switching, the HA-5033 and HA-2542 offer good performance plus 100mA output current for driving coaxial cables. For general wideband applications, the HA-2541 offers the convenience of unity gain stability plus 90ns settling (to 0.1%) and 10V output swing. Also, the Hl-524 includes a feedback resistance for use with the HA This resistance matches and tracks the channel ON resistance, to minimize offset voltage due to the buffer's bias currents. FN3148 Rev 3.00 Page 5 of 6

6 Die Characteristics DIE DIMSIONS: 2250m x 3720m x 485m METALLIZATION: Type: CuAl Thickness: 16kÅ 2kÅ PASSIVATION: Type: Nitride Over Silox Nitride Thickness: 3.5kÅ 1kÅ Silox Thickness: 12kÅ 2kÅ WORST CASE CURRT DSITY: 1.58 x 10 5 A/cm 2 Metallization Mask Layout HI-524 AO A1 SUPPLY FB () -V FB (IN) +V Copyright Intersil Americas LLC All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see FN3148 Rev 3.00 Page 6 of 6